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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <asm/m52xxacr.h>Go to the source code of this file.
Macros | |
| #define | CPU_NAME "COLDFIRE(m520x)" |
| #define | CPU_INSTR_PER_JIFFY 3 |
| #define | MCF_BUSCLK (MCF_CLK / 2) |
| #define | MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ |
| #define | MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| #define | MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| #define | MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| #define | MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| #define | MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| #define | MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| #define | MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ |
| #define | MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ |
| #define | MCFINTC_ICR0 0x40 /* Base ICR register */ |
| #define | MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) |
| #define | MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) |
| #define | MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) |
| #define | MCFINTC1_SIMR (0) |
| #define | MCFINTC1_CIMR (0) |
| #define | MCFINTC1_ICR0 (0) |
| #define | MCFINTC2_SIMR (0) |
| #define | MCFINTC2_CIMR (0) |
| #define | MCFINTC2_ICR0 (0) |
| #define | MCFINT_VECBASE 64 |
| #define | MCFINT_UART0 26 /* Interrupt number for UART0 */ |
| #define | MCFINT_UART1 27 /* Interrupt number for UART1 */ |
| #define | MCFINT_UART2 28 /* Interrupt number for UART2 */ |
| #define | MCFINT_QSPI 31 /* Interrupt number for QSPI */ |
| #define | MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ |
| #define | MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ |
| #define | MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */ |
| #define | MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ |
| #define | MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
| #define | MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
| #define | MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
| #define | MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
| #define | MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
| #define | MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| #define | MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| #define | MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
| #define | MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ |
| #define | MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ |
| #define | MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ |
| #define | MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ |
| #define | MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ |
| #define | MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ |
| #define | MCFEPORT_EPPAR 0xFC088000 |
| #define | MCFEPORT_EPDDR 0xFC088002 |
| #define | MCFEPORT_EPIER 0xFC088003 |
| #define | MCFEPORT_EPDR 0xFC088004 |
| #define | MCFEPORT_EPPDR 0xFC088005 |
| #define | MCFEPORT_EPFR 0xFC088006 |
| #define | MCFGPIO_PODR_BUSCTL 0xFC0A4000 |
| #define | MCFGPIO_PODR_BE 0xFC0A4001 |
| #define | MCFGPIO_PODR_CS 0xFC0A4002 |
| #define | MCFGPIO_PODR_FECI2C 0xFC0A4003 |
| #define | MCFGPIO_PODR_QSPI 0xFC0A4004 |
| #define | MCFGPIO_PODR_TIMER 0xFC0A4005 |
| #define | MCFGPIO_PODR_UART 0xFC0A4006 |
| #define | MCFGPIO_PODR_FECH 0xFC0A4007 |
| #define | MCFGPIO_PODR_FECL 0xFC0A4008 |
| #define | MCFGPIO_PDDR_BUSCTL 0xFC0A400C |
| #define | MCFGPIO_PDDR_BE 0xFC0A400D |
| #define | MCFGPIO_PDDR_CS 0xFC0A400E |
| #define | MCFGPIO_PDDR_FECI2C 0xFC0A400F |
| #define | MCFGPIO_PDDR_QSPI 0xFC0A4010 |
| #define | MCFGPIO_PDDR_TIMER 0xFC0A4011 |
| #define | MCFGPIO_PDDR_UART 0xFC0A4012 |
| #define | MCFGPIO_PDDR_FECH 0xFC0A4013 |
| #define | MCFGPIO_PDDR_FECL 0xFC0A4014 |
| #define | MCFGPIO_PPDSDR_CS 0xFC0A401A |
| #define | MCFGPIO_PPDSDR_FECI2C 0xFC0A401B |
| #define | MCFGPIO_PPDSDR_QSPI 0xFC0A401C |
| #define | MCFGPIO_PPDSDR_TIMER 0xFC0A401D |
| #define | MCFGPIO_PPDSDR_UART 0xFC0A401E |
| #define | MCFGPIO_PPDSDR_FECH 0xFC0A401F |
| #define | MCFGPIO_PPDSDR_FECL 0xFC0A4020 |
| #define | MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 |
| #define | MCFGPIO_PCLRR_BE 0xFC0A4025 |
| #define | MCFGPIO_PCLRR_CS 0xFC0A4026 |
| #define | MCFGPIO_PCLRR_FECI2C 0xFC0A4027 |
| #define | MCFGPIO_PCLRR_QSPI 0xFC0A4028 |
| #define | MCFGPIO_PCLRR_TIMER 0xFC0A4029 |
| #define | MCFGPIO_PCLRR_UART 0xFC0A402A |
| #define | MCFGPIO_PCLRR_FECH 0xFC0A402B |
| #define | MCFGPIO_PCLRR_FECL 0xFC0A402C |
| #define | MCFGPIO_PODR MCFGPIO_PODR_CS |
| #define | MCFGPIO_PDDR MCFGPIO_PDDR_CS |
| #define | MCFGPIO_PPDR MCFGPIO_PPDSDR_CS |
| #define | MCFGPIO_SETR MCFGPIO_PPDSDR_CS |
| #define | MCFGPIO_CLRR MCFGPIO_PCLRR_CS |
| #define | MCFGPIO_PIN_MAX 80 |
| #define | MCFGPIO_IRQ_MAX 8 |
| #define | MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| #define | MCF_GPIO_PAR_UART 0xFC0A4036 |
| #define | MCF_GPIO_PAR_FECI2C 0xFC0A4033 |
| #define | MCF_GPIO_PAR_QSPI 0xFC0A4034 |
| #define | MCF_GPIO_PAR_FEC 0xFC0A4038 |
| #define | MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) |
| #define | MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) |
| #define | MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) |
| #define | MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) |
| #define | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) |
| #define | MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) |
| #define | MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ |
| #define | MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ |
| #define | MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ |
| #define | MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ |
| #define | MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ |
| #define | MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ |
| #define | MCFFEC_SIZE0 0x800 /* Register set size */ |
| #define | MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ |
| #define | MCFQSPI_SIZE 0x40 /* Register set size */ |
| #define | MCFQSPI_CS0 46 |
| #define | MCFQSPI_CS1 47 |
| #define | MCFQSPI_CS2 27 |
| #define | MCF_RCR 0xFC0A0000 |
| #define | MCF_RSR 0xFC0A0001 |
| #define | MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| #define | MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| #define | MCFPM_WCR 0xfc040013 |
| #define | MCFPM_PPMSR0 0xfc04002c |
| #define | MCFPM_PPMCR0 0xfc04002d |
| #define | MCFPM_PPMHR0 0xfc040030 |
| #define | MCFPM_PPMLR0 0xfc040034 |
| #define | MCFPM_LPCR 0xfc0a0007 |
| #define CPU_INSTR_PER_JIFFY 3 |
Definition at line 15 of file m520xsim.h.
| #define CPU_NAME "COLDFIRE(m520x)" |
Definition at line 14 of file m520xsim.h.
| #define MCF_BUSCLK (MCF_CLK / 2) |
Definition at line 16 of file m520xsim.h.
| #define MCF_GPIO_PAR_FEC 0xFC0A4038 |
Definition at line 144 of file m520xsim.h.
| #define MCF_GPIO_PAR_FECI2C 0xFC0A4033 |
Definition at line 142 of file m520xsim.h.
| #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) |
Definition at line 153 of file m520xsim.h.
| #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) |
Definition at line 152 of file m520xsim.h.
| #define MCF_GPIO_PAR_QSPI 0xFC0A4034 |
Definition at line 143 of file m520xsim.h.
| #define MCF_GPIO_PAR_UART 0xFC0A4036 |
Definition at line 141 of file m520xsim.h.
| #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) |
Definition at line 146 of file m520xsim.h.
| #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) |
Definition at line 149 of file m520xsim.h.
| #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) |
Definition at line 147 of file m520xsim.h.
| #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) |
Definition at line 150 of file m520xsim.h.
| #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
Definition at line 65 of file m520xsim.h.
| #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
Definition at line 63 of file m520xsim.h.
| #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
Definition at line 64 of file m520xsim.h.
| #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
Definition at line 68 of file m520xsim.h.
| #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
Definition at line 67 of file m520xsim.h.
| #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
Definition at line 59 of file m520xsim.h.
| #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
Definition at line 60 of file m520xsim.h.
| #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
Definition at line 61 of file m520xsim.h.
| #define MCF_RCR 0xFC0A0000 |
Definition at line 187 of file m520xsim.h.
| #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
Definition at line 191 of file m520xsim.h.
| #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
Definition at line 190 of file m520xsim.h.
| #define MCF_RSR 0xFC0A0001 |
Definition at line 188 of file m520xsim.h.
| #define MCFEPORT_EPDDR 0xFC088002 |
Definition at line 84 of file m520xsim.h.
| #define MCFEPORT_EPDR 0xFC088004 |
Definition at line 86 of file m520xsim.h.
| #define MCFEPORT_EPFR 0xFC088006 |
Definition at line 88 of file m520xsim.h.
| #define MCFEPORT_EPIER 0xFC088003 |
Definition at line 85 of file m520xsim.h.
| #define MCFEPORT_EPPAR 0xFC088000 |
Definition at line 83 of file m520xsim.h.
| #define MCFEPORT_EPPDR 0xFC088005 |
Definition at line 87 of file m520xsim.h.
| #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ |
Definition at line 171 of file m520xsim.h.
| #define MCFFEC_SIZE0 0x800 /* Register set size */ |
Definition at line 172 of file m520xsim.h.
| #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS |
Definition at line 135 of file m520xsim.h.
| #define MCFGPIO_IRQ_MAX 8 |
Definition at line 138 of file m520xsim.h.
| #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
Definition at line 139 of file m520xsim.h.
| #define MCFGPIO_PCLRR_BE 0xFC0A4025 |
Definition at line 119 of file m520xsim.h.
| #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 |
Definition at line 118 of file m520xsim.h.
| #define MCFGPIO_PCLRR_CS 0xFC0A4026 |
Definition at line 120 of file m520xsim.h.
| #define MCFGPIO_PCLRR_FECH 0xFC0A402B |
Definition at line 125 of file m520xsim.h.
| #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 |
Definition at line 121 of file m520xsim.h.
| #define MCFGPIO_PCLRR_FECL 0xFC0A402C |
Definition at line 126 of file m520xsim.h.
| #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 |
Definition at line 122 of file m520xsim.h.
| #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 |
Definition at line 123 of file m520xsim.h.
| #define MCFGPIO_PCLRR_UART 0xFC0A402A |
Definition at line 124 of file m520xsim.h.
| #define MCFGPIO_PDDR MCFGPIO_PDDR_CS |
Definition at line 132 of file m520xsim.h.
| #define MCFGPIO_PDDR_BE 0xFC0A400D |
Definition at line 101 of file m520xsim.h.
| #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C |
Definition at line 100 of file m520xsim.h.
| #define MCFGPIO_PDDR_CS 0xFC0A400E |
Definition at line 102 of file m520xsim.h.
| #define MCFGPIO_PDDR_FECH 0xFC0A4013 |
Definition at line 107 of file m520xsim.h.
| #define MCFGPIO_PDDR_FECI2C 0xFC0A400F |
Definition at line 103 of file m520xsim.h.
| #define MCFGPIO_PDDR_FECL 0xFC0A4014 |
Definition at line 108 of file m520xsim.h.
| #define MCFGPIO_PDDR_QSPI 0xFC0A4010 |
Definition at line 104 of file m520xsim.h.
| #define MCFGPIO_PDDR_TIMER 0xFC0A4011 |
Definition at line 105 of file m520xsim.h.
| #define MCFGPIO_PDDR_UART 0xFC0A4012 |
Definition at line 106 of file m520xsim.h.
| #define MCFGPIO_PIN_MAX 80 |
Definition at line 137 of file m520xsim.h.
| #define MCFGPIO_PODR MCFGPIO_PODR_CS |
Definition at line 131 of file m520xsim.h.
| #define MCFGPIO_PODR_BE 0xFC0A4001 |
Definition at line 91 of file m520xsim.h.
| #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 |
Definition at line 90 of file m520xsim.h.
| #define MCFGPIO_PODR_CS 0xFC0A4002 |
Definition at line 92 of file m520xsim.h.
| #define MCFGPIO_PODR_FECH 0xFC0A4007 |
Definition at line 97 of file m520xsim.h.
| #define MCFGPIO_PODR_FECI2C 0xFC0A4003 |
Definition at line 93 of file m520xsim.h.
| #define MCFGPIO_PODR_FECL 0xFC0A4008 |
Definition at line 98 of file m520xsim.h.
| #define MCFGPIO_PODR_QSPI 0xFC0A4004 |
Definition at line 94 of file m520xsim.h.
| #define MCFGPIO_PODR_TIMER 0xFC0A4005 |
Definition at line 95 of file m520xsim.h.
| #define MCFGPIO_PODR_UART 0xFC0A4006 |
Definition at line 96 of file m520xsim.h.
| #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS |
Definition at line 133 of file m520xsim.h.
| #define MCFGPIO_PPDSDR_CS 0xFC0A401A |
Definition at line 110 of file m520xsim.h.
| #define MCFGPIO_PPDSDR_FECH 0xFC0A401F |
Definition at line 115 of file m520xsim.h.
| #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B |
Definition at line 111 of file m520xsim.h.
| #define MCFGPIO_PPDSDR_FECL 0xFC0A4020 |
Definition at line 116 of file m520xsim.h.
| #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C |
Definition at line 112 of file m520xsim.h.
| #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D |
Definition at line 113 of file m520xsim.h.
| #define MCFGPIO_PPDSDR_UART 0xFC0A401E |
Definition at line 114 of file m520xsim.h.
| #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS |
Definition at line 134 of file m520xsim.h.
| #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ |
Definition at line 23 of file m520xsim.h.
Definition at line 56 of file m520xsim.h.
Definition at line 54 of file m520xsim.h.
Definition at line 55 of file m520xsim.h.
Definition at line 57 of file m520xsim.h.
Definition at line 53 of file m520xsim.h.
Definition at line 50 of file m520xsim.h.
Definition at line 51 of file m520xsim.h.
Definition at line 52 of file m520xsim.h.
| #define MCFINT_VECBASE 64 |
Definition at line 49 of file m520xsim.h.
| #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) |
Definition at line 40 of file m520xsim.h.
| #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) |
Definition at line 41 of file m520xsim.h.
| #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) |
Definition at line 39 of file m520xsim.h.
| #define MCFINTC1_CIMR (0) |
Definition at line 43 of file m520xsim.h.
| #define MCFINTC1_ICR0 (0) |
Definition at line 44 of file m520xsim.h.
| #define MCFINTC1_SIMR (0) |
Definition at line 42 of file m520xsim.h.
| #define MCFINTC2_CIMR (0) |
Definition at line 46 of file m520xsim.h.
| #define MCFINTC2_ICR0 (0) |
Definition at line 47 of file m520xsim.h.
| #define MCFINTC2_SIMR (0) |
Definition at line 45 of file m520xsim.h.
| #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ |
Definition at line 31 of file m520xsim.h.
| #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
Definition at line 32 of file m520xsim.h.
| #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
Definition at line 26 of file m520xsim.h.
| #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
Definition at line 27 of file m520xsim.h.
| #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
Definition at line 28 of file m520xsim.h.
| #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
Definition at line 29 of file m520xsim.h.
| #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
Definition at line 24 of file m520xsim.h.
| #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
Definition at line 25 of file m520xsim.h.
| #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ |
Definition at line 30 of file m520xsim.h.
| #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ |
Definition at line 158 of file m520xsim.h.
| #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ |
Definition at line 159 of file m520xsim.h.
| #define MCFPM_LPCR 0xfc0a0007 |
Definition at line 201 of file m520xsim.h.
| #define MCFPM_PPMCR0 0xfc04002d |
Definition at line 198 of file m520xsim.h.
| #define MCFPM_PPMHR0 0xfc040030 |
Definition at line 199 of file m520xsim.h.
| #define MCFPM_PPMLR0 0xfc040034 |
Definition at line 200 of file m520xsim.h.
| #define MCFPM_PPMSR0 0xfc04002c |
Definition at line 197 of file m520xsim.h.
| #define MCFPM_WCR 0xfc040013 |
Definition at line 196 of file m520xsim.h.
| #define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ |
Definition at line 177 of file m520xsim.h.
| #define MCFQSPI_CS0 46 |
Definition at line 180 of file m520xsim.h.
| #define MCFQSPI_CS1 47 |
Definition at line 181 of file m520xsim.h.
| #define MCFQSPI_CS2 27 |
Definition at line 182 of file m520xsim.h.
| #define MCFQSPI_SIZE 0x40 /* Register set size */ |
Definition at line 178 of file m520xsim.h.
| #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ |
Definition at line 75 of file m520xsim.h.
| #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ |
Definition at line 76 of file m520xsim.h.
| #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ |
Definition at line 74 of file m520xsim.h.
| #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ |
Definition at line 77 of file m520xsim.h.
| #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ |
Definition at line 78 of file m520xsim.h.
| #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ |
Definition at line 73 of file m520xsim.h.
| #define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ |
Definition at line 164 of file m520xsim.h.
| #define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ |
Definition at line 165 of file m520xsim.h.
| #define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ |
Definition at line 166 of file m520xsim.h.
1.8.2