Linux Kernel
3.7.1
|
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfdma.h>
#include <asm/mcfwdebug.h>
#include <asm/mcfclk.h>
Go to the source code of this file.
Macros | |
#define | MAX_FVCO 500000 /* KHz */ |
#define | MAX_FSYS 80000 /* KHz */ |
#define | MIN_FSYS 58333 /* KHz */ |
#define | FREF 16000 /* KHz */ |
#define | MAX_MFD 135 /* Multiplier */ |
#define | MIN_MFD 88 /* Multiplier */ |
#define | BUSDIV 6 /* Divider */ |
#define | MIN_LPD (1 << 0) /* Divider (not encoded) */ |
#define | MAX_LPD (1 << 15) /* Divider (not encoded) */ |
#define | DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ |
#define | SYS_CLK_KHZ 80000 |
#define | SYSTEM_PERIOD 12.5 |
#define | SDRAM_BL 8 /* # of beats in a burst */ |
#define | SDRAM_TWR 2 /* in clocks */ |
#define | SDRAM_CASL 2.5 /* CASL in clocks */ |
#define | SDRAM_TRCD 2 /* in clocks */ |
#define | SDRAM_TRP 2 /* in clocks */ |
#define | SDRAM_TRFC 7 /* in clocks */ |
#define | SDRAM_TREFI 7800 /* in ns */ |
#define | EXT_SRAM_ADDRESS (0xC0000000) |
#define | FLASH_ADDRESS (0x00000000) |
#define | SDRAM_ADDRESS (0x40000000) |
#define | NAND_FLASH_ADDRESS (0xD0000000) |
#define | MCF_SCM_BCR_GBW (0x00000100) |
#define | MCF_SCM_BCR_GBR (0x00000200) |
Functions | |
DEFINE_CLK (0,"flexbus", 2, MCF_CLK) | |
DEFINE_CLK (0,"mcfcan.0", 8, MCF_CLK) | |
DEFINE_CLK (0,"fec.0", 12, MCF_CLK) | |
DEFINE_CLK (0,"edma", 17, MCF_CLK) | |
DEFINE_CLK (0,"intc.0", 18, MCF_CLK) | |
DEFINE_CLK (0,"intc.1", 19, MCF_CLK) | |
DEFINE_CLK (0,"iack.0", 21, MCF_CLK) | |
DEFINE_CLK (0,"mcfi2c.0", 22, MCF_CLK) | |
DEFINE_CLK (0,"mcfqspi.0", 23, MCF_CLK) | |
DEFINE_CLK (0,"mcfuart.0", 24, MCF_BUSCLK) | |
DEFINE_CLK (0,"mcfuart.1", 25, MCF_BUSCLK) | |
DEFINE_CLK (0,"mcfuart.2", 26, MCF_BUSCLK) | |
DEFINE_CLK (0,"mcftmr.0", 28, MCF_CLK) | |
DEFINE_CLK (0,"mcftmr.1", 29, MCF_CLK) | |
DEFINE_CLK (0,"mcftmr.2", 30, MCF_CLK) | |
DEFINE_CLK (0,"mcftmr.3", 31, MCF_CLK) | |
DEFINE_CLK (0,"mcfpit.0", 32, MCF_CLK) | |
DEFINE_CLK (0,"mcfpit.1", 33, MCF_CLK) | |
DEFINE_CLK (0,"mcfpit.2", 34, MCF_CLK) | |
DEFINE_CLK (0,"mcfpit.3", 35, MCF_CLK) | |
DEFINE_CLK (0,"mcfpwm.0", 36, MCF_CLK) | |
DEFINE_CLK (0,"mcfeport.0", 37, MCF_CLK) | |
DEFINE_CLK (0,"mcfwdt.0", 38, MCF_CLK) | |
DEFINE_CLK (0,"sys.0", 40, MCF_BUSCLK) | |
DEFINE_CLK (0,"gpio.0", 41, MCF_BUSCLK) | |
DEFINE_CLK (0,"mcfrtc.0", 42, MCF_CLK) | |
DEFINE_CLK (0,"mcflcd.0", 43, MCF_CLK) | |
DEFINE_CLK (0,"mcfusb-otg.0", 44, MCF_CLK) | |
DEFINE_CLK (0,"mcfusb-host.0", 45, MCF_CLK) | |
DEFINE_CLK (0,"sdram.0", 46, MCF_CLK) | |
DEFINE_CLK (0,"ssi.0", 47, MCF_CLK) | |
DEFINE_CLK (0,"pll.0", 48, MCF_CLK) | |
DEFINE_CLK (1,"mdha.0", 32, MCF_CLK) | |
DEFINE_CLK (1,"skha.0", 33, MCF_CLK) | |
DEFINE_CLK (1,"rng.0", 34, MCF_CLK) | |
void __init | config_BSP (char *commandp, int size) |
void | wtm_init (void) |
void | scm_init (void) |
void | gpio_init (void) |
void | fbcs_init (void) |
void | sdramc_init (void) |
int | clock_pll (int fsys, int flags) |
int | clock_limp (int) |
int | clock_exit_limp (void) |
int | get_sys_clock (void) |
asmlinkage void __init | sysinit (void) |
Variables | |
struct clk * | mcf_clks [] |
int | sys_clk_khz = 0 |
int | sys_clk_mhz = 0 |
DEFINE_CLK | ( | 0 | , |
"flexbus" | , | ||
2 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfcan.0" | , | ||
8 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"fec.0" | , | ||
12 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"edma" | , | ||
17 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"intc.0" | , | ||
18 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"intc.1" | , | ||
19 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"iack.0" | , | ||
21 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfi2c.0" | , | ||
22 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfqspi.0" | , | ||
23 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfuart.0" | , | ||
24 | , | ||
MCF_BUSCLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfuart.1" | , | ||
25 | , | ||
MCF_BUSCLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfuart.2" | , | ||
26 | , | ||
MCF_BUSCLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcftmr.0" | , | ||
28 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcftmr.1" | , | ||
29 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcftmr.2" | , | ||
30 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcftmr.3" | , | ||
31 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfpit.0" | , | ||
32 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfpit.1" | , | ||
33 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfpit.2" | , | ||
34 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfpit.3" | , | ||
35 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfpwm.0" | , | ||
36 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfeport.0" | , | ||
37 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfwdt.0" | , | ||
38 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"sys.0" | , | ||
40 | , | ||
MCF_BUSCLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"gpio.0" | , | ||
41 | , | ||
MCF_BUSCLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfrtc.0" | , | ||
42 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcflcd.0" | , | ||
43 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfusb-otg.0" | , | ||
44 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"mcfusb-host.0" | , | ||
45 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"sdram.0" | , | ||
46 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"ssi.0" | , | ||
47 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 0 | , |
"pll.0" | , | ||
48 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 1 | , |
"mdha.0" | , | ||
32 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 1 | , |
"skha.0" | , | ||
33 | , | ||
MCF_CLK | |||
) |
DEFINE_CLK | ( | 1 | , |
"rng.0" | , | ||
34 | , | ||
MCF_CLK | |||
) |