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| #define | VIA1_BASE (0x50F00000) |
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| #define | VIA2_BASE (0x50F02000) |
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| #define | RBV_BASE (0x50F26000) |
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| #define | VIA1A_vSccWrReq |
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| #define | VIA1A_vRev8 |
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| #define | VIA1A_vHeadSel |
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| #define | VIA1A_vOverlay |
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| #define | VIA1A_vSync |
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| #define | VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ |
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| #define | VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ |
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| #define | VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ |
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| #define | VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ |
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| #define | VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ |
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| #define | VIA1B_vSound |
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| #define | VIA1B_vMystery |
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| #define | VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ |
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| #define | VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ |
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| #define | VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ |
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| #define | VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ |
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| #define | VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ |
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| #define | VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ |
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| #define | EVRB_XCVR 0x08 /* XCVR_SESSION* */ |
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| #define | EVRB_FULL 0x10 /* VIA_FULL */ |
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| #define | EVRB_SYSES 0x20 /* SYS_SESSION */ |
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| #define | EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */ |
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| #define | EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */ |
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| #define | EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */ |
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| #define | EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */ |
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| #define | VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ |
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| #define | VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ |
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| #define | VIA2A_vIRQE 0x20 /* IRQ from slot $E */ |
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| #define | VIA2A_vIRQD 0x10 /* IRQ from slot $D */ |
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| #define | VIA2A_vIRQC 0x08 /* IRQ from slot $C */ |
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| #define | VIA2A_vIRQB 0x04 /* IRQ from slot $B */ |
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| #define | VIA2A_vIRQA 0x02 /* IRQ from slot $A */ |
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| #define | VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ |
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| #define | VIA2B_vVBL |
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| #define | VIA2B_vSndJck |
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| #define | VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ |
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| #define | VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ |
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| #define | VIA2B_vMode32 |
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| #define | VIA2B_vPower |
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| #define | VIA2B_vBusLk |
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| #define | VIA2B_vCDis |
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| #define | vBufB 0x0000 /* [VIA/RBV] Register B */ |
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| #define | vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ |
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| #define | vDirB 0x0400 /* [VIA only] Data Direction Register B. */ |
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| #define | vDirA 0x0600 /* [VIA only] Data Direction Register A. */ |
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| #define | vT1CL 0x0800 /* [VIA only] Timer one counter low. */ |
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| #define | vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ |
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| #define | vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ |
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| #define | vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ |
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| #define | vT2CL 0x1000 /* [VIA only] Timer two counter low. */ |
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| #define | vT2CH 0x1200 /* [VIA only] Timer two counter high. */ |
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| #define | vSR 0x1400 /* [VIA only] Shift register. */ |
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| #define | vACR 0x1600 /* [VIA only] Auxiliary control register. */ |
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| #define | vPCR 0x1800 /* [VIA only] Peripheral control register. */ |
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| #define | vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ |
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| #define | vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ |
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| #define | vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ |
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| #define | rBufB 0x0000 /* [VIA/RBV] Register B */ |
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| #define | rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */ |
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| #define | rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */ |
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| #define | rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */ |
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| #define | rMonP 0x0010 /* [RBV only] RBV video monitor type. */ |
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| #define | rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */ |
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| #define | rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */ |
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| #define | rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */ |
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| #define | rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */ |
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| #define | RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */ |
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| #define | RBV_MONID 0x38 /* monitor type, as below. */ |
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| #define | RBV_VIDOFF 0x40 /* 1 turns off onboard video */ |
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| #define | MON_15BW (1<<3) /* 15" BW portrait. */ |
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| #define | MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */ |
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| #define | MON_15RGB (5<<3) /* 15" RGB portrait. */ |
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| #define | MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */ |
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| #define | MON_NONE (7<<3) /* No monitor attached. */ |
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| #define | IER_SET_BIT(b) (0x80 | (1<<(b)) ) |
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| #define | IER_CLR_BIT(b) (0x7F & (1<<(b)) ) |
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1.8.2