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pic.h File Reference

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Macros

#define PIC_CTRL   0x00
 
#define PIC_CTRL_ITV   32 /* interrupt timeout value */
 
#define PIC_CTRL_ICI   19 /* ICI interrupt timeout enable */
 
#define PIC_CTRL_ITE   18 /* interrupt timeout enable */
 
#define PIC_CTRL_STE   10 /* system timer interrupt enable */
 
#define PIC_CTRL_WWR1   8 /* watchdog 1 wraparound count for reset */
 
#define PIC_CTRL_WWR0   6 /* watchdog 0 wraparound count for reset */
 
#define PIC_CTRL_WWN1   4 /* watchdog 1 wraparound count for NMI */
 
#define PIC_CTRL_WWN0   2 /* watchdog 0 wraparound count for NMI */
 
#define PIC_CTRL_WTE   0 /* watchdog timer enable */
 
#define PIC_ICI_STATUS   33 /* ICI interrupt timeout status */
 
#define PIC_ITE_STATUS   32 /* interrupt timeout status */
 
#define PIC_STS_STATUS   4 /* System timer interrupt status */
 
#define PIC_WNS_STATUS   2 /* NMI status for watchdog timers */
 
#define PIC_WIS_STATUS   0 /* Interrupt status for watchdog timers */
 
#define PIC_IPICTRL_NMI   32
 
#define PIC_IPICTRL_RIV   20 /* received interrupt vector */
 
#define PIC_IPICTRL_IDB   16 /* interrupt destination base */
 
#define PIC_IPICTRL_DTE   0 /* interrupt destination thread enables */
 
#define PIC_IRT_ENABLE   31
 
#define PIC_IRT_NMI   29
 
#define PIC_IRT_SCH   28 /* Scheduling scheme */
 
#define PIC_IRT_RVEC   20 /* Interrupt receive vectors */
 
#define PIC_IRT_DT   19 /* Destination type */
 
#define PIC_IRT_DB   16 /* Destination base */
 
#define PIC_IRT_DTE   0 /* Destination thread enables */
 
#define PIC_BYTESWAP   0x02
 
#define PIC_STATUS   0x04
 
#define PIC_INTR_TIMEOUT   0x06
 
#define PIC_ICI0_INTR_TIMEOUT   0x08
 
#define PIC_ICI1_INTR_TIMEOUT   0x0a
 
#define PIC_ICI2_INTR_TIMEOUT   0x0c
 
#define PIC_IPI_CTL   0x0e
 
#define PIC_INT_ACK   0x10
 
#define PIC_INT_PENDING0   0x12
 
#define PIC_INT_PENDING1   0x14
 
#define PIC_INT_PENDING2   0x16
 
#define PIC_WDOG0_MAXVAL   0x18
 
#define PIC_WDOG0_COUNT   0x1a
 
#define PIC_WDOG0_ENABLE0   0x1c
 
#define PIC_WDOG0_ENABLE1   0x1e
 
#define PIC_WDOG0_BEATCMD   0x20
 
#define PIC_WDOG0_BEAT0   0x22
 
#define PIC_WDOG0_BEAT1   0x24
 
#define PIC_WDOG1_MAXVAL   0x26
 
#define PIC_WDOG1_COUNT   0x28
 
#define PIC_WDOG1_ENABLE0   0x2a
 
#define PIC_WDOG1_ENABLE1   0x2c
 
#define PIC_WDOG1_BEATCMD   0x2e
 
#define PIC_WDOG1_BEAT0   0x30
 
#define PIC_WDOG1_BEAT1   0x32
 
#define PIC_WDOG_MAXVAL(i)   (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
 
#define PIC_WDOG_COUNT(i)   (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
 
#define PIC_WDOG_ENABLE0(i)   (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
 
#define PIC_WDOG_ENABLE1(i)   (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
 
#define PIC_WDOG_BEATCMD(i)   (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
 
#define PIC_WDOG_BEAT0(i)   (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
 
#define PIC_WDOG_BEAT1(i)   (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
 
#define PIC_TIMER0_MAXVAL   0x34
 
#define PIC_TIMER1_MAXVAL   0x36
 
#define PIC_TIMER2_MAXVAL   0x38
 
#define PIC_TIMER3_MAXVAL   0x3a
 
#define PIC_TIMER4_MAXVAL   0x3c
 
#define PIC_TIMER5_MAXVAL   0x3e
 
#define PIC_TIMER6_MAXVAL   0x40
 
#define PIC_TIMER7_MAXVAL   0x42
 
#define PIC_TIMER_MAXVAL(i)   (PIC_TIMER0_MAXVAL + ((i) * 2))
 
#define PIC_TIMER0_COUNT   0x44
 
#define PIC_TIMER1_COUNT   0x46
 
#define PIC_TIMER2_COUNT   0x48
 
#define PIC_TIMER3_COUNT   0x4a
 
#define PIC_TIMER4_COUNT   0x4c
 
#define PIC_TIMER5_COUNT   0x4e
 
#define PIC_TIMER6_COUNT   0x50
 
#define PIC_TIMER7_COUNT   0x52
 
#define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
 
#define PIC_ITE0_N0_N1   0x54
 
#define PIC_ITE1_N0_N1   0x58
 
#define PIC_ITE2_N0_N1   0x5c
 
#define PIC_ITE3_N0_N1   0x60
 
#define PIC_ITE4_N0_N1   0x64
 
#define PIC_ITE5_N0_N1   0x68
 
#define PIC_ITE6_N0_N1   0x6c
 
#define PIC_ITE7_N0_N1   0x70
 
#define PIC_ITE_N0_N1(i)   (PIC_ITE0_N0_N1 + ((i) * 4))
 
#define PIC_ITE0_N2_N3   0x56
 
#define PIC_ITE1_N2_N3   0x5a
 
#define PIC_ITE2_N2_N3   0x5e
 
#define PIC_ITE3_N2_N3   0x62
 
#define PIC_ITE4_N2_N3   0x66
 
#define PIC_ITE5_N2_N3   0x6a
 
#define PIC_ITE6_N2_N3   0x6e
 
#define PIC_ITE7_N2_N3   0x72
 
#define PIC_ITE_N2_N3(i)   (PIC_ITE0_N2_N3 + ((i) * 4))
 
#define PIC_IRT0   0x74
 
#define PIC_IRT(i)   (PIC_IRT0 + ((i) * 2))
 
#define TIMER_CYCLES_MAXVAL   0xffffffffffffffffULL
 
#define PIC_NUM_IRTS   160
 
#define PIC_IRT_WD_0_INDEX   0
 
#define PIC_IRT_WD_1_INDEX   1
 
#define PIC_IRT_WD_NMI_0_INDEX   2
 
#define PIC_IRT_WD_NMI_1_INDEX   3
 
#define PIC_IRT_TIMER_0_INDEX   4
 
#define PIC_IRT_TIMER_1_INDEX   5
 
#define PIC_IRT_TIMER_2_INDEX   6
 
#define PIC_IRT_TIMER_3_INDEX   7
 
#define PIC_IRT_TIMER_4_INDEX   8
 
#define PIC_IRT_TIMER_5_INDEX   9
 
#define PIC_IRT_TIMER_6_INDEX   10
 
#define PIC_IRT_TIMER_7_INDEX   11
 
#define PIC_IRT_CLOCK_INDEX   PIC_IRT_TIMER_7_INDEX
 
#define PIC_IRT_TIMER_INDEX(num)   ((num) + PIC_IRT_TIMER_0_INDEX)
 
#define PIC_NUM_MSG_Q_IRTS   32
 
#define PIC_IRT_MSG_Q0_INDEX   12
 
#define PIC_IRT_MSG_Q_INDEX(qid)   ((qid) + PIC_IRT_MSG_Q0_INDEX)
 
#define PIC_IRT_MSG_0_INDEX   44
 
#define PIC_IRT_MSG_1_INDEX   45
 
#define PIC_NUM_PCIE_MSIX_IRTS   32
 
#define PIC_IRT_PCIE_MSIX_0_INDEX   46
 
#define PIC_IRT_PCIE_MSIX_INDEX(num)   ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
 
#define PIC_NUM_PCIE_LINK_IRTS   4
 
#define PIC_IRT_PCIE_LINK_0_INDEX   78
 
#define PIC_IRT_PCIE_LINK_1_INDEX   79
 
#define PIC_IRT_PCIE_LINK_2_INDEX   80
 
#define PIC_IRT_PCIE_LINK_3_INDEX   81
 
#define PIC_IRT_PCIE_LINK_INDEX(num)   ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
 
#define PIC_NUM_NA_IRTS   32
 
#define PIC_IRT_NA_0_INDEX   82
 
#define PIC_IRT_NA_INDEX(num)   ((num) + PIC_IRT_NA_0_INDEX)
 
#define PIC_IRT_POE_INDEX   114
 
#define PIC_NUM_USB_IRTS   6
 
#define PIC_IRT_USB_0_INDEX   115
 
#define PIC_IRT_EHCI_0_INDEX   115
 
#define PIC_IRT_OHCI_0_INDEX   116
 
#define PIC_IRT_OHCI_1_INDEX   117
 
#define PIC_IRT_EHCI_1_INDEX   118
 
#define PIC_IRT_OHCI_2_INDEX   119
 
#define PIC_IRT_OHCI_3_INDEX   120
 
#define PIC_IRT_USB_INDEX(num)   ((num) + PIC_IRT_USB_0_INDEX)
 
#define PIC_IRT_GDX_INDEX   121
 
#define PIC_IRT_SEC_INDEX   122
 
#define PIC_IRT_RSA_INDEX   123
 
#define PIC_NUM_COMP_IRTS   4
 
#define PIC_IRT_COMP_0_INDEX   124
 
#define PIC_IRT_COMP_INDEX(num)   ((num) + PIC_IRT_COMP_0_INDEX)
 
#define PIC_IRT_GBU_INDEX   128
 
#define PIC_IRT_ICC_0_INDEX   129 /* ICC - Inter Chip Coherency */
 
#define PIC_IRT_ICC_1_INDEX   130
 
#define PIC_IRT_ICC_2_INDEX   131
 
#define PIC_IRT_CAM_INDEX   132
 
#define PIC_IRT_UART_0_INDEX   133
 
#define PIC_IRT_UART_1_INDEX   134
 
#define PIC_IRT_I2C_0_INDEX   135
 
#define PIC_IRT_I2C_1_INDEX   136
 
#define PIC_IRT_SYS_0_INDEX   137
 
#define PIC_IRT_SYS_1_INDEX   138
 
#define PIC_IRT_JTAG_INDEX   139
 
#define PIC_IRT_PIC_INDEX   140
 
#define PIC_IRT_NBU_INDEX   141
 
#define PIC_IRT_TCU_INDEX   142
 
#define PIC_IRT_GCU_INDEX   143 /* GBC - Global Coherency */
 
#define PIC_IRT_DMC_0_INDEX   144
 
#define PIC_IRT_DMC_1_INDEX   145
 
#define PIC_NUM_GPIO_IRTS   4
 
#define PIC_IRT_GPIO_0_INDEX   146
 
#define PIC_IRT_GPIO_INDEX(num)   ((num) + PIC_IRT_GPIO_0_INDEX)
 
#define PIC_IRT_NOR_INDEX   150
 
#define PIC_IRT_NAND_INDEX   151
 
#define PIC_IRT_SPI_INDEX   152
 
#define PIC_IRT_MMC_INDEX   153
 
#define PIC_CLOCK_TIMER   7
 
#define PIC_IRQ_BASE   8
 
#define PIC_IRT_FIRST_IRQ   (PIC_IRQ_BASE)
 
#define PIC_IRT_LAST_IRQ   63
 
#define PIC_IRQ_IS_IRT(irq)   ((irq) >= PIC_IRT_FIRST_IRQ)
 
#define PIC_IRT_VALID   1
 
#define PIC_LOCAL_SCHEDULING   1
 
#define PIC_GLOBAL_SCHEDULING   0
 
#define nlm_read_pic_reg(b, r)   nlm_read_reg64(b, r)
 
#define nlm_write_pic_reg(b, r, v)   nlm_write_reg64(b, r, v)
 
#define nlm_get_pic_pcibase(node)   nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
 
#define nlm_get_pic_regbase(node)   (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
 

Functions

int nlm_irq_to_irt (int irq)
 
int nlm_irt_to_irq (int irt)
 

Variables

uint64_t nlm_pic_base
 

Macro Definition Documentation

#define nlm_get_pic_pcibase (   node)    nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))

Definition at line 266 of file pic.h.

#define nlm_get_pic_regbase (   node)    (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)

Definition at line 267 of file pic.h.

#define nlm_read_pic_reg (   b,
  r 
)    nlm_read_reg64(b, r)

Definition at line 264 of file pic.h.

#define nlm_write_pic_reg (   b,
  r,
  v 
)    nlm_write_reg64(b, r, v)

Definition at line 265 of file pic.h.

#define PIC_BYTESWAP   0x02

Definition at line 74 of file pic.h.

#define PIC_CLOCK_TIMER   7

Definition at line 248 of file pic.h.

#define PIC_CTRL   0x00

Definition at line 39 of file pic.h.

#define PIC_CTRL_ICI   19 /* ICI interrupt timeout enable */

Definition at line 43 of file pic.h.

#define PIC_CTRL_ITE   18 /* interrupt timeout enable */

Definition at line 44 of file pic.h.

#define PIC_CTRL_ITV   32 /* interrupt timeout value */

Definition at line 42 of file pic.h.

#define PIC_CTRL_STE   10 /* system timer interrupt enable */

Definition at line 45 of file pic.h.

#define PIC_CTRL_WTE   0 /* watchdog timer enable */

Definition at line 50 of file pic.h.

#define PIC_CTRL_WWN0   2 /* watchdog 0 wraparound count for NMI */

Definition at line 49 of file pic.h.

#define PIC_CTRL_WWN1   4 /* watchdog 1 wraparound count for NMI */

Definition at line 48 of file pic.h.

#define PIC_CTRL_WWR0   6 /* watchdog 0 wraparound count for reset */

Definition at line 47 of file pic.h.

#define PIC_CTRL_WWR1   8 /* watchdog 1 wraparound count for reset */

Definition at line 46 of file pic.h.

#define PIC_GLOBAL_SCHEDULING   0

Definition at line 262 of file pic.h.

#define PIC_ICI0_INTR_TIMEOUT   0x08

Definition at line 77 of file pic.h.

#define PIC_ICI1_INTR_TIMEOUT   0x0a

Definition at line 78 of file pic.h.

#define PIC_ICI2_INTR_TIMEOUT   0x0c

Definition at line 79 of file pic.h.

#define PIC_ICI_STATUS   33 /* ICI interrupt timeout status */

Definition at line 53 of file pic.h.

#define PIC_INT_ACK   0x10

Definition at line 81 of file pic.h.

#define PIC_INT_PENDING0   0x12

Definition at line 82 of file pic.h.

#define PIC_INT_PENDING1   0x14

Definition at line 83 of file pic.h.

#define PIC_INT_PENDING2   0x16

Definition at line 84 of file pic.h.

#define PIC_INTR_TIMEOUT   0x06

Definition at line 76 of file pic.h.

#define PIC_IPI_CTL   0x0e

Definition at line 80 of file pic.h.

#define PIC_IPICTRL_DTE   0 /* interrupt destination thread enables */

Definition at line 63 of file pic.h.

#define PIC_IPICTRL_IDB   16 /* interrupt destination base */

Definition at line 62 of file pic.h.

#define PIC_IPICTRL_NMI   32

Definition at line 60 of file pic.h.

#define PIC_IPICTRL_RIV   20 /* received interrupt vector */

Definition at line 61 of file pic.h.

#define PIC_IRQ_BASE   8

Definition at line 249 of file pic.h.

#define PIC_IRQ_IS_IRT (   irq)    ((irq) >= PIC_IRT_FIRST_IRQ)

Definition at line 255 of file pic.h.

#define PIC_IRT (   i)    (PIC_IRT0 + ((i) * 2))

Definition at line 151 of file pic.h.

#define PIC_IRT0   0x74

Definition at line 150 of file pic.h.

#define PIC_IRT_CAM_INDEX   132

Definition at line 223 of file pic.h.

#define PIC_IRT_CLOCK_INDEX   PIC_IRT_TIMER_7_INDEX

Definition at line 172 of file pic.h.

#define PIC_IRT_COMP_0_INDEX   124

Definition at line 216 of file pic.h.

#define PIC_IRT_COMP_INDEX (   num)    ((num) + PIC_IRT_COMP_0_INDEX)

Definition at line 217 of file pic.h.

#define PIC_IRT_DB   16 /* Destination base */

Definition at line 71 of file pic.h.

#define PIC_IRT_DMC_0_INDEX   144

Definition at line 235 of file pic.h.

#define PIC_IRT_DMC_1_INDEX   145

Definition at line 236 of file pic.h.

#define PIC_IRT_DT   19 /* Destination type */

Definition at line 70 of file pic.h.

#define PIC_IRT_DTE   0 /* Destination thread enables */

Definition at line 72 of file pic.h.

#define PIC_IRT_EHCI_0_INDEX   115

Definition at line 203 of file pic.h.

#define PIC_IRT_EHCI_1_INDEX   118

Definition at line 206 of file pic.h.

#define PIC_IRT_ENABLE   31

Definition at line 66 of file pic.h.

#define PIC_IRT_FIRST_IRQ   (PIC_IRQ_BASE)

Definition at line 253 of file pic.h.

#define PIC_IRT_GBU_INDEX   128

Definition at line 219 of file pic.h.

#define PIC_IRT_GCU_INDEX   143 /* GBC - Global Coherency */

Definition at line 234 of file pic.h.

#define PIC_IRT_GDX_INDEX   121

Definition at line 211 of file pic.h.

#define PIC_IRT_GPIO_0_INDEX   146

Definition at line 239 of file pic.h.

#define PIC_IRT_GPIO_INDEX (   num)    ((num) + PIC_IRT_GPIO_0_INDEX)

Definition at line 240 of file pic.h.

#define PIC_IRT_I2C_0_INDEX   135

Definition at line 226 of file pic.h.

#define PIC_IRT_I2C_1_INDEX   136

Definition at line 227 of file pic.h.

#define PIC_IRT_ICC_0_INDEX   129 /* ICC - Inter Chip Coherency */

Definition at line 220 of file pic.h.

#define PIC_IRT_ICC_1_INDEX   130

Definition at line 221 of file pic.h.

#define PIC_IRT_ICC_2_INDEX   131

Definition at line 222 of file pic.h.

#define PIC_IRT_JTAG_INDEX   139

Definition at line 230 of file pic.h.

#define PIC_IRT_LAST_IRQ   63

Definition at line 254 of file pic.h.

#define PIC_IRT_MMC_INDEX   153

Definition at line 246 of file pic.h.

#define PIC_IRT_MSG_0_INDEX   44

Definition at line 181 of file pic.h.

#define PIC_IRT_MSG_1_INDEX   45

Definition at line 182 of file pic.h.

#define PIC_IRT_MSG_Q0_INDEX   12

Definition at line 178 of file pic.h.

#define PIC_IRT_MSG_Q_INDEX (   qid)    ((qid) + PIC_IRT_MSG_Q0_INDEX)

Definition at line 179 of file pic.h.

#define PIC_IRT_NA_0_INDEX   82

Definition at line 197 of file pic.h.

#define PIC_IRT_NA_INDEX (   num)    ((num) + PIC_IRT_NA_0_INDEX)

Definition at line 198 of file pic.h.

#define PIC_IRT_NAND_INDEX   151

Definition at line 244 of file pic.h.

#define PIC_IRT_NBU_INDEX   141

Definition at line 232 of file pic.h.

#define PIC_IRT_NMI   29

Definition at line 67 of file pic.h.

#define PIC_IRT_NOR_INDEX   150

Definition at line 243 of file pic.h.

#define PIC_IRT_OHCI_0_INDEX   116

Definition at line 204 of file pic.h.

#define PIC_IRT_OHCI_1_INDEX   117

Definition at line 205 of file pic.h.

#define PIC_IRT_OHCI_2_INDEX   119

Definition at line 207 of file pic.h.

#define PIC_IRT_OHCI_3_INDEX   120

Definition at line 208 of file pic.h.

#define PIC_IRT_PCIE_LINK_0_INDEX   78

Definition at line 189 of file pic.h.

#define PIC_IRT_PCIE_LINK_1_INDEX   79

Definition at line 190 of file pic.h.

#define PIC_IRT_PCIE_LINK_2_INDEX   80

Definition at line 191 of file pic.h.

#define PIC_IRT_PCIE_LINK_3_INDEX   81

Definition at line 192 of file pic.h.

#define PIC_IRT_PCIE_LINK_INDEX (   num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)

Definition at line 193 of file pic.h.

#define PIC_IRT_PCIE_MSIX_0_INDEX   46

Definition at line 185 of file pic.h.

#define PIC_IRT_PCIE_MSIX_INDEX (   num)    ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)

Definition at line 186 of file pic.h.

#define PIC_IRT_PIC_INDEX   140

Definition at line 231 of file pic.h.

#define PIC_IRT_POE_INDEX   114

Definition at line 199 of file pic.h.

#define PIC_IRT_RSA_INDEX   123

Definition at line 213 of file pic.h.

#define PIC_IRT_RVEC   20 /* Interrupt receive vectors */

Definition at line 69 of file pic.h.

#define PIC_IRT_SCH   28 /* Scheduling scheme */

Definition at line 68 of file pic.h.

#define PIC_IRT_SEC_INDEX   122

Definition at line 212 of file pic.h.

#define PIC_IRT_SPI_INDEX   152

Definition at line 245 of file pic.h.

#define PIC_IRT_SYS_0_INDEX   137

Definition at line 228 of file pic.h.

#define PIC_IRT_SYS_1_INDEX   138

Definition at line 229 of file pic.h.

#define PIC_IRT_TCU_INDEX   142

Definition at line 233 of file pic.h.

#define PIC_IRT_TIMER_0_INDEX   4

Definition at line 164 of file pic.h.

#define PIC_IRT_TIMER_1_INDEX   5

Definition at line 165 of file pic.h.

#define PIC_IRT_TIMER_2_INDEX   6

Definition at line 166 of file pic.h.

#define PIC_IRT_TIMER_3_INDEX   7

Definition at line 167 of file pic.h.

#define PIC_IRT_TIMER_4_INDEX   8

Definition at line 168 of file pic.h.

#define PIC_IRT_TIMER_5_INDEX   9

Definition at line 169 of file pic.h.

#define PIC_IRT_TIMER_6_INDEX   10

Definition at line 170 of file pic.h.

#define PIC_IRT_TIMER_7_INDEX   11

Definition at line 171 of file pic.h.

#define PIC_IRT_TIMER_INDEX (   num)    ((num) + PIC_IRT_TIMER_0_INDEX)

Definition at line 173 of file pic.h.

#define PIC_IRT_UART_0_INDEX   133

Definition at line 224 of file pic.h.

#define PIC_IRT_UART_1_INDEX   134

Definition at line 225 of file pic.h.

#define PIC_IRT_USB_0_INDEX   115

Definition at line 202 of file pic.h.

#define PIC_IRT_USB_INDEX (   num)    ((num) + PIC_IRT_USB_0_INDEX)

Definition at line 209 of file pic.h.

#define PIC_IRT_VALID   1

Definition at line 260 of file pic.h.

#define PIC_IRT_WD_0_INDEX   0

Definition at line 160 of file pic.h.

#define PIC_IRT_WD_1_INDEX   1

Definition at line 161 of file pic.h.

#define PIC_IRT_WD_NMI_0_INDEX   2

Definition at line 162 of file pic.h.

#define PIC_IRT_WD_NMI_1_INDEX   3

Definition at line 163 of file pic.h.

#define PIC_ITE0_N0_N1   0x54

Definition at line 130 of file pic.h.

#define PIC_ITE0_N2_N3   0x56

Definition at line 140 of file pic.h.

#define PIC_ITE1_N0_N1   0x58

Definition at line 131 of file pic.h.

#define PIC_ITE1_N2_N3   0x5a

Definition at line 141 of file pic.h.

#define PIC_ITE2_N0_N1   0x5c

Definition at line 132 of file pic.h.

#define PIC_ITE2_N2_N3   0x5e

Definition at line 142 of file pic.h.

#define PIC_ITE3_N0_N1   0x60

Definition at line 133 of file pic.h.

#define PIC_ITE3_N2_N3   0x62

Definition at line 143 of file pic.h.

#define PIC_ITE4_N0_N1   0x64

Definition at line 134 of file pic.h.

#define PIC_ITE4_N2_N3   0x66

Definition at line 144 of file pic.h.

#define PIC_ITE5_N0_N1   0x68

Definition at line 135 of file pic.h.

#define PIC_ITE5_N2_N3   0x6a

Definition at line 145 of file pic.h.

#define PIC_ITE6_N0_N1   0x6c

Definition at line 136 of file pic.h.

#define PIC_ITE6_N2_N3   0x6e

Definition at line 146 of file pic.h.

#define PIC_ITE7_N0_N1   0x70

Definition at line 137 of file pic.h.

#define PIC_ITE7_N2_N3   0x72

Definition at line 147 of file pic.h.

#define PIC_ITE_N0_N1 (   i)    (PIC_ITE0_N0_N1 + ((i) * 4))

Definition at line 138 of file pic.h.

#define PIC_ITE_N2_N3 (   i)    (PIC_ITE0_N2_N3 + ((i) * 4))

Definition at line 148 of file pic.h.

#define PIC_ITE_STATUS   32 /* interrupt timeout status */

Definition at line 54 of file pic.h.

#define PIC_LOCAL_SCHEDULING   1

Definition at line 261 of file pic.h.

#define PIC_NUM_COMP_IRTS   4

Definition at line 215 of file pic.h.

#define PIC_NUM_GPIO_IRTS   4

Definition at line 238 of file pic.h.

#define PIC_NUM_IRTS   160

Definition at line 158 of file pic.h.

#define PIC_NUM_MSG_Q_IRTS   32

Definition at line 177 of file pic.h.

#define PIC_NUM_NA_IRTS   32

Definition at line 195 of file pic.h.

#define PIC_NUM_PCIE_LINK_IRTS   4

Definition at line 188 of file pic.h.

#define PIC_NUM_PCIE_MSIX_IRTS   32

Definition at line 184 of file pic.h.

#define PIC_NUM_USB_IRTS   6

Definition at line 201 of file pic.h.

#define PIC_STATUS   0x04

Definition at line 75 of file pic.h.

#define PIC_STS_STATUS   4 /* System timer interrupt status */

Definition at line 55 of file pic.h.

#define PIC_TIMER0_COUNT   0x44

Definition at line 120 of file pic.h.

#define PIC_TIMER0_MAXVAL   0x34

Definition at line 110 of file pic.h.

#define PIC_TIMER1_COUNT   0x46

Definition at line 121 of file pic.h.

#define PIC_TIMER1_MAXVAL   0x36

Definition at line 111 of file pic.h.

#define PIC_TIMER2_COUNT   0x48

Definition at line 122 of file pic.h.

#define PIC_TIMER2_MAXVAL   0x38

Definition at line 112 of file pic.h.

#define PIC_TIMER3_COUNT   0x4a

Definition at line 123 of file pic.h.

#define PIC_TIMER3_MAXVAL   0x3a

Definition at line 113 of file pic.h.

#define PIC_TIMER4_COUNT   0x4c

Definition at line 124 of file pic.h.

#define PIC_TIMER4_MAXVAL   0x3c

Definition at line 114 of file pic.h.

#define PIC_TIMER5_COUNT   0x4e

Definition at line 125 of file pic.h.

#define PIC_TIMER5_MAXVAL   0x3e

Definition at line 115 of file pic.h.

#define PIC_TIMER6_COUNT   0x50

Definition at line 126 of file pic.h.

#define PIC_TIMER6_MAXVAL   0x40

Definition at line 116 of file pic.h.

#define PIC_TIMER7_COUNT   0x52

Definition at line 127 of file pic.h.

#define PIC_TIMER7_MAXVAL   0x42

Definition at line 117 of file pic.h.

#define PIC_TIMER_COUNT (   i)    (PIC_TIMER0_COUNT + ((i) * 2))

Definition at line 128 of file pic.h.

#define PIC_TIMER_MAXVAL (   i)    (PIC_TIMER0_MAXVAL + ((i) * 2))

Definition at line 118 of file pic.h.

#define PIC_WDOG0_BEAT0   0x22

Definition at line 91 of file pic.h.

#define PIC_WDOG0_BEAT1   0x24

Definition at line 92 of file pic.h.

#define PIC_WDOG0_BEATCMD   0x20

Definition at line 90 of file pic.h.

#define PIC_WDOG0_COUNT   0x1a

Definition at line 87 of file pic.h.

#define PIC_WDOG0_ENABLE0   0x1c

Definition at line 88 of file pic.h.

#define PIC_WDOG0_ENABLE1   0x1e

Definition at line 89 of file pic.h.

#define PIC_WDOG0_MAXVAL   0x18

Definition at line 86 of file pic.h.

#define PIC_WDOG1_BEAT0   0x30

Definition at line 99 of file pic.h.

#define PIC_WDOG1_BEAT1   0x32

Definition at line 100 of file pic.h.

#define PIC_WDOG1_BEATCMD   0x2e

Definition at line 98 of file pic.h.

#define PIC_WDOG1_COUNT   0x28

Definition at line 95 of file pic.h.

#define PIC_WDOG1_ENABLE0   0x2a

Definition at line 96 of file pic.h.

#define PIC_WDOG1_ENABLE1   0x2c

Definition at line 97 of file pic.h.

#define PIC_WDOG1_MAXVAL   0x26

Definition at line 94 of file pic.h.

#define PIC_WDOG_BEAT0 (   i)    (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))

Definition at line 107 of file pic.h.

#define PIC_WDOG_BEAT1 (   i)    (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))

Definition at line 108 of file pic.h.

#define PIC_WDOG_BEATCMD (   i)    (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))

Definition at line 106 of file pic.h.

#define PIC_WDOG_COUNT (   i)    (PIC_WDOG0_COUNT + ((i) ? 7 : 0))

Definition at line 103 of file pic.h.

#define PIC_WDOG_ENABLE0 (   i)    (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))

Definition at line 104 of file pic.h.

#define PIC_WDOG_ENABLE1 (   i)    (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))

Definition at line 105 of file pic.h.

#define PIC_WDOG_MAXVAL (   i)    (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))

Definition at line 102 of file pic.h.

#define PIC_WIS_STATUS   0 /* Interrupt status for watchdog timers */

Definition at line 57 of file pic.h.

#define PIC_WNS_STATUS   2 /* NMI status for watchdog timers */

Definition at line 56 of file pic.h.

#define TIMER_CYCLES_MAXVAL   0xffffffffffffffffULL

Definition at line 153 of file pic.h.

Function Documentation

int nlm_irq_to_irt ( int  irq)

Definition at line 62 of file nlm_hal.c.

int nlm_irt_to_irq ( int  irt)

Definition at line 103 of file nlm_hal.c.

Variable Documentation

uint64_t nlm_pic_base

Definition at line 52 of file nlm_hal.c.