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mxl5005s.c
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1 /*
2  MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
3 
4  Copyright (C) 2008 MaxLinear
5  Copyright (C) 2006 Steven Toth <[email protected]>
6  Functions:
7  mxl5005s_reset()
8  mxl5005s_writereg()
9  mxl5005s_writeregs()
10  mxl5005s_init()
11  mxl5005s_reconfigure()
12  mxl5005s_AssignTunerMode()
13  mxl5005s_set_params()
14  mxl5005s_get_frequency()
15  mxl5005s_get_bandwidth()
16  mxl5005s_release()
17  mxl5005s_attach()
18 
19  Copyright (C) 2008 Realtek
20  Copyright (C) 2008 Jan Hoogenraad
21  Functions:
22  mxl5005s_SetRfFreqHz()
23 
24  This program is free software; you can redistribute it and/or modify
25  it under the terms of the GNU General Public License as published by
26  the Free Software Foundation; either version 2 of the License, or
27  (at your option) any later version.
28 
29  This program is distributed in the hope that it will be useful,
30  but WITHOUT ANY WARRANTY; without even the implied warranty of
31  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32  GNU General Public License for more details.
33 
34  You should have received a copy of the GNU General Public License
35  along with this program; if not, write to the Free Software
36  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
37 
38 */
39 
40 /*
41  History of this driver (Steven Toth):
42  I was given a public release of a linux driver that included
43  support for the MaxLinear MXL5005S silicon tuner. Analysis of
44  the tuner driver showed clearly three things.
45 
46  1. The tuner driver didn't support the LinuxTV tuner API
47  so the code Realtek added had to be removed.
48 
49  2. A significant amount of the driver is reference driver code
50  from MaxLinear, I felt it was important to identify and
51  preserve this.
52 
53  3. New code has to be added to interface correctly with the
54  LinuxTV API, as a regular kernel module.
55 
56  Other than the reference driver enum's, I've clearly marked
57  sections of the code and retained the copyright of the
58  respective owners.
59 */
60 #include <linux/kernel.h>
61 #include <linux/init.h>
62 #include <linux/module.h>
63 #include <linux/string.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include "dvb_frontend.h"
67 #include "mxl5005s.h"
68 
69 static int debug;
70 
71 #define dprintk(level, arg...) do { \
72  if (level <= debug) \
73  printk(arg); \
74  } while (0)
75 
76 #define TUNER_REGS_NUM 104
77 #define INITCTRL_NUM 40
78 
79 #ifdef _MXL_PRODUCTION
80 #define CHCTRL_NUM 39
81 #else
82 #define CHCTRL_NUM 36
83 #endif
84 
85 #define MXLCTRL_NUM 189
86 #define MASTER_CONTROL_ADDR 9
87 
88 /* Enumeration of Master Control Register State */
89 enum master_control_state {
90  MC_LOAD_START = 1,
91  MC_POWER_DOWN,
92  MC_SYNTH_RESET,
93  MC_SEQ_OFF
94 };
95 
96 /* Enumeration of MXL5005 Tuner Modulation Type */
97 enum {
98  MXL_DEFAULT_MODULATION = 0,
99  MXL_DVBT,
100  MXL_ATSC,
101  MXL_QAM,
102  MXL_ANALOG_CABLE,
103  MXL_ANALOG_OTA
104 };
105 
106 /* MXL5005 Tuner Register Struct */
107 struct TunerReg {
108  u16 Reg_Num; /* Tuner Register Address */
109  u16 Reg_Val; /* Current sw programmed value waiting to be written */
110 };
111 
112 enum {
113  /* Initialization Control Names */
114  DN_IQTN_AMP_CUT = 1, /* 1 */
115  BB_MODE, /* 2 */
116  BB_BUF, /* 3 */
117  BB_BUF_OA, /* 4 */
118  BB_ALPF_BANDSELECT, /* 5 */
119  BB_IQSWAP, /* 6 */
120  BB_DLPF_BANDSEL, /* 7 */
121  RFSYN_CHP_GAIN, /* 8 */
122  RFSYN_EN_CHP_HIGAIN, /* 9 */
123  AGC_IF, /* 10 */
124  AGC_RF, /* 11 */
125  IF_DIVVAL, /* 12 */
126  IF_VCO_BIAS, /* 13 */
127  CHCAL_INT_MOD_IF, /* 14 */
128  CHCAL_FRAC_MOD_IF, /* 15 */
129  DRV_RES_SEL, /* 16 */
130  I_DRIVER, /* 17 */
131  EN_AAF, /* 18 */
132  EN_3P, /* 19 */
133  EN_AUX_3P, /* 20 */
134  SEL_AAF_BAND, /* 21 */
135  SEQ_ENCLK16_CLK_OUT, /* 22 */
136  SEQ_SEL4_16B, /* 23 */
137  XTAL_CAPSELECT, /* 24 */
138  IF_SEL_DBL, /* 25 */
139  RFSYN_R_DIV, /* 26 */
140  SEQ_EXTSYNTHCALIF, /* 27 */
141  SEQ_EXTDCCAL, /* 28 */
142  AGC_EN_RSSI, /* 29 */
143  RFA_ENCLKRFAGC, /* 30 */
144  RFA_RSSI_REFH, /* 31 */
145  RFA_RSSI_REF, /* 32 */
146  RFA_RSSI_REFL, /* 33 */
147  RFA_FLR, /* 34 */
148  RFA_CEIL, /* 35 */
149  SEQ_EXTIQFSMPULSE, /* 36 */
150  OVERRIDE_1, /* 37 */
151  BB_INITSTATE_DLPF_TUNE, /* 38 */
152  TG_R_DIV, /* 39 */
153  EN_CHP_LIN_B, /* 40 */
154 
155  /* Channel Change Control Names */
156  DN_POLY = 51, /* 51 */
157  DN_RFGAIN, /* 52 */
158  DN_CAP_RFLPF, /* 53 */
159  DN_EN_VHFUHFBAR, /* 54 */
160  DN_GAIN_ADJUST, /* 55 */
161  DN_IQTNBUF_AMP, /* 56 */
162  DN_IQTNGNBFBIAS_BST, /* 57 */
163  RFSYN_EN_OUTMUX, /* 58 */
164  RFSYN_SEL_VCO_OUT, /* 59 */
165  RFSYN_SEL_VCO_HI, /* 60 */
166  RFSYN_SEL_DIVM, /* 61 */
167  RFSYN_RF_DIV_BIAS, /* 62 */
168  DN_SEL_FREQ, /* 63 */
169  RFSYN_VCO_BIAS, /* 64 */
170  CHCAL_INT_MOD_RF, /* 65 */
171  CHCAL_FRAC_MOD_RF, /* 66 */
172  RFSYN_LPF_R, /* 67 */
173  CHCAL_EN_INT_RF, /* 68 */
174  TG_LO_DIVVAL, /* 69 */
175  TG_LO_SELVAL, /* 70 */
176  TG_DIV_VAL, /* 71 */
177  TG_VCO_BIAS, /* 72 */
178  SEQ_EXTPOWERUP, /* 73 */
179  OVERRIDE_2, /* 74 */
180  OVERRIDE_3, /* 75 */
181  OVERRIDE_4, /* 76 */
182  SEQ_FSM_PULSE, /* 77 */
183  GPIO_4B, /* 78 */
184  GPIO_3B, /* 79 */
185  GPIO_4, /* 80 */
186  GPIO_3, /* 81 */
187  GPIO_1B, /* 82 */
188  DAC_A_ENABLE, /* 83 */
189  DAC_B_ENABLE, /* 84 */
190  DAC_DIN_A, /* 85 */
191  DAC_DIN_B, /* 86 */
192 #ifdef _MXL_PRODUCTION
193  RFSYN_EN_DIV, /* 87 */
194  RFSYN_DIVM, /* 88 */
195  DN_BYPASS_AGC_I2C /* 89 */
196 #endif
197 };
198 
199 /*
200  * The following context is source code provided by MaxLinear.
201  * MaxLinear source code - Common_MXL.h (?)
202  */
203 
204 /* Constants */
205 #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
206 #define MXL5005S_LATCH_BYTE 0xfe
207 
208 /* Register address, MSB, and LSB */
209 #define MXL5005S_BB_IQSWAP_ADDR 59
210 #define MXL5005S_BB_IQSWAP_MSB 0
211 #define MXL5005S_BB_IQSWAP_LSB 0
212 
213 #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
214 #define MXL5005S_BB_DLPF_BANDSEL_MSB 4
215 #define MXL5005S_BB_DLPF_BANDSEL_LSB 3
216 
217 /* Standard modes */
218 enum {
219  MXL5005S_STANDARD_DVBT,
220  MXL5005S_STANDARD_ATSC,
221 };
222 #define MXL5005S_STANDARD_MODE_NUM 2
223 
224 /* Bandwidth modes */
225 enum {
226  MXL5005S_BANDWIDTH_6MHZ = 6000000,
227  MXL5005S_BANDWIDTH_7MHZ = 7000000,
228  MXL5005S_BANDWIDTH_8MHZ = 8000000,
229 };
230 #define MXL5005S_BANDWIDTH_MODE_NUM 3
231 
232 /* MXL5005 Tuner Control Struct */
233 struct TunerControl {
234  u16 Ctrl_Num; /* Control Number */
235  u16 size; /* Number of bits to represent Value */
236  u16 addr[25]; /* Array of Tuner Register Address for each bit pos */
237  u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */
238  u16 val[25]; /* Binary representation of Value */
239 };
240 
241 /* MXL5005 Tuner Struct */
242 struct mxl5005s_state {
243  u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
244  u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
245  u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
246  u32 IF_OUT; /* Desired IF Out Frequency */
247  u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
248  u32 RF_IN; /* RF Input Frequency */
249  u32 Fxtal; /* XTAL Frequency */
250  u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
251  u16 TOP; /* Value: take over point */
252  u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */
253  u8 DIV_OUT; /* 4MHz or 16MHz */
254  u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
255  u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
256 
257  /* Modulation Type; */
258  /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
259  u8 Mod_Type;
260 
261  /* Tracking Filter Type */
262  /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
263  u8 TF_Type;
264 
265  /* Calculated Settings */
266  u32 RF_LO; /* Synth RF LO Frequency */
267  u32 IF_LO; /* Synth IF LO Frequency */
268  u32 TG_LO; /* Synth TG_LO Frequency */
269 
270  /* Pointers to ControlName Arrays */
271  u16 Init_Ctrl_Num; /* Number of INIT Control Names */
272  struct TunerControl
273  Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
274 
275  u16 CH_Ctrl_Num; /* Number of CH Control Names */
276  struct TunerControl
277  CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
278 
279  u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
280  struct TunerControl
281  MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
282 
283  /* Pointer to Tuner Register Array */
284  u16 TunerRegs_Num; /* Number of Tuner Registers */
285  struct TunerReg
286  TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
287 
288  /* Linux driver framework specific */
289  struct mxl5005s_config *config;
290  struct dvb_frontend *frontend;
291  struct i2c_adapter *i2c;
292 
293  /* Cache values */
294  u32 current_mode;
295 
296 };
297 
298 static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
299 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
300 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
301 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
302  u8 bitVal);
303 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
304  u8 *RegVal, int *count);
305 static u32 MXL_Ceiling(u32 value, u32 resolution);
306 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
307 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
308  u32 value, u16 controlGroup);
309 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
310 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
311  u8 *RegVal, int *count);
312 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
313 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
314 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
315 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
316  u8 *RegVal, int *count);
317 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
318  u8 *datatable, u8 len);
319 static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
320 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
321  u32 bandwidth);
322 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
323  u32 bandwidth);
324 
325 /* ----------------------------------------------------------------
326  * Begin: Custom code salvaged from the Realtek driver.
327  * Copyright (C) 2008 Realtek
328  * Copyright (C) 2008 Jan Hoogenraad
329  * This code is placed under the terms of the GNU General Public License
330  *
331  * Released by Realtek under GPLv2.
332  * Thanks to Realtek for a lot of support we received !
333  *
334  * Revision: 080314 - original version
335  */
336 
337 static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
338 {
339  struct mxl5005s_state *state = fe->tuner_priv;
340  unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
341  unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
342  int TableLen;
343 
344  u32 IfDivval = 0;
345  unsigned char MasterControlByte;
346 
347  dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
348 
349  /* Set MxL5005S tuner RF frequency according to example code. */
350 
351  /* Tuner RF frequency setting stage 0 */
352  MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
353  AddrTable[0] = MASTER_CONTROL_ADDR;
354  ByteTable[0] |= state->config->AgcMasterByte;
355 
356  mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
357 
358  /* Tuner RF frequency setting stage 1 */
359  MXL_TuneRF(fe, RfFreqHz);
360 
361  MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
362 
363  MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
364  MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
365  MXL_ControlWrite(fe, IF_DIVVAL, 8);
366  MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
367 
368  MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
369  AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
370  ByteTable[TableLen] = MasterControlByte |
371  state->config->AgcMasterByte;
372  TableLen += 1;
373 
374  mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
375 
376  /* Wait 30 ms. */
377  msleep(150);
378 
379  /* Tuner RF frequency setting stage 2 */
380  MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
381  MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
382  MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
383 
384  MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
385  AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
386  ByteTable[TableLen] = MasterControlByte |
387  state->config->AgcMasterByte ;
388  TableLen += 1;
389 
390  mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
391 
392  msleep(100);
393 
394  return 0;
395 }
396 /* End: Custom code taken from the Realtek driver */
397 
398 /* ----------------------------------------------------------------
399  * Begin: Reference driver code found in the Realtek driver.
400  * Copyright (C) 2008 MaxLinear
401  */
402 static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
403 {
404  struct mxl5005s_state *state = fe->tuner_priv;
405  state->TunerRegs_Num = TUNER_REGS_NUM ;
406 
407  state->TunerRegs[0].Reg_Num = 9 ;
408  state->TunerRegs[0].Reg_Val = 0x40 ;
409 
410  state->TunerRegs[1].Reg_Num = 11 ;
411  state->TunerRegs[1].Reg_Val = 0x19 ;
412 
413  state->TunerRegs[2].Reg_Num = 12 ;
414  state->TunerRegs[2].Reg_Val = 0x60 ;
415 
416  state->TunerRegs[3].Reg_Num = 13 ;
417  state->TunerRegs[3].Reg_Val = 0x00 ;
418 
419  state->TunerRegs[4].Reg_Num = 14 ;
420  state->TunerRegs[4].Reg_Val = 0x00 ;
421 
422  state->TunerRegs[5].Reg_Num = 15 ;
423  state->TunerRegs[5].Reg_Val = 0xC0 ;
424 
425  state->TunerRegs[6].Reg_Num = 16 ;
426  state->TunerRegs[6].Reg_Val = 0x00 ;
427 
428  state->TunerRegs[7].Reg_Num = 17 ;
429  state->TunerRegs[7].Reg_Val = 0x00 ;
430 
431  state->TunerRegs[8].Reg_Num = 18 ;
432  state->TunerRegs[8].Reg_Val = 0x00 ;
433 
434  state->TunerRegs[9].Reg_Num = 19 ;
435  state->TunerRegs[9].Reg_Val = 0x34 ;
436 
437  state->TunerRegs[10].Reg_Num = 21 ;
438  state->TunerRegs[10].Reg_Val = 0x00 ;
439 
440  state->TunerRegs[11].Reg_Num = 22 ;
441  state->TunerRegs[11].Reg_Val = 0x6B ;
442 
443  state->TunerRegs[12].Reg_Num = 23 ;
444  state->TunerRegs[12].Reg_Val = 0x35 ;
445 
446  state->TunerRegs[13].Reg_Num = 24 ;
447  state->TunerRegs[13].Reg_Val = 0x70 ;
448 
449  state->TunerRegs[14].Reg_Num = 25 ;
450  state->TunerRegs[14].Reg_Val = 0x3E ;
451 
452  state->TunerRegs[15].Reg_Num = 26 ;
453  state->TunerRegs[15].Reg_Val = 0x82 ;
454 
455  state->TunerRegs[16].Reg_Num = 31 ;
456  state->TunerRegs[16].Reg_Val = 0x00 ;
457 
458  state->TunerRegs[17].Reg_Num = 32 ;
459  state->TunerRegs[17].Reg_Val = 0x40 ;
460 
461  state->TunerRegs[18].Reg_Num = 33 ;
462  state->TunerRegs[18].Reg_Val = 0x53 ;
463 
464  state->TunerRegs[19].Reg_Num = 34 ;
465  state->TunerRegs[19].Reg_Val = 0x81 ;
466 
467  state->TunerRegs[20].Reg_Num = 35 ;
468  state->TunerRegs[20].Reg_Val = 0xC9 ;
469 
470  state->TunerRegs[21].Reg_Num = 36 ;
471  state->TunerRegs[21].Reg_Val = 0x01 ;
472 
473  state->TunerRegs[22].Reg_Num = 37 ;
474  state->TunerRegs[22].Reg_Val = 0x00 ;
475 
476  state->TunerRegs[23].Reg_Num = 41 ;
477  state->TunerRegs[23].Reg_Val = 0x00 ;
478 
479  state->TunerRegs[24].Reg_Num = 42 ;
480  state->TunerRegs[24].Reg_Val = 0xF8 ;
481 
482  state->TunerRegs[25].Reg_Num = 43 ;
483  state->TunerRegs[25].Reg_Val = 0x43 ;
484 
485  state->TunerRegs[26].Reg_Num = 44 ;
486  state->TunerRegs[26].Reg_Val = 0x20 ;
487 
488  state->TunerRegs[27].Reg_Num = 45 ;
489  state->TunerRegs[27].Reg_Val = 0x80 ;
490 
491  state->TunerRegs[28].Reg_Num = 46 ;
492  state->TunerRegs[28].Reg_Val = 0x88 ;
493 
494  state->TunerRegs[29].Reg_Num = 47 ;
495  state->TunerRegs[29].Reg_Val = 0x86 ;
496 
497  state->TunerRegs[30].Reg_Num = 48 ;
498  state->TunerRegs[30].Reg_Val = 0x00 ;
499 
500  state->TunerRegs[31].Reg_Num = 49 ;
501  state->TunerRegs[31].Reg_Val = 0x00 ;
502 
503  state->TunerRegs[32].Reg_Num = 53 ;
504  state->TunerRegs[32].Reg_Val = 0x94 ;
505 
506  state->TunerRegs[33].Reg_Num = 54 ;
507  state->TunerRegs[33].Reg_Val = 0xFA ;
508 
509  state->TunerRegs[34].Reg_Num = 55 ;
510  state->TunerRegs[34].Reg_Val = 0x92 ;
511 
512  state->TunerRegs[35].Reg_Num = 56 ;
513  state->TunerRegs[35].Reg_Val = 0x80 ;
514 
515  state->TunerRegs[36].Reg_Num = 57 ;
516  state->TunerRegs[36].Reg_Val = 0x41 ;
517 
518  state->TunerRegs[37].Reg_Num = 58 ;
519  state->TunerRegs[37].Reg_Val = 0xDB ;
520 
521  state->TunerRegs[38].Reg_Num = 59 ;
522  state->TunerRegs[38].Reg_Val = 0x00 ;
523 
524  state->TunerRegs[39].Reg_Num = 60 ;
525  state->TunerRegs[39].Reg_Val = 0x00 ;
526 
527  state->TunerRegs[40].Reg_Num = 61 ;
528  state->TunerRegs[40].Reg_Val = 0x00 ;
529 
530  state->TunerRegs[41].Reg_Num = 62 ;
531  state->TunerRegs[41].Reg_Val = 0x00 ;
532 
533  state->TunerRegs[42].Reg_Num = 65 ;
534  state->TunerRegs[42].Reg_Val = 0xF8 ;
535 
536  state->TunerRegs[43].Reg_Num = 66 ;
537  state->TunerRegs[43].Reg_Val = 0xE4 ;
538 
539  state->TunerRegs[44].Reg_Num = 67 ;
540  state->TunerRegs[44].Reg_Val = 0x90 ;
541 
542  state->TunerRegs[45].Reg_Num = 68 ;
543  state->TunerRegs[45].Reg_Val = 0xC0 ;
544 
545  state->TunerRegs[46].Reg_Num = 69 ;
546  state->TunerRegs[46].Reg_Val = 0x01 ;
547 
548  state->TunerRegs[47].Reg_Num = 70 ;
549  state->TunerRegs[47].Reg_Val = 0x50 ;
550 
551  state->TunerRegs[48].Reg_Num = 71 ;
552  state->TunerRegs[48].Reg_Val = 0x06 ;
553 
554  state->TunerRegs[49].Reg_Num = 72 ;
555  state->TunerRegs[49].Reg_Val = 0x00 ;
556 
557  state->TunerRegs[50].Reg_Num = 73 ;
558  state->TunerRegs[50].Reg_Val = 0x20 ;
559 
560  state->TunerRegs[51].Reg_Num = 76 ;
561  state->TunerRegs[51].Reg_Val = 0xBB ;
562 
563  state->TunerRegs[52].Reg_Num = 77 ;
564  state->TunerRegs[52].Reg_Val = 0x13 ;
565 
566  state->TunerRegs[53].Reg_Num = 81 ;
567  state->TunerRegs[53].Reg_Val = 0x04 ;
568 
569  state->TunerRegs[54].Reg_Num = 82 ;
570  state->TunerRegs[54].Reg_Val = 0x75 ;
571 
572  state->TunerRegs[55].Reg_Num = 83 ;
573  state->TunerRegs[55].Reg_Val = 0x00 ;
574 
575  state->TunerRegs[56].Reg_Num = 84 ;
576  state->TunerRegs[56].Reg_Val = 0x00 ;
577 
578  state->TunerRegs[57].Reg_Num = 85 ;
579  state->TunerRegs[57].Reg_Val = 0x00 ;
580 
581  state->TunerRegs[58].Reg_Num = 91 ;
582  state->TunerRegs[58].Reg_Val = 0x70 ;
583 
584  state->TunerRegs[59].Reg_Num = 92 ;
585  state->TunerRegs[59].Reg_Val = 0x00 ;
586 
587  state->TunerRegs[60].Reg_Num = 93 ;
588  state->TunerRegs[60].Reg_Val = 0x00 ;
589 
590  state->TunerRegs[61].Reg_Num = 94 ;
591  state->TunerRegs[61].Reg_Val = 0x00 ;
592 
593  state->TunerRegs[62].Reg_Num = 95 ;
594  state->TunerRegs[62].Reg_Val = 0x0C ;
595 
596  state->TunerRegs[63].Reg_Num = 96 ;
597  state->TunerRegs[63].Reg_Val = 0x00 ;
598 
599  state->TunerRegs[64].Reg_Num = 97 ;
600  state->TunerRegs[64].Reg_Val = 0x00 ;
601 
602  state->TunerRegs[65].Reg_Num = 98 ;
603  state->TunerRegs[65].Reg_Val = 0xE2 ;
604 
605  state->TunerRegs[66].Reg_Num = 99 ;
606  state->TunerRegs[66].Reg_Val = 0x00 ;
607 
608  state->TunerRegs[67].Reg_Num = 100 ;
609  state->TunerRegs[67].Reg_Val = 0x00 ;
610 
611  state->TunerRegs[68].Reg_Num = 101 ;
612  state->TunerRegs[68].Reg_Val = 0x12 ;
613 
614  state->TunerRegs[69].Reg_Num = 102 ;
615  state->TunerRegs[69].Reg_Val = 0x80 ;
616 
617  state->TunerRegs[70].Reg_Num = 103 ;
618  state->TunerRegs[70].Reg_Val = 0x32 ;
619 
620  state->TunerRegs[71].Reg_Num = 104 ;
621  state->TunerRegs[71].Reg_Val = 0xB4 ;
622 
623  state->TunerRegs[72].Reg_Num = 105 ;
624  state->TunerRegs[72].Reg_Val = 0x60 ;
625 
626  state->TunerRegs[73].Reg_Num = 106 ;
627  state->TunerRegs[73].Reg_Val = 0x83 ;
628 
629  state->TunerRegs[74].Reg_Num = 107 ;
630  state->TunerRegs[74].Reg_Val = 0x84 ;
631 
632  state->TunerRegs[75].Reg_Num = 108 ;
633  state->TunerRegs[75].Reg_Val = 0x9C ;
634 
635  state->TunerRegs[76].Reg_Num = 109 ;
636  state->TunerRegs[76].Reg_Val = 0x02 ;
637 
638  state->TunerRegs[77].Reg_Num = 110 ;
639  state->TunerRegs[77].Reg_Val = 0x81 ;
640 
641  state->TunerRegs[78].Reg_Num = 111 ;
642  state->TunerRegs[78].Reg_Val = 0xC0 ;
643 
644  state->TunerRegs[79].Reg_Num = 112 ;
645  state->TunerRegs[79].Reg_Val = 0x10 ;
646 
647  state->TunerRegs[80].Reg_Num = 131 ;
648  state->TunerRegs[80].Reg_Val = 0x8A ;
649 
650  state->TunerRegs[81].Reg_Num = 132 ;
651  state->TunerRegs[81].Reg_Val = 0x10 ;
652 
653  state->TunerRegs[82].Reg_Num = 133 ;
654  state->TunerRegs[82].Reg_Val = 0x24 ;
655 
656  state->TunerRegs[83].Reg_Num = 134 ;
657  state->TunerRegs[83].Reg_Val = 0x00 ;
658 
659  state->TunerRegs[84].Reg_Num = 135 ;
660  state->TunerRegs[84].Reg_Val = 0x00 ;
661 
662  state->TunerRegs[85].Reg_Num = 136 ;
663  state->TunerRegs[85].Reg_Val = 0x7E ;
664 
665  state->TunerRegs[86].Reg_Num = 137 ;
666  state->TunerRegs[86].Reg_Val = 0x40 ;
667 
668  state->TunerRegs[87].Reg_Num = 138 ;
669  state->TunerRegs[87].Reg_Val = 0x38 ;
670 
671  state->TunerRegs[88].Reg_Num = 146 ;
672  state->TunerRegs[88].Reg_Val = 0xF6 ;
673 
674  state->TunerRegs[89].Reg_Num = 147 ;
675  state->TunerRegs[89].Reg_Val = 0x1A ;
676 
677  state->TunerRegs[90].Reg_Num = 148 ;
678  state->TunerRegs[90].Reg_Val = 0x62 ;
679 
680  state->TunerRegs[91].Reg_Num = 149 ;
681  state->TunerRegs[91].Reg_Val = 0x33 ;
682 
683  state->TunerRegs[92].Reg_Num = 150 ;
684  state->TunerRegs[92].Reg_Val = 0x80 ;
685 
686  state->TunerRegs[93].Reg_Num = 156 ;
687  state->TunerRegs[93].Reg_Val = 0x56 ;
688 
689  state->TunerRegs[94].Reg_Num = 157 ;
690  state->TunerRegs[94].Reg_Val = 0x17 ;
691 
692  state->TunerRegs[95].Reg_Num = 158 ;
693  state->TunerRegs[95].Reg_Val = 0xA9 ;
694 
695  state->TunerRegs[96].Reg_Num = 159 ;
696  state->TunerRegs[96].Reg_Val = 0x00 ;
697 
698  state->TunerRegs[97].Reg_Num = 160 ;
699  state->TunerRegs[97].Reg_Val = 0x00 ;
700 
701  state->TunerRegs[98].Reg_Num = 161 ;
702  state->TunerRegs[98].Reg_Val = 0x00 ;
703 
704  state->TunerRegs[99].Reg_Num = 162 ;
705  state->TunerRegs[99].Reg_Val = 0x40 ;
706 
707  state->TunerRegs[100].Reg_Num = 166 ;
708  state->TunerRegs[100].Reg_Val = 0xAE ;
709 
710  state->TunerRegs[101].Reg_Num = 167 ;
711  state->TunerRegs[101].Reg_Val = 0x1B ;
712 
713  state->TunerRegs[102].Reg_Num = 168 ;
714  state->TunerRegs[102].Reg_Val = 0xF2 ;
715 
716  state->TunerRegs[103].Reg_Num = 195 ;
717  state->TunerRegs[103].Reg_Val = 0x00 ;
718 
719  return 0 ;
720 }
721 
722 static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
723 {
724  struct mxl5005s_state *state = fe->tuner_priv;
725  state->Init_Ctrl_Num = INITCTRL_NUM;
726 
727  state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
728  state->Init_Ctrl[0].size = 1 ;
729  state->Init_Ctrl[0].addr[0] = 73;
730  state->Init_Ctrl[0].bit[0] = 7;
731  state->Init_Ctrl[0].val[0] = 0;
732 
733  state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
734  state->Init_Ctrl[1].size = 1 ;
735  state->Init_Ctrl[1].addr[0] = 53;
736  state->Init_Ctrl[1].bit[0] = 2;
737  state->Init_Ctrl[1].val[0] = 1;
738 
739  state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
740  state->Init_Ctrl[2].size = 2 ;
741  state->Init_Ctrl[2].addr[0] = 53;
742  state->Init_Ctrl[2].bit[0] = 1;
743  state->Init_Ctrl[2].val[0] = 0;
744  state->Init_Ctrl[2].addr[1] = 57;
745  state->Init_Ctrl[2].bit[1] = 0;
746  state->Init_Ctrl[2].val[1] = 1;
747 
748  state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
749  state->Init_Ctrl[3].size = 1 ;
750  state->Init_Ctrl[3].addr[0] = 53;
751  state->Init_Ctrl[3].bit[0] = 0;
752  state->Init_Ctrl[3].val[0] = 0;
753 
754  state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
755  state->Init_Ctrl[4].size = 3 ;
756  state->Init_Ctrl[4].addr[0] = 53;
757  state->Init_Ctrl[4].bit[0] = 5;
758  state->Init_Ctrl[4].val[0] = 0;
759  state->Init_Ctrl[4].addr[1] = 53;
760  state->Init_Ctrl[4].bit[1] = 6;
761  state->Init_Ctrl[4].val[1] = 0;
762  state->Init_Ctrl[4].addr[2] = 53;
763  state->Init_Ctrl[4].bit[2] = 7;
764  state->Init_Ctrl[4].val[2] = 1;
765 
766  state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
767  state->Init_Ctrl[5].size = 1 ;
768  state->Init_Ctrl[5].addr[0] = 59;
769  state->Init_Ctrl[5].bit[0] = 0;
770  state->Init_Ctrl[5].val[0] = 0;
771 
772  state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
773  state->Init_Ctrl[6].size = 2 ;
774  state->Init_Ctrl[6].addr[0] = 53;
775  state->Init_Ctrl[6].bit[0] = 3;
776  state->Init_Ctrl[6].val[0] = 0;
777  state->Init_Ctrl[6].addr[1] = 53;
778  state->Init_Ctrl[6].bit[1] = 4;
779  state->Init_Ctrl[6].val[1] = 1;
780 
781  state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
782  state->Init_Ctrl[7].size = 4 ;
783  state->Init_Ctrl[7].addr[0] = 22;
784  state->Init_Ctrl[7].bit[0] = 4;
785  state->Init_Ctrl[7].val[0] = 0;
786  state->Init_Ctrl[7].addr[1] = 22;
787  state->Init_Ctrl[7].bit[1] = 5;
788  state->Init_Ctrl[7].val[1] = 1;
789  state->Init_Ctrl[7].addr[2] = 22;
790  state->Init_Ctrl[7].bit[2] = 6;
791  state->Init_Ctrl[7].val[2] = 1;
792  state->Init_Ctrl[7].addr[3] = 22;
793  state->Init_Ctrl[7].bit[3] = 7;
794  state->Init_Ctrl[7].val[3] = 0;
795 
796  state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
797  state->Init_Ctrl[8].size = 1 ;
798  state->Init_Ctrl[8].addr[0] = 22;
799  state->Init_Ctrl[8].bit[0] = 2;
800  state->Init_Ctrl[8].val[0] = 0;
801 
802  state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
803  state->Init_Ctrl[9].size = 4 ;
804  state->Init_Ctrl[9].addr[0] = 76;
805  state->Init_Ctrl[9].bit[0] = 0;
806  state->Init_Ctrl[9].val[0] = 1;
807  state->Init_Ctrl[9].addr[1] = 76;
808  state->Init_Ctrl[9].bit[1] = 1;
809  state->Init_Ctrl[9].val[1] = 1;
810  state->Init_Ctrl[9].addr[2] = 76;
811  state->Init_Ctrl[9].bit[2] = 2;
812  state->Init_Ctrl[9].val[2] = 0;
813  state->Init_Ctrl[9].addr[3] = 76;
814  state->Init_Ctrl[9].bit[3] = 3;
815  state->Init_Ctrl[9].val[3] = 1;
816 
817  state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
818  state->Init_Ctrl[10].size = 4 ;
819  state->Init_Ctrl[10].addr[0] = 76;
820  state->Init_Ctrl[10].bit[0] = 4;
821  state->Init_Ctrl[10].val[0] = 1;
822  state->Init_Ctrl[10].addr[1] = 76;
823  state->Init_Ctrl[10].bit[1] = 5;
824  state->Init_Ctrl[10].val[1] = 1;
825  state->Init_Ctrl[10].addr[2] = 76;
826  state->Init_Ctrl[10].bit[2] = 6;
827  state->Init_Ctrl[10].val[2] = 0;
828  state->Init_Ctrl[10].addr[3] = 76;
829  state->Init_Ctrl[10].bit[3] = 7;
830  state->Init_Ctrl[10].val[3] = 1;
831 
832  state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
833  state->Init_Ctrl[11].size = 5 ;
834  state->Init_Ctrl[11].addr[0] = 43;
835  state->Init_Ctrl[11].bit[0] = 3;
836  state->Init_Ctrl[11].val[0] = 0;
837  state->Init_Ctrl[11].addr[1] = 43;
838  state->Init_Ctrl[11].bit[1] = 4;
839  state->Init_Ctrl[11].val[1] = 0;
840  state->Init_Ctrl[11].addr[2] = 43;
841  state->Init_Ctrl[11].bit[2] = 5;
842  state->Init_Ctrl[11].val[2] = 0;
843  state->Init_Ctrl[11].addr[3] = 43;
844  state->Init_Ctrl[11].bit[3] = 6;
845  state->Init_Ctrl[11].val[3] = 1;
846  state->Init_Ctrl[11].addr[4] = 43;
847  state->Init_Ctrl[11].bit[4] = 7;
848  state->Init_Ctrl[11].val[4] = 0;
849 
850  state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
851  state->Init_Ctrl[12].size = 6 ;
852  state->Init_Ctrl[12].addr[0] = 44;
853  state->Init_Ctrl[12].bit[0] = 2;
854  state->Init_Ctrl[12].val[0] = 0;
855  state->Init_Ctrl[12].addr[1] = 44;
856  state->Init_Ctrl[12].bit[1] = 3;
857  state->Init_Ctrl[12].val[1] = 0;
858  state->Init_Ctrl[12].addr[2] = 44;
859  state->Init_Ctrl[12].bit[2] = 4;
860  state->Init_Ctrl[12].val[2] = 0;
861  state->Init_Ctrl[12].addr[3] = 44;
862  state->Init_Ctrl[12].bit[3] = 5;
863  state->Init_Ctrl[12].val[3] = 1;
864  state->Init_Ctrl[12].addr[4] = 44;
865  state->Init_Ctrl[12].bit[4] = 6;
866  state->Init_Ctrl[12].val[4] = 0;
867  state->Init_Ctrl[12].addr[5] = 44;
868  state->Init_Ctrl[12].bit[5] = 7;
869  state->Init_Ctrl[12].val[5] = 0;
870 
871  state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
872  state->Init_Ctrl[13].size = 7 ;
873  state->Init_Ctrl[13].addr[0] = 11;
874  state->Init_Ctrl[13].bit[0] = 0;
875  state->Init_Ctrl[13].val[0] = 1;
876  state->Init_Ctrl[13].addr[1] = 11;
877  state->Init_Ctrl[13].bit[1] = 1;
878  state->Init_Ctrl[13].val[1] = 0;
879  state->Init_Ctrl[13].addr[2] = 11;
880  state->Init_Ctrl[13].bit[2] = 2;
881  state->Init_Ctrl[13].val[2] = 0;
882  state->Init_Ctrl[13].addr[3] = 11;
883  state->Init_Ctrl[13].bit[3] = 3;
884  state->Init_Ctrl[13].val[3] = 1;
885  state->Init_Ctrl[13].addr[4] = 11;
886  state->Init_Ctrl[13].bit[4] = 4;
887  state->Init_Ctrl[13].val[4] = 1;
888  state->Init_Ctrl[13].addr[5] = 11;
889  state->Init_Ctrl[13].bit[5] = 5;
890  state->Init_Ctrl[13].val[5] = 0;
891  state->Init_Ctrl[13].addr[6] = 11;
892  state->Init_Ctrl[13].bit[6] = 6;
893  state->Init_Ctrl[13].val[6] = 0;
894 
895  state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
896  state->Init_Ctrl[14].size = 16 ;
897  state->Init_Ctrl[14].addr[0] = 13;
898  state->Init_Ctrl[14].bit[0] = 0;
899  state->Init_Ctrl[14].val[0] = 0;
900  state->Init_Ctrl[14].addr[1] = 13;
901  state->Init_Ctrl[14].bit[1] = 1;
902  state->Init_Ctrl[14].val[1] = 0;
903  state->Init_Ctrl[14].addr[2] = 13;
904  state->Init_Ctrl[14].bit[2] = 2;
905  state->Init_Ctrl[14].val[2] = 0;
906  state->Init_Ctrl[14].addr[3] = 13;
907  state->Init_Ctrl[14].bit[3] = 3;
908  state->Init_Ctrl[14].val[3] = 0;
909  state->Init_Ctrl[14].addr[4] = 13;
910  state->Init_Ctrl[14].bit[4] = 4;
911  state->Init_Ctrl[14].val[4] = 0;
912  state->Init_Ctrl[14].addr[5] = 13;
913  state->Init_Ctrl[14].bit[5] = 5;
914  state->Init_Ctrl[14].val[5] = 0;
915  state->Init_Ctrl[14].addr[6] = 13;
916  state->Init_Ctrl[14].bit[6] = 6;
917  state->Init_Ctrl[14].val[6] = 0;
918  state->Init_Ctrl[14].addr[7] = 13;
919  state->Init_Ctrl[14].bit[7] = 7;
920  state->Init_Ctrl[14].val[7] = 0;
921  state->Init_Ctrl[14].addr[8] = 12;
922  state->Init_Ctrl[14].bit[8] = 0;
923  state->Init_Ctrl[14].val[8] = 0;
924  state->Init_Ctrl[14].addr[9] = 12;
925  state->Init_Ctrl[14].bit[9] = 1;
926  state->Init_Ctrl[14].val[9] = 0;
927  state->Init_Ctrl[14].addr[10] = 12;
928  state->Init_Ctrl[14].bit[10] = 2;
929  state->Init_Ctrl[14].val[10] = 0;
930  state->Init_Ctrl[14].addr[11] = 12;
931  state->Init_Ctrl[14].bit[11] = 3;
932  state->Init_Ctrl[14].val[11] = 0;
933  state->Init_Ctrl[14].addr[12] = 12;
934  state->Init_Ctrl[14].bit[12] = 4;
935  state->Init_Ctrl[14].val[12] = 0;
936  state->Init_Ctrl[14].addr[13] = 12;
937  state->Init_Ctrl[14].bit[13] = 5;
938  state->Init_Ctrl[14].val[13] = 1;
939  state->Init_Ctrl[14].addr[14] = 12;
940  state->Init_Ctrl[14].bit[14] = 6;
941  state->Init_Ctrl[14].val[14] = 1;
942  state->Init_Ctrl[14].addr[15] = 12;
943  state->Init_Ctrl[14].bit[15] = 7;
944  state->Init_Ctrl[14].val[15] = 0;
945 
946  state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
947  state->Init_Ctrl[15].size = 3 ;
948  state->Init_Ctrl[15].addr[0] = 147;
949  state->Init_Ctrl[15].bit[0] = 2;
950  state->Init_Ctrl[15].val[0] = 0;
951  state->Init_Ctrl[15].addr[1] = 147;
952  state->Init_Ctrl[15].bit[1] = 3;
953  state->Init_Ctrl[15].val[1] = 1;
954  state->Init_Ctrl[15].addr[2] = 147;
955  state->Init_Ctrl[15].bit[2] = 4;
956  state->Init_Ctrl[15].val[2] = 1;
957 
958  state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
959  state->Init_Ctrl[16].size = 2 ;
960  state->Init_Ctrl[16].addr[0] = 147;
961  state->Init_Ctrl[16].bit[0] = 0;
962  state->Init_Ctrl[16].val[0] = 0;
963  state->Init_Ctrl[16].addr[1] = 147;
964  state->Init_Ctrl[16].bit[1] = 1;
965  state->Init_Ctrl[16].val[1] = 1;
966 
967  state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
968  state->Init_Ctrl[17].size = 1 ;
969  state->Init_Ctrl[17].addr[0] = 147;
970  state->Init_Ctrl[17].bit[0] = 7;
971  state->Init_Ctrl[17].val[0] = 0;
972 
973  state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
974  state->Init_Ctrl[18].size = 1 ;
975  state->Init_Ctrl[18].addr[0] = 147;
976  state->Init_Ctrl[18].bit[0] = 6;
977  state->Init_Ctrl[18].val[0] = 0;
978 
979  state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
980  state->Init_Ctrl[19].size = 1 ;
981  state->Init_Ctrl[19].addr[0] = 156;
982  state->Init_Ctrl[19].bit[0] = 0;
983  state->Init_Ctrl[19].val[0] = 0;
984 
985  state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
986  state->Init_Ctrl[20].size = 1 ;
987  state->Init_Ctrl[20].addr[0] = 147;
988  state->Init_Ctrl[20].bit[0] = 5;
989  state->Init_Ctrl[20].val[0] = 0;
990 
991  state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
992  state->Init_Ctrl[21].size = 1 ;
993  state->Init_Ctrl[21].addr[0] = 137;
994  state->Init_Ctrl[21].bit[0] = 4;
995  state->Init_Ctrl[21].val[0] = 0;
996 
997  state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
998  state->Init_Ctrl[22].size = 1 ;
999  state->Init_Ctrl[22].addr[0] = 137;
1000  state->Init_Ctrl[22].bit[0] = 7;
1001  state->Init_Ctrl[22].val[0] = 0;
1002 
1003  state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1004  state->Init_Ctrl[23].size = 1 ;
1005  state->Init_Ctrl[23].addr[0] = 91;
1006  state->Init_Ctrl[23].bit[0] = 5;
1007  state->Init_Ctrl[23].val[0] = 1;
1008 
1009  state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1010  state->Init_Ctrl[24].size = 1 ;
1011  state->Init_Ctrl[24].addr[0] = 43;
1012  state->Init_Ctrl[24].bit[0] = 0;
1013  state->Init_Ctrl[24].val[0] = 1;
1014 
1015  state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1016  state->Init_Ctrl[25].size = 2 ;
1017  state->Init_Ctrl[25].addr[0] = 22;
1018  state->Init_Ctrl[25].bit[0] = 0;
1019  state->Init_Ctrl[25].val[0] = 1;
1020  state->Init_Ctrl[25].addr[1] = 22;
1021  state->Init_Ctrl[25].bit[1] = 1;
1022  state->Init_Ctrl[25].val[1] = 1;
1023 
1024  state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1025  state->Init_Ctrl[26].size = 1 ;
1026  state->Init_Ctrl[26].addr[0] = 134;
1027  state->Init_Ctrl[26].bit[0] = 2;
1028  state->Init_Ctrl[26].val[0] = 0;
1029 
1030  state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1031  state->Init_Ctrl[27].size = 1 ;
1032  state->Init_Ctrl[27].addr[0] = 137;
1033  state->Init_Ctrl[27].bit[0] = 3;
1034  state->Init_Ctrl[27].val[0] = 0;
1035 
1036  state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1037  state->Init_Ctrl[28].size = 1 ;
1038  state->Init_Ctrl[28].addr[0] = 77;
1039  state->Init_Ctrl[28].bit[0] = 7;
1040  state->Init_Ctrl[28].val[0] = 0;
1041 
1042  state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1043  state->Init_Ctrl[29].size = 1 ;
1044  state->Init_Ctrl[29].addr[0] = 166;
1045  state->Init_Ctrl[29].bit[0] = 7;
1046  state->Init_Ctrl[29].val[0] = 1;
1047 
1048  state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1049  state->Init_Ctrl[30].size = 3 ;
1050  state->Init_Ctrl[30].addr[0] = 166;
1051  state->Init_Ctrl[30].bit[0] = 0;
1052  state->Init_Ctrl[30].val[0] = 0;
1053  state->Init_Ctrl[30].addr[1] = 166;
1054  state->Init_Ctrl[30].bit[1] = 1;
1055  state->Init_Ctrl[30].val[1] = 1;
1056  state->Init_Ctrl[30].addr[2] = 166;
1057  state->Init_Ctrl[30].bit[2] = 2;
1058  state->Init_Ctrl[30].val[2] = 1;
1059 
1060  state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1061  state->Init_Ctrl[31].size = 3 ;
1062  state->Init_Ctrl[31].addr[0] = 166;
1063  state->Init_Ctrl[31].bit[0] = 3;
1064  state->Init_Ctrl[31].val[0] = 1;
1065  state->Init_Ctrl[31].addr[1] = 166;
1066  state->Init_Ctrl[31].bit[1] = 4;
1067  state->Init_Ctrl[31].val[1] = 0;
1068  state->Init_Ctrl[31].addr[2] = 166;
1069  state->Init_Ctrl[31].bit[2] = 5;
1070  state->Init_Ctrl[31].val[2] = 1;
1071 
1072  state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1073  state->Init_Ctrl[32].size = 3 ;
1074  state->Init_Ctrl[32].addr[0] = 167;
1075  state->Init_Ctrl[32].bit[0] = 0;
1076  state->Init_Ctrl[32].val[0] = 1;
1077  state->Init_Ctrl[32].addr[1] = 167;
1078  state->Init_Ctrl[32].bit[1] = 1;
1079  state->Init_Ctrl[32].val[1] = 1;
1080  state->Init_Ctrl[32].addr[2] = 167;
1081  state->Init_Ctrl[32].bit[2] = 2;
1082  state->Init_Ctrl[32].val[2] = 0;
1083 
1084  state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1085  state->Init_Ctrl[33].size = 4 ;
1086  state->Init_Ctrl[33].addr[0] = 168;
1087  state->Init_Ctrl[33].bit[0] = 0;
1088  state->Init_Ctrl[33].val[0] = 0;
1089  state->Init_Ctrl[33].addr[1] = 168;
1090  state->Init_Ctrl[33].bit[1] = 1;
1091  state->Init_Ctrl[33].val[1] = 1;
1092  state->Init_Ctrl[33].addr[2] = 168;
1093  state->Init_Ctrl[33].bit[2] = 2;
1094  state->Init_Ctrl[33].val[2] = 0;
1095  state->Init_Ctrl[33].addr[3] = 168;
1096  state->Init_Ctrl[33].bit[3] = 3;
1097  state->Init_Ctrl[33].val[3] = 0;
1098 
1099  state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1100  state->Init_Ctrl[34].size = 4 ;
1101  state->Init_Ctrl[34].addr[0] = 168;
1102  state->Init_Ctrl[34].bit[0] = 4;
1103  state->Init_Ctrl[34].val[0] = 1;
1104  state->Init_Ctrl[34].addr[1] = 168;
1105  state->Init_Ctrl[34].bit[1] = 5;
1106  state->Init_Ctrl[34].val[1] = 1;
1107  state->Init_Ctrl[34].addr[2] = 168;
1108  state->Init_Ctrl[34].bit[2] = 6;
1109  state->Init_Ctrl[34].val[2] = 1;
1110  state->Init_Ctrl[34].addr[3] = 168;
1111  state->Init_Ctrl[34].bit[3] = 7;
1112  state->Init_Ctrl[34].val[3] = 1;
1113 
1114  state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1115  state->Init_Ctrl[35].size = 1 ;
1116  state->Init_Ctrl[35].addr[0] = 135;
1117  state->Init_Ctrl[35].bit[0] = 0;
1118  state->Init_Ctrl[35].val[0] = 0;
1119 
1120  state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1121  state->Init_Ctrl[36].size = 1 ;
1122  state->Init_Ctrl[36].addr[0] = 56;
1123  state->Init_Ctrl[36].bit[0] = 3;
1124  state->Init_Ctrl[36].val[0] = 0;
1125 
1126  state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1127  state->Init_Ctrl[37].size = 7 ;
1128  state->Init_Ctrl[37].addr[0] = 59;
1129  state->Init_Ctrl[37].bit[0] = 1;
1130  state->Init_Ctrl[37].val[0] = 0;
1131  state->Init_Ctrl[37].addr[1] = 59;
1132  state->Init_Ctrl[37].bit[1] = 2;
1133  state->Init_Ctrl[37].val[1] = 0;
1134  state->Init_Ctrl[37].addr[2] = 59;
1135  state->Init_Ctrl[37].bit[2] = 3;
1136  state->Init_Ctrl[37].val[2] = 0;
1137  state->Init_Ctrl[37].addr[3] = 59;
1138  state->Init_Ctrl[37].bit[3] = 4;
1139  state->Init_Ctrl[37].val[3] = 0;
1140  state->Init_Ctrl[37].addr[4] = 59;
1141  state->Init_Ctrl[37].bit[4] = 5;
1142  state->Init_Ctrl[37].val[4] = 0;
1143  state->Init_Ctrl[37].addr[5] = 59;
1144  state->Init_Ctrl[37].bit[5] = 6;
1145  state->Init_Ctrl[37].val[5] = 0;
1146  state->Init_Ctrl[37].addr[6] = 59;
1147  state->Init_Ctrl[37].bit[6] = 7;
1148  state->Init_Ctrl[37].val[6] = 0;
1149 
1150  state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1151  state->Init_Ctrl[38].size = 6 ;
1152  state->Init_Ctrl[38].addr[0] = 32;
1153  state->Init_Ctrl[38].bit[0] = 2;
1154  state->Init_Ctrl[38].val[0] = 0;
1155  state->Init_Ctrl[38].addr[1] = 32;
1156  state->Init_Ctrl[38].bit[1] = 3;
1157  state->Init_Ctrl[38].val[1] = 0;
1158  state->Init_Ctrl[38].addr[2] = 32;
1159  state->Init_Ctrl[38].bit[2] = 4;
1160  state->Init_Ctrl[38].val[2] = 0;
1161  state->Init_Ctrl[38].addr[3] = 32;
1162  state->Init_Ctrl[38].bit[3] = 5;
1163  state->Init_Ctrl[38].val[3] = 0;
1164  state->Init_Ctrl[38].addr[4] = 32;
1165  state->Init_Ctrl[38].bit[4] = 6;
1166  state->Init_Ctrl[38].val[4] = 1;
1167  state->Init_Ctrl[38].addr[5] = 32;
1168  state->Init_Ctrl[38].bit[5] = 7;
1169  state->Init_Ctrl[38].val[5] = 0;
1170 
1171  state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1172  state->Init_Ctrl[39].size = 1 ;
1173  state->Init_Ctrl[39].addr[0] = 25;
1174  state->Init_Ctrl[39].bit[0] = 3;
1175  state->Init_Ctrl[39].val[0] = 1;
1176 
1177 
1178  state->CH_Ctrl_Num = CHCTRL_NUM ;
1179 
1180  state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1181  state->CH_Ctrl[0].size = 2 ;
1182  state->CH_Ctrl[0].addr[0] = 68;
1183  state->CH_Ctrl[0].bit[0] = 6;
1184  state->CH_Ctrl[0].val[0] = 1;
1185  state->CH_Ctrl[0].addr[1] = 68;
1186  state->CH_Ctrl[0].bit[1] = 7;
1187  state->CH_Ctrl[0].val[1] = 1;
1188 
1189  state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1190  state->CH_Ctrl[1].size = 2 ;
1191  state->CH_Ctrl[1].addr[0] = 70;
1192  state->CH_Ctrl[1].bit[0] = 6;
1193  state->CH_Ctrl[1].val[0] = 1;
1194  state->CH_Ctrl[1].addr[1] = 70;
1195  state->CH_Ctrl[1].bit[1] = 7;
1196  state->CH_Ctrl[1].val[1] = 0;
1197 
1198  state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1199  state->CH_Ctrl[2].size = 9 ;
1200  state->CH_Ctrl[2].addr[0] = 69;
1201  state->CH_Ctrl[2].bit[0] = 5;
1202  state->CH_Ctrl[2].val[0] = 0;
1203  state->CH_Ctrl[2].addr[1] = 69;
1204  state->CH_Ctrl[2].bit[1] = 6;
1205  state->CH_Ctrl[2].val[1] = 0;
1206  state->CH_Ctrl[2].addr[2] = 69;
1207  state->CH_Ctrl[2].bit[2] = 7;
1208  state->CH_Ctrl[2].val[2] = 0;
1209  state->CH_Ctrl[2].addr[3] = 68;
1210  state->CH_Ctrl[2].bit[3] = 0;
1211  state->CH_Ctrl[2].val[3] = 0;
1212  state->CH_Ctrl[2].addr[4] = 68;
1213  state->CH_Ctrl[2].bit[4] = 1;
1214  state->CH_Ctrl[2].val[4] = 0;
1215  state->CH_Ctrl[2].addr[5] = 68;
1216  state->CH_Ctrl[2].bit[5] = 2;
1217  state->CH_Ctrl[2].val[5] = 0;
1218  state->CH_Ctrl[2].addr[6] = 68;
1219  state->CH_Ctrl[2].bit[6] = 3;
1220  state->CH_Ctrl[2].val[6] = 0;
1221  state->CH_Ctrl[2].addr[7] = 68;
1222  state->CH_Ctrl[2].bit[7] = 4;
1223  state->CH_Ctrl[2].val[7] = 0;
1224  state->CH_Ctrl[2].addr[8] = 68;
1225  state->CH_Ctrl[2].bit[8] = 5;
1226  state->CH_Ctrl[2].val[8] = 0;
1227 
1228  state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1229  state->CH_Ctrl[3].size = 1 ;
1230  state->CH_Ctrl[3].addr[0] = 70;
1231  state->CH_Ctrl[3].bit[0] = 5;
1232  state->CH_Ctrl[3].val[0] = 0;
1233 
1234  state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1235  state->CH_Ctrl[4].size = 3 ;
1236  state->CH_Ctrl[4].addr[0] = 73;
1237  state->CH_Ctrl[4].bit[0] = 4;
1238  state->CH_Ctrl[4].val[0] = 0;
1239  state->CH_Ctrl[4].addr[1] = 73;
1240  state->CH_Ctrl[4].bit[1] = 5;
1241  state->CH_Ctrl[4].val[1] = 1;
1242  state->CH_Ctrl[4].addr[2] = 73;
1243  state->CH_Ctrl[4].bit[2] = 6;
1244  state->CH_Ctrl[4].val[2] = 0;
1245 
1246  state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1247  state->CH_Ctrl[5].size = 4 ;
1248  state->CH_Ctrl[5].addr[0] = 70;
1249  state->CH_Ctrl[5].bit[0] = 0;
1250  state->CH_Ctrl[5].val[0] = 0;
1251  state->CH_Ctrl[5].addr[1] = 70;
1252  state->CH_Ctrl[5].bit[1] = 1;
1253  state->CH_Ctrl[5].val[1] = 0;
1254  state->CH_Ctrl[5].addr[2] = 70;
1255  state->CH_Ctrl[5].bit[2] = 2;
1256  state->CH_Ctrl[5].val[2] = 0;
1257  state->CH_Ctrl[5].addr[3] = 70;
1258  state->CH_Ctrl[5].bit[3] = 3;
1259  state->CH_Ctrl[5].val[3] = 0;
1260 
1261  state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1262  state->CH_Ctrl[6].size = 1 ;
1263  state->CH_Ctrl[6].addr[0] = 70;
1264  state->CH_Ctrl[6].bit[0] = 4;
1265  state->CH_Ctrl[6].val[0] = 1;
1266 
1267  state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1268  state->CH_Ctrl[7].size = 1 ;
1269  state->CH_Ctrl[7].addr[0] = 111;
1270  state->CH_Ctrl[7].bit[0] = 4;
1271  state->CH_Ctrl[7].val[0] = 0;
1272 
1273  state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1274  state->CH_Ctrl[8].size = 1 ;
1275  state->CH_Ctrl[8].addr[0] = 111;
1276  state->CH_Ctrl[8].bit[0] = 7;
1277  state->CH_Ctrl[8].val[0] = 1;
1278 
1279  state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1280  state->CH_Ctrl[9].size = 1 ;
1281  state->CH_Ctrl[9].addr[0] = 111;
1282  state->CH_Ctrl[9].bit[0] = 6;
1283  state->CH_Ctrl[9].val[0] = 1;
1284 
1285  state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1286  state->CH_Ctrl[10].size = 1 ;
1287  state->CH_Ctrl[10].addr[0] = 111;
1288  state->CH_Ctrl[10].bit[0] = 5;
1289  state->CH_Ctrl[10].val[0] = 0;
1290 
1291  state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1292  state->CH_Ctrl[11].size = 2 ;
1293  state->CH_Ctrl[11].addr[0] = 110;
1294  state->CH_Ctrl[11].bit[0] = 0;
1295  state->CH_Ctrl[11].val[0] = 1;
1296  state->CH_Ctrl[11].addr[1] = 110;
1297  state->CH_Ctrl[11].bit[1] = 1;
1298  state->CH_Ctrl[11].val[1] = 0;
1299 
1300  state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1301  state->CH_Ctrl[12].size = 3 ;
1302  state->CH_Ctrl[12].addr[0] = 69;
1303  state->CH_Ctrl[12].bit[0] = 2;
1304  state->CH_Ctrl[12].val[0] = 0;
1305  state->CH_Ctrl[12].addr[1] = 69;
1306  state->CH_Ctrl[12].bit[1] = 3;
1307  state->CH_Ctrl[12].val[1] = 0;
1308  state->CH_Ctrl[12].addr[2] = 69;
1309  state->CH_Ctrl[12].bit[2] = 4;
1310  state->CH_Ctrl[12].val[2] = 0;
1311 
1312  state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1313  state->CH_Ctrl[13].size = 6 ;
1314  state->CH_Ctrl[13].addr[0] = 110;
1315  state->CH_Ctrl[13].bit[0] = 2;
1316  state->CH_Ctrl[13].val[0] = 0;
1317  state->CH_Ctrl[13].addr[1] = 110;
1318  state->CH_Ctrl[13].bit[1] = 3;
1319  state->CH_Ctrl[13].val[1] = 0;
1320  state->CH_Ctrl[13].addr[2] = 110;
1321  state->CH_Ctrl[13].bit[2] = 4;
1322  state->CH_Ctrl[13].val[2] = 0;
1323  state->CH_Ctrl[13].addr[3] = 110;
1324  state->CH_Ctrl[13].bit[3] = 5;
1325  state->CH_Ctrl[13].val[3] = 0;
1326  state->CH_Ctrl[13].addr[4] = 110;
1327  state->CH_Ctrl[13].bit[4] = 6;
1328  state->CH_Ctrl[13].val[4] = 0;
1329  state->CH_Ctrl[13].addr[5] = 110;
1330  state->CH_Ctrl[13].bit[5] = 7;
1331  state->CH_Ctrl[13].val[5] = 1;
1332 
1333  state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1334  state->CH_Ctrl[14].size = 7 ;
1335  state->CH_Ctrl[14].addr[0] = 14;
1336  state->CH_Ctrl[14].bit[0] = 0;
1337  state->CH_Ctrl[14].val[0] = 0;
1338  state->CH_Ctrl[14].addr[1] = 14;
1339  state->CH_Ctrl[14].bit[1] = 1;
1340  state->CH_Ctrl[14].val[1] = 0;
1341  state->CH_Ctrl[14].addr[2] = 14;
1342  state->CH_Ctrl[14].bit[2] = 2;
1343  state->CH_Ctrl[14].val[2] = 0;
1344  state->CH_Ctrl[14].addr[3] = 14;
1345  state->CH_Ctrl[14].bit[3] = 3;
1346  state->CH_Ctrl[14].val[3] = 0;
1347  state->CH_Ctrl[14].addr[4] = 14;
1348  state->CH_Ctrl[14].bit[4] = 4;
1349  state->CH_Ctrl[14].val[4] = 0;
1350  state->CH_Ctrl[14].addr[5] = 14;
1351  state->CH_Ctrl[14].bit[5] = 5;
1352  state->CH_Ctrl[14].val[5] = 0;
1353  state->CH_Ctrl[14].addr[6] = 14;
1354  state->CH_Ctrl[14].bit[6] = 6;
1355  state->CH_Ctrl[14].val[6] = 0;
1356 
1357  state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1358  state->CH_Ctrl[15].size = 18 ;
1359  state->CH_Ctrl[15].addr[0] = 17;
1360  state->CH_Ctrl[15].bit[0] = 6;
1361  state->CH_Ctrl[15].val[0] = 0;
1362  state->CH_Ctrl[15].addr[1] = 17;
1363  state->CH_Ctrl[15].bit[1] = 7;
1364  state->CH_Ctrl[15].val[1] = 0;
1365  state->CH_Ctrl[15].addr[2] = 16;
1366  state->CH_Ctrl[15].bit[2] = 0;
1367  state->CH_Ctrl[15].val[2] = 0;
1368  state->CH_Ctrl[15].addr[3] = 16;
1369  state->CH_Ctrl[15].bit[3] = 1;
1370  state->CH_Ctrl[15].val[3] = 0;
1371  state->CH_Ctrl[15].addr[4] = 16;
1372  state->CH_Ctrl[15].bit[4] = 2;
1373  state->CH_Ctrl[15].val[4] = 0;
1374  state->CH_Ctrl[15].addr[5] = 16;
1375  state->CH_Ctrl[15].bit[5] = 3;
1376  state->CH_Ctrl[15].val[5] = 0;
1377  state->CH_Ctrl[15].addr[6] = 16;
1378  state->CH_Ctrl[15].bit[6] = 4;
1379  state->CH_Ctrl[15].val[6] = 0;
1380  state->CH_Ctrl[15].addr[7] = 16;
1381  state->CH_Ctrl[15].bit[7] = 5;
1382  state->CH_Ctrl[15].val[7] = 0;
1383  state->CH_Ctrl[15].addr[8] = 16;
1384  state->CH_Ctrl[15].bit[8] = 6;
1385  state->CH_Ctrl[15].val[8] = 0;
1386  state->CH_Ctrl[15].addr[9] = 16;
1387  state->CH_Ctrl[15].bit[9] = 7;
1388  state->CH_Ctrl[15].val[9] = 0;
1389  state->CH_Ctrl[15].addr[10] = 15;
1390  state->CH_Ctrl[15].bit[10] = 0;
1391  state->CH_Ctrl[15].val[10] = 0;
1392  state->CH_Ctrl[15].addr[11] = 15;
1393  state->CH_Ctrl[15].bit[11] = 1;
1394  state->CH_Ctrl[15].val[11] = 0;
1395  state->CH_Ctrl[15].addr[12] = 15;
1396  state->CH_Ctrl[15].bit[12] = 2;
1397  state->CH_Ctrl[15].val[12] = 0;
1398  state->CH_Ctrl[15].addr[13] = 15;
1399  state->CH_Ctrl[15].bit[13] = 3;
1400  state->CH_Ctrl[15].val[13] = 0;
1401  state->CH_Ctrl[15].addr[14] = 15;
1402  state->CH_Ctrl[15].bit[14] = 4;
1403  state->CH_Ctrl[15].val[14] = 0;
1404  state->CH_Ctrl[15].addr[15] = 15;
1405  state->CH_Ctrl[15].bit[15] = 5;
1406  state->CH_Ctrl[15].val[15] = 0;
1407  state->CH_Ctrl[15].addr[16] = 15;
1408  state->CH_Ctrl[15].bit[16] = 6;
1409  state->CH_Ctrl[15].val[16] = 1;
1410  state->CH_Ctrl[15].addr[17] = 15;
1411  state->CH_Ctrl[15].bit[17] = 7;
1412  state->CH_Ctrl[15].val[17] = 1;
1413 
1414  state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1415  state->CH_Ctrl[16].size = 5 ;
1416  state->CH_Ctrl[16].addr[0] = 112;
1417  state->CH_Ctrl[16].bit[0] = 0;
1418  state->CH_Ctrl[16].val[0] = 0;
1419  state->CH_Ctrl[16].addr[1] = 112;
1420  state->CH_Ctrl[16].bit[1] = 1;
1421  state->CH_Ctrl[16].val[1] = 0;
1422  state->CH_Ctrl[16].addr[2] = 112;
1423  state->CH_Ctrl[16].bit[2] = 2;
1424  state->CH_Ctrl[16].val[2] = 0;
1425  state->CH_Ctrl[16].addr[3] = 112;
1426  state->CH_Ctrl[16].bit[3] = 3;
1427  state->CH_Ctrl[16].val[3] = 0;
1428  state->CH_Ctrl[16].addr[4] = 112;
1429  state->CH_Ctrl[16].bit[4] = 4;
1430  state->CH_Ctrl[16].val[4] = 1;
1431 
1432  state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1433  state->CH_Ctrl[17].size = 1 ;
1434  state->CH_Ctrl[17].addr[0] = 14;
1435  state->CH_Ctrl[17].bit[0] = 7;
1436  state->CH_Ctrl[17].val[0] = 0;
1437 
1438  state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1439  state->CH_Ctrl[18].size = 4 ;
1440  state->CH_Ctrl[18].addr[0] = 107;
1441  state->CH_Ctrl[18].bit[0] = 3;
1442  state->CH_Ctrl[18].val[0] = 0;
1443  state->CH_Ctrl[18].addr[1] = 107;
1444  state->CH_Ctrl[18].bit[1] = 4;
1445  state->CH_Ctrl[18].val[1] = 0;
1446  state->CH_Ctrl[18].addr[2] = 107;
1447  state->CH_Ctrl[18].bit[2] = 5;
1448  state->CH_Ctrl[18].val[2] = 0;
1449  state->CH_Ctrl[18].addr[3] = 107;
1450  state->CH_Ctrl[18].bit[3] = 6;
1451  state->CH_Ctrl[18].val[3] = 0;
1452 
1453  state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1454  state->CH_Ctrl[19].size = 3 ;
1455  state->CH_Ctrl[19].addr[0] = 107;
1456  state->CH_Ctrl[19].bit[0] = 7;
1457  state->CH_Ctrl[19].val[0] = 1;
1458  state->CH_Ctrl[19].addr[1] = 106;
1459  state->CH_Ctrl[19].bit[1] = 0;
1460  state->CH_Ctrl[19].val[1] = 1;
1461  state->CH_Ctrl[19].addr[2] = 106;
1462  state->CH_Ctrl[19].bit[2] = 1;
1463  state->CH_Ctrl[19].val[2] = 1;
1464 
1465  state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1466  state->CH_Ctrl[20].size = 11 ;
1467  state->CH_Ctrl[20].addr[0] = 109;
1468  state->CH_Ctrl[20].bit[0] = 2;
1469  state->CH_Ctrl[20].val[0] = 0;
1470  state->CH_Ctrl[20].addr[1] = 109;
1471  state->CH_Ctrl[20].bit[1] = 3;
1472  state->CH_Ctrl[20].val[1] = 0;
1473  state->CH_Ctrl[20].addr[2] = 109;
1474  state->CH_Ctrl[20].bit[2] = 4;
1475  state->CH_Ctrl[20].val[2] = 0;
1476  state->CH_Ctrl[20].addr[3] = 109;
1477  state->CH_Ctrl[20].bit[3] = 5;
1478  state->CH_Ctrl[20].val[3] = 0;
1479  state->CH_Ctrl[20].addr[4] = 109;
1480  state->CH_Ctrl[20].bit[4] = 6;
1481  state->CH_Ctrl[20].val[4] = 0;
1482  state->CH_Ctrl[20].addr[5] = 109;
1483  state->CH_Ctrl[20].bit[5] = 7;
1484  state->CH_Ctrl[20].val[5] = 0;
1485  state->CH_Ctrl[20].addr[6] = 108;
1486  state->CH_Ctrl[20].bit[6] = 0;
1487  state->CH_Ctrl[20].val[6] = 0;
1488  state->CH_Ctrl[20].addr[7] = 108;
1489  state->CH_Ctrl[20].bit[7] = 1;
1490  state->CH_Ctrl[20].val[7] = 0;
1491  state->CH_Ctrl[20].addr[8] = 108;
1492  state->CH_Ctrl[20].bit[8] = 2;
1493  state->CH_Ctrl[20].val[8] = 1;
1494  state->CH_Ctrl[20].addr[9] = 108;
1495  state->CH_Ctrl[20].bit[9] = 3;
1496  state->CH_Ctrl[20].val[9] = 1;
1497  state->CH_Ctrl[20].addr[10] = 108;
1498  state->CH_Ctrl[20].bit[10] = 4;
1499  state->CH_Ctrl[20].val[10] = 1;
1500 
1501  state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1502  state->CH_Ctrl[21].size = 6 ;
1503  state->CH_Ctrl[21].addr[0] = 106;
1504  state->CH_Ctrl[21].bit[0] = 2;
1505  state->CH_Ctrl[21].val[0] = 0;
1506  state->CH_Ctrl[21].addr[1] = 106;
1507  state->CH_Ctrl[21].bit[1] = 3;
1508  state->CH_Ctrl[21].val[1] = 0;
1509  state->CH_Ctrl[21].addr[2] = 106;
1510  state->CH_Ctrl[21].bit[2] = 4;
1511  state->CH_Ctrl[21].val[2] = 0;
1512  state->CH_Ctrl[21].addr[3] = 106;
1513  state->CH_Ctrl[21].bit[3] = 5;
1514  state->CH_Ctrl[21].val[3] = 0;
1515  state->CH_Ctrl[21].addr[4] = 106;
1516  state->CH_Ctrl[21].bit[4] = 6;
1517  state->CH_Ctrl[21].val[4] = 0;
1518  state->CH_Ctrl[21].addr[5] = 106;
1519  state->CH_Ctrl[21].bit[5] = 7;
1520  state->CH_Ctrl[21].val[5] = 1;
1521 
1522  state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1523  state->CH_Ctrl[22].size = 1 ;
1524  state->CH_Ctrl[22].addr[0] = 138;
1525  state->CH_Ctrl[22].bit[0] = 4;
1526  state->CH_Ctrl[22].val[0] = 1;
1527 
1528  state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1529  state->CH_Ctrl[23].size = 1 ;
1530  state->CH_Ctrl[23].addr[0] = 17;
1531  state->CH_Ctrl[23].bit[0] = 5;
1532  state->CH_Ctrl[23].val[0] = 0;
1533 
1534  state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1535  state->CH_Ctrl[24].size = 1 ;
1536  state->CH_Ctrl[24].addr[0] = 111;
1537  state->CH_Ctrl[24].bit[0] = 3;
1538  state->CH_Ctrl[24].val[0] = 0;
1539 
1540  state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1541  state->CH_Ctrl[25].size = 1 ;
1542  state->CH_Ctrl[25].addr[0] = 112;
1543  state->CH_Ctrl[25].bit[0] = 7;
1544  state->CH_Ctrl[25].val[0] = 0;
1545 
1546  state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1547  state->CH_Ctrl[26].size = 1 ;
1548  state->CH_Ctrl[26].addr[0] = 136;
1549  state->CH_Ctrl[26].bit[0] = 7;
1550  state->CH_Ctrl[26].val[0] = 0;
1551 
1552  state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1553  state->CH_Ctrl[27].size = 1 ;
1554  state->CH_Ctrl[27].addr[0] = 149;
1555  state->CH_Ctrl[27].bit[0] = 7;
1556  state->CH_Ctrl[27].val[0] = 0;
1557 
1558  state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1559  state->CH_Ctrl[28].size = 1 ;
1560  state->CH_Ctrl[28].addr[0] = 149;
1561  state->CH_Ctrl[28].bit[0] = 6;
1562  state->CH_Ctrl[28].val[0] = 0;
1563 
1564  state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1565  state->CH_Ctrl[29].size = 1 ;
1566  state->CH_Ctrl[29].addr[0] = 149;
1567  state->CH_Ctrl[29].bit[0] = 5;
1568  state->CH_Ctrl[29].val[0] = 1;
1569 
1570  state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1571  state->CH_Ctrl[30].size = 1 ;
1572  state->CH_Ctrl[30].addr[0] = 149;
1573  state->CH_Ctrl[30].bit[0] = 4;
1574  state->CH_Ctrl[30].val[0] = 1;
1575 
1576  state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1577  state->CH_Ctrl[31].size = 1 ;
1578  state->CH_Ctrl[31].addr[0] = 149;
1579  state->CH_Ctrl[31].bit[0] = 3;
1580  state->CH_Ctrl[31].val[0] = 0;
1581 
1582  state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1583  state->CH_Ctrl[32].size = 1 ;
1584  state->CH_Ctrl[32].addr[0] = 93;
1585  state->CH_Ctrl[32].bit[0] = 1;
1586  state->CH_Ctrl[32].val[0] = 0;
1587 
1588  state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1589  state->CH_Ctrl[33].size = 1 ;
1590  state->CH_Ctrl[33].addr[0] = 93;
1591  state->CH_Ctrl[33].bit[0] = 0;
1592  state->CH_Ctrl[33].val[0] = 0;
1593 
1594  state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1595  state->CH_Ctrl[34].size = 6 ;
1596  state->CH_Ctrl[34].addr[0] = 92;
1597  state->CH_Ctrl[34].bit[0] = 2;
1598  state->CH_Ctrl[34].val[0] = 0;
1599  state->CH_Ctrl[34].addr[1] = 92;
1600  state->CH_Ctrl[34].bit[1] = 3;
1601  state->CH_Ctrl[34].val[1] = 0;
1602  state->CH_Ctrl[34].addr[2] = 92;
1603  state->CH_Ctrl[34].bit[2] = 4;
1604  state->CH_Ctrl[34].val[2] = 0;
1605  state->CH_Ctrl[34].addr[3] = 92;
1606  state->CH_Ctrl[34].bit[3] = 5;
1607  state->CH_Ctrl[34].val[3] = 0;
1608  state->CH_Ctrl[34].addr[4] = 92;
1609  state->CH_Ctrl[34].bit[4] = 6;
1610  state->CH_Ctrl[34].val[4] = 0;
1611  state->CH_Ctrl[34].addr[5] = 92;
1612  state->CH_Ctrl[34].bit[5] = 7;
1613  state->CH_Ctrl[34].val[5] = 0;
1614 
1615  state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1616  state->CH_Ctrl[35].size = 6 ;
1617  state->CH_Ctrl[35].addr[0] = 93;
1618  state->CH_Ctrl[35].bit[0] = 2;
1619  state->CH_Ctrl[35].val[0] = 0;
1620  state->CH_Ctrl[35].addr[1] = 93;
1621  state->CH_Ctrl[35].bit[1] = 3;
1622  state->CH_Ctrl[35].val[1] = 0;
1623  state->CH_Ctrl[35].addr[2] = 93;
1624  state->CH_Ctrl[35].bit[2] = 4;
1625  state->CH_Ctrl[35].val[2] = 0;
1626  state->CH_Ctrl[35].addr[3] = 93;
1627  state->CH_Ctrl[35].bit[3] = 5;
1628  state->CH_Ctrl[35].val[3] = 0;
1629  state->CH_Ctrl[35].addr[4] = 93;
1630  state->CH_Ctrl[35].bit[4] = 6;
1631  state->CH_Ctrl[35].val[4] = 0;
1632  state->CH_Ctrl[35].addr[5] = 93;
1633  state->CH_Ctrl[35].bit[5] = 7;
1634  state->CH_Ctrl[35].val[5] = 0;
1635 
1636 #ifdef _MXL_PRODUCTION
1637  state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1638  state->CH_Ctrl[36].size = 1 ;
1639  state->CH_Ctrl[36].addr[0] = 109;
1640  state->CH_Ctrl[36].bit[0] = 1;
1641  state->CH_Ctrl[36].val[0] = 1;
1642 
1643  state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1644  state->CH_Ctrl[37].size = 2 ;
1645  state->CH_Ctrl[37].addr[0] = 112;
1646  state->CH_Ctrl[37].bit[0] = 5;
1647  state->CH_Ctrl[37].val[0] = 0;
1648  state->CH_Ctrl[37].addr[1] = 112;
1649  state->CH_Ctrl[37].bit[1] = 6;
1650  state->CH_Ctrl[37].val[1] = 0;
1651 
1652  state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1653  state->CH_Ctrl[38].size = 1 ;
1654  state->CH_Ctrl[38].addr[0] = 65;
1655  state->CH_Ctrl[38].bit[0] = 1;
1656  state->CH_Ctrl[38].val[0] = 0;
1657 #endif
1658 
1659  return 0 ;
1660 }
1661 
1662 static void InitTunerControls(struct dvb_frontend *fe)
1663 {
1664  MXL5005_RegisterInit(fe);
1665  MXL5005_ControlInit(fe);
1666 #ifdef _MXL_INTERNAL
1667  MXL5005_MXLControlInit(fe);
1668 #endif
1669 }
1670 
1671 static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1672  u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
1673  u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
1674  u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
1675  u32 IF_out, /* Desired IF Out Frequency */
1676  u32 Fxtal, /* XTAL Frequency */
1677  u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1678  u16 TOP, /* 0: Dual AGC; Value: take over point */
1679  u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
1680  u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */
1681  u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
1682  u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
1683  u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
1684 
1685  /* Modulation Type; */
1686  /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1687  u8 Mod_Type,
1688 
1689  /* Tracking Filter */
1690  /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
1691  u8 TF_Type
1692  )
1693 {
1694  struct mxl5005s_state *state = fe->tuner_priv;
1695  u16 status = 0;
1696 
1697  state->Mode = Mode;
1698  state->IF_Mode = IF_mode;
1699  state->Chan_Bandwidth = Bandwidth;
1700  state->IF_OUT = IF_out;
1701  state->Fxtal = Fxtal;
1702  state->AGC_Mode = AGC_Mode;
1703  state->TOP = TOP;
1704  state->IF_OUT_LOAD = IF_OUT_LOAD;
1705  state->CLOCK_OUT = CLOCK_OUT;
1706  state->DIV_OUT = DIV_OUT;
1707  state->CAPSELECT = CAPSELECT;
1708  state->EN_RSSI = EN_RSSI;
1709  state->Mod_Type = Mod_Type;
1710  state->TF_Type = TF_Type;
1711 
1712  /* Initialize all the controls and registers */
1713  InitTunerControls(fe);
1714 
1715  /* Synthesizer LO frequency calculation */
1716  MXL_SynthIFLO_Calc(fe);
1717 
1718  return status;
1719 }
1720 
1721 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1722 {
1723  struct mxl5005s_state *state = fe->tuner_priv;
1724  if (state->Mode == 1) /* Digital Mode */
1725  state->IF_LO = state->IF_OUT;
1726  else /* Analog Mode */ {
1727  if (state->IF_Mode == 0) /* Analog Zero IF mode */
1728  state->IF_LO = state->IF_OUT + 400000;
1729  else /* Analog Low IF mode */
1730  state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1731  }
1732 }
1733 
1734 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1735 {
1736  struct mxl5005s_state *state = fe->tuner_priv;
1737 
1738  if (state->Mode == 1) /* Digital Mode */ {
1739  /* remove 20.48MHz setting for 2.6.10 */
1740  state->RF_LO = state->RF_IN;
1741  /* change for 2.6.6 */
1742  state->TG_LO = state->RF_IN - 750000;
1743  } else /* Analog Mode */ {
1744  if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
1745  state->RF_LO = state->RF_IN - 400000;
1746  state->TG_LO = state->RF_IN - 1750000;
1747  } else /* Analog Low IF mode */ {
1748  state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1749  state->TG_LO = state->RF_IN -
1750  state->Chan_Bandwidth + 500000;
1751  }
1752  }
1753 }
1754 
1755 static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1756 {
1757  u16 status = 0;
1758 
1759  status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1760  status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1761  status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1762  status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
1763 
1764  return status;
1765 }
1766 
1767 static u16 MXL_BlockInit(struct dvb_frontend *fe)
1768 {
1769  struct mxl5005s_state *state = fe->tuner_priv;
1770  u16 status = 0;
1771 
1772  status += MXL_OverwriteICDefault(fe);
1773 
1774  /* Downconverter Control Dig Ana */
1775  status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1776 
1777  /* Filter Control Dig Ana */
1778  status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1779  status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1780  status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1781  status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1782  status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1783 
1784  /* Initialize Low-Pass Filter */
1785  if (state->Mode) { /* Digital Mode */
1786  switch (state->Chan_Bandwidth) {
1787  case 8000000:
1788  status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1789  break;
1790  case 7000000:
1791  status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1792  break;
1793  case 6000000:
1794  status += MXL_ControlWrite(fe,
1795  BB_DLPF_BANDSEL, 3);
1796  break;
1797  }
1798  } else { /* Analog Mode */
1799  switch (state->Chan_Bandwidth) {
1800  case 8000000: /* Low Zero */
1801  status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1802  (state->IF_Mode ? 0 : 3));
1803  break;
1804  case 7000000:
1805  status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1806  (state->IF_Mode ? 1 : 4));
1807  break;
1808  case 6000000:
1809  status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1810  (state->IF_Mode ? 2 : 5));
1811  break;
1812  }
1813  }
1814 
1815  /* Charge Pump Control Dig Ana */
1816  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1817  status += MXL_ControlWrite(fe,
1818  RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1819  status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1820 
1821  /* AGC TOP Control */
1822  if (state->AGC_Mode == 0) /* Dual AGC */ {
1823  status += MXL_ControlWrite(fe, AGC_IF, 15);
1824  status += MXL_ControlWrite(fe, AGC_RF, 15);
1825  } else /* Single AGC Mode Dig Ana */
1826  status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1827 
1828  if (state->TOP == 55) /* TOP == 5.5 */
1829  status += MXL_ControlWrite(fe, AGC_IF, 0x0);
1830 
1831  if (state->TOP == 72) /* TOP == 7.2 */
1832  status += MXL_ControlWrite(fe, AGC_IF, 0x1);
1833 
1834  if (state->TOP == 92) /* TOP == 9.2 */
1835  status += MXL_ControlWrite(fe, AGC_IF, 0x2);
1836 
1837  if (state->TOP == 110) /* TOP == 11.0 */
1838  status += MXL_ControlWrite(fe, AGC_IF, 0x3);
1839 
1840  if (state->TOP == 129) /* TOP == 12.9 */
1841  status += MXL_ControlWrite(fe, AGC_IF, 0x4);
1842 
1843  if (state->TOP == 147) /* TOP == 14.7 */
1844  status += MXL_ControlWrite(fe, AGC_IF, 0x5);
1845 
1846  if (state->TOP == 168) /* TOP == 16.8 */
1847  status += MXL_ControlWrite(fe, AGC_IF, 0x6);
1848 
1849  if (state->TOP == 194) /* TOP == 19.4 */
1850  status += MXL_ControlWrite(fe, AGC_IF, 0x7);
1851 
1852  if (state->TOP == 212) /* TOP == 21.2 */
1853  status += MXL_ControlWrite(fe, AGC_IF, 0x9);
1854 
1855  if (state->TOP == 232) /* TOP == 23.2 */
1856  status += MXL_ControlWrite(fe, AGC_IF, 0xA);
1857 
1858  if (state->TOP == 252) /* TOP == 25.2 */
1859  status += MXL_ControlWrite(fe, AGC_IF, 0xB);
1860 
1861  if (state->TOP == 271) /* TOP == 27.1 */
1862  status += MXL_ControlWrite(fe, AGC_IF, 0xC);
1863 
1864  if (state->TOP == 292) /* TOP == 29.2 */
1865  status += MXL_ControlWrite(fe, AGC_IF, 0xD);
1866 
1867  if (state->TOP == 317) /* TOP == 31.7 */
1868  status += MXL_ControlWrite(fe, AGC_IF, 0xE);
1869 
1870  if (state->TOP == 349) /* TOP == 34.9 */
1871  status += MXL_ControlWrite(fe, AGC_IF, 0xF);
1872 
1873  /* IF Synthesizer Control */
1874  status += MXL_IFSynthInit(fe);
1875 
1876  /* IF UpConverter Control */
1877  if (state->IF_OUT_LOAD == 200) {
1878  status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
1879  status += MXL_ControlWrite(fe, I_DRIVER, 2);
1880  }
1881  if (state->IF_OUT_LOAD == 300) {
1882  status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
1883  status += MXL_ControlWrite(fe, I_DRIVER, 1);
1884  }
1885 
1886  /* Anti-Alias Filtering Control
1887  * initialise Anti-Aliasing Filter
1888  */
1889  if (state->Mode) { /* Digital Mode */
1890  if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
1891  status += MXL_ControlWrite(fe, EN_AAF, 1);
1892  status += MXL_ControlWrite(fe, EN_3P, 1);
1893  status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1894  status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1895  }
1896  if ((state->IF_OUT == 36125000UL) ||
1897  (state->IF_OUT == 36150000UL)) {
1898  status += MXL_ControlWrite(fe, EN_AAF, 1);
1899  status += MXL_ControlWrite(fe, EN_3P, 1);
1900  status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1901  status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1902  }
1903  if (state->IF_OUT > 36150000UL) {
1904  status += MXL_ControlWrite(fe, EN_AAF, 0);
1905  status += MXL_ControlWrite(fe, EN_3P, 1);
1906  status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1907  status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1908  }
1909  } else { /* Analog Mode */
1910  if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
1911  status += MXL_ControlWrite(fe, EN_AAF, 1);
1912  status += MXL_ControlWrite(fe, EN_3P, 1);
1913  status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1914  status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1915  }
1916  if (state->IF_OUT > 5000000UL) {
1917  status += MXL_ControlWrite(fe, EN_AAF, 0);
1918  status += MXL_ControlWrite(fe, EN_3P, 0);
1919  status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
1920  status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1921  }
1922  }
1923 
1924  /* Demod Clock Out */
1925  if (state->CLOCK_OUT)
1926  status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
1927  else
1928  status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
1929 
1930  if (state->DIV_OUT == 1)
1931  status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
1932  if (state->DIV_OUT == 0)
1933  status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
1934 
1935  /* Crystal Control */
1936  if (state->CAPSELECT)
1937  status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
1938  else
1939  status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
1940 
1941  if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
1942  status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
1943  if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
1944  status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
1945 
1946  if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
1947  status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
1948  if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
1949  status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
1950 
1951  /* Misc Controls */
1952  if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
1953  status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
1954  else
1955  status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
1956 
1957  /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
1958 
1959  /* Set TG_R_DIV */
1960  status += MXL_ControlWrite(fe, TG_R_DIV,
1961  MXL_Ceiling(state->Fxtal, 1000000));
1962 
1963  /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
1964 
1965  /* RSSI Control */
1966  if (state->EN_RSSI) {
1967  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1968  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1969  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1970  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1971 
1972  /* RSSI reference point */
1973  status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
1974  status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
1975  status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1976 
1977  /* TOP point */
1978  status += MXL_ControlWrite(fe, RFA_FLR, 0);
1979  status += MXL_ControlWrite(fe, RFA_CEIL, 12);
1980  }
1981 
1982  /* Modulation type bit settings
1983  * Override the control values preset
1984  */
1985  if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
1986  state->AGC_Mode = 1; /* Single AGC Mode */
1987 
1988  /* Enable RSSI */
1989  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1990  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1991  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1992  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1993 
1994  /* RSSI reference point */
1995  status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
1996  status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
1997  status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1998 
1999  /* TOP point */
2000  status += MXL_ControlWrite(fe, RFA_FLR, 2);
2001  status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2002  if (state->IF_OUT <= 6280000UL) /* Low IF */
2003  status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2004  else /* High IF */
2005  status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2006 
2007  }
2008  if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
2009  state->AGC_Mode = 1; /* Single AGC Mode */
2010 
2011  /* Enable RSSI */
2012  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2013  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2014  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2015  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2016 
2017  /* RSSI reference point */
2018  status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2019  status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2020  status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2021 
2022  /* TOP point */
2023  status += MXL_ControlWrite(fe, RFA_FLR, 2);
2024  status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2025  status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2026  /* Low Zero */
2027  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
2028 
2029  if (state->IF_OUT <= 6280000UL) /* Low IF */
2030  status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2031  else /* High IF */
2032  status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2033  }
2034  if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
2035  state->Mode = MXL_DIGITAL_MODE;
2036 
2037  /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2038 
2039  /* Disable RSSI */ /* change here for v2.6.5 */
2040  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2041  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2042  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2043  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2044 
2045  /* RSSI reference point */
2046  status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2047  status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2048  status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2049  /* change here for v2.6.5 */
2050  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2051 
2052  if (state->IF_OUT <= 6280000UL) /* Low IF */
2053  status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2054  else /* High IF */
2055  status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2056  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2057 
2058  }
2059  if (state->Mod_Type == MXL_ANALOG_CABLE) {
2060  /* Analog Cable Mode */
2061  /* state->Mode = MXL_DIGITAL_MODE; */
2062 
2063  state->AGC_Mode = 1; /* Single AGC Mode */
2064 
2065  /* Disable RSSI */
2066  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2067  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2068  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2069  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2070  /* change for 2.6.3 */
2071  status += MXL_ControlWrite(fe, AGC_IF, 1);
2072  status += MXL_ControlWrite(fe, AGC_RF, 15);
2073  status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2074  }
2075 
2076  if (state->Mod_Type == MXL_ANALOG_OTA) {
2077  /* Analog OTA Terrestrial mode add for 2.6.7 */
2078  /* state->Mode = MXL_ANALOG_MODE; */
2079 
2080  /* Enable RSSI */
2081  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2082  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2083  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2084  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2085 
2086  /* RSSI reference point */
2087  status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2088  status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2089  status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2090  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2091  status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2092  }
2093 
2094  /* RSSI disable */
2095  if (state->EN_RSSI == 0) {
2096  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2097  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2098  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2099  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2100  }
2101 
2102  return status;
2103 }
2104 
2105 static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2106 {
2107  struct mxl5005s_state *state = fe->tuner_priv;
2108  u16 status = 0 ;
2109  u32 Fref = 0 ;
2110  u32 Kdbl, intModVal ;
2111  u32 fracModVal ;
2112  Kdbl = 2 ;
2113 
2114  if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2115  Kdbl = 2 ;
2116  if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2117  Kdbl = 1 ;
2118 
2119  /* IF Synthesizer Control */
2120  if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
2121  if (state->IF_LO == 41000000UL) {
2122  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2123  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2124  Fref = 328000000UL ;
2125  }
2126  if (state->IF_LO == 47000000UL) {
2127  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2128  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2129  Fref = 376000000UL ;
2130  }
2131  if (state->IF_LO == 54000000UL) {
2132  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2133  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2134  Fref = 324000000UL ;
2135  }
2136  if (state->IF_LO == 60000000UL) {
2137  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2138  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2139  Fref = 360000000UL ;
2140  }
2141  if (state->IF_LO == 39250000UL) {
2142  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2143  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2144  Fref = 314000000UL ;
2145  }
2146  if (state->IF_LO == 39650000UL) {
2147  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2148  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2149  Fref = 317200000UL ;
2150  }
2151  if (state->IF_LO == 40150000UL) {
2152  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2153  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2154  Fref = 321200000UL ;
2155  }
2156  if (state->IF_LO == 40650000UL) {
2157  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2158  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2159  Fref = 325200000UL ;
2160  }
2161  }
2162 
2163  if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
2164  if (state->IF_LO == 57000000UL) {
2165  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2166  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2167  Fref = 342000000UL ;
2168  }
2169  if (state->IF_LO == 44000000UL) {
2170  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2171  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2172  Fref = 352000000UL ;
2173  }
2174  if (state->IF_LO == 43750000UL) {
2175  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2176  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2177  Fref = 350000000UL ;
2178  }
2179  if (state->IF_LO == 36650000UL) {
2180  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2181  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2182  Fref = 366500000UL ;
2183  }
2184  if (state->IF_LO == 36150000UL) {
2185  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2186  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2187  Fref = 361500000UL ;
2188  }
2189  if (state->IF_LO == 36000000UL) {
2190  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2191  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2192  Fref = 360000000UL ;
2193  }
2194  if (state->IF_LO == 35250000UL) {
2195  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2196  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2197  Fref = 352500000UL ;
2198  }
2199  if (state->IF_LO == 34750000UL) {
2200  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2201  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2202  Fref = 347500000UL ;
2203  }
2204  if (state->IF_LO == 6280000UL) {
2205  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2206  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2207  Fref = 376800000UL ;
2208  }
2209  if (state->IF_LO == 5000000UL) {
2210  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2211  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2212  Fref = 360000000UL ;
2213  }
2214  if (state->IF_LO == 4500000UL) {
2215  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2216  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2217  Fref = 360000000UL ;
2218  }
2219  if (state->IF_LO == 4570000UL) {
2220  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2221  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2222  Fref = 365600000UL ;
2223  }
2224  if (state->IF_LO == 4000000UL) {
2225  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2226  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2227  Fref = 360000000UL ;
2228  }
2229  if (state->IF_LO == 57400000UL) {
2230  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2231  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2232  Fref = 344400000UL ;
2233  }
2234  if (state->IF_LO == 44400000UL) {
2235  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2236  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2237  Fref = 355200000UL ;
2238  }
2239  if (state->IF_LO == 44150000UL) {
2240  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2241  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2242  Fref = 353200000UL ;
2243  }
2244  if (state->IF_LO == 37050000UL) {
2245  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2246  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2247  Fref = 370500000UL ;
2248  }
2249  if (state->IF_LO == 36550000UL) {
2250  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2251  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2252  Fref = 365500000UL ;
2253  }
2254  if (state->IF_LO == 36125000UL) {
2255  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2256  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2257  Fref = 361250000UL ;
2258  }
2259  if (state->IF_LO == 6000000UL) {
2260  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2261  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2262  Fref = 360000000UL ;
2263  }
2264  if (state->IF_LO == 5400000UL) {
2265  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2266  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2267  Fref = 324000000UL ;
2268  }
2269  if (state->IF_LO == 5380000UL) {
2270  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2271  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2272  Fref = 322800000UL ;
2273  }
2274  if (state->IF_LO == 5200000UL) {
2275  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2276  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2277  Fref = 374400000UL ;
2278  }
2279  if (state->IF_LO == 4900000UL) {
2280  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2281  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2282  Fref = 352800000UL ;
2283  }
2284  if (state->IF_LO == 4400000UL) {
2285  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2286  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2287  Fref = 352000000UL ;
2288  }
2289  if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ {
2290  status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2291  status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2292  Fref = 365670000UL ;
2293  }
2294  }
2295  /* CHCAL_INT_MOD_IF */
2296  /* CHCAL_FRAC_MOD_IF */
2297  intModVal = Fref / (state->Fxtal * Kdbl/2);
2298  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
2299 
2300  fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
2301  intModVal);
2302 
2303  fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
2304  status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
2305 
2306  return status ;
2307 }
2308 
2309 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2310 {
2311  struct mxl5005s_state *state = fe->tuner_priv;
2312  u16 status = 0;
2313  u32 divider_val, E3, E4, E5, E5A;
2314  u32 Fmax, Fmin, FmaxBin, FminBin;
2315  u32 Kdbl_RF = 2;
2316  u32 tg_divval;
2317  u32 tg_lo;
2318 
2319  u32 Fref_TG;
2320  u32 Fvco;
2321 
2322  state->RF_IN = RF_Freq;
2323 
2324  MXL_SynthRFTGLO_Calc(fe);
2325 
2326  if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2327  Kdbl_RF = 2;
2328  if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2329  Kdbl_RF = 1;
2330 
2331  /* Downconverter Controls
2332  * Look-Up Table Implementation for:
2333  * DN_POLY
2334  * DN_RFGAIN
2335  * DN_CAP_RFLPF
2336  * DN_EN_VHFUHFBAR
2337  * DN_GAIN_ADJUST
2338  * Change the boundary reference from RF_IN to RF_LO
2339  */
2340  if (state->RF_LO < 40000000UL)
2341  return -1;
2342 
2343  if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2344  status += MXL_ControlWrite(fe, DN_POLY, 2);
2345  status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2346  status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
2347  status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2348  status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2349  }
2350  if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2351  status += MXL_ControlWrite(fe, DN_POLY, 3);
2352  status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2353  status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
2354  status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2355  status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2356  }
2357  if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2358  status += MXL_ControlWrite(fe, DN_POLY, 3);
2359  status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2360  status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
2361  status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2362  status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2363  }
2364  if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2365  status += MXL_ControlWrite(fe, DN_POLY, 3);
2366  status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2367  status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
2368  status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2369  status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2370  }
2371  if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2372  status += MXL_ControlWrite(fe, DN_POLY, 3);
2373  status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2374  status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2375  status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2376  status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2377  }
2378  if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2379  status += MXL_ControlWrite(fe, DN_POLY, 3);
2380  status += MXL_ControlWrite(fe, DN_RFGAIN, 1);
2381  status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2382  status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2383  status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2384  }
2385  if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2386  status += MXL_ControlWrite(fe, DN_POLY, 3);
2387  status += MXL_ControlWrite(fe, DN_RFGAIN, 2);
2388  status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2389  status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2390  status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2391  }
2392  if (state->RF_LO > 900000000UL)
2393  return -1;
2394 
2395  /* DN_IQTNBUF_AMP */
2396  /* DN_IQTNGNBFBIAS_BST */
2397  if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2398  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2399  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2400  }
2401  if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2402  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2403  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2404  }
2405  if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2406  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2407  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2408  }
2409  if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2410  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2411  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2412  }
2413  if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2414  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2415  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2416  }
2417  if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2418  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2419  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2420  }
2421  if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2422  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2423  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2424  }
2425  if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2426  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2427  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2428  }
2429  if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2430  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2431  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2432  }
2433  if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2434  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2435  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2436  }
2437  if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2438  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2439  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2440  }
2441  if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2442  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2443  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2444  }
2445  if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2446  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2447  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2448  }
2449  if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2450  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2451  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2452  }
2453  if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2454  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2455  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2456  }
2457  if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2458  status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2459  status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2460  }
2461 
2462  /*
2463  * Set RF Synth and LO Path Control
2464  *
2465  * Look-Up table implementation for:
2466  * RFSYN_EN_OUTMUX
2467  * RFSYN_SEL_VCO_OUT
2468  * RFSYN_SEL_VCO_HI
2469  * RFSYN_SEL_DIVM
2470  * RFSYN_RF_DIV_BIAS
2471  * DN_SEL_FREQ
2472  *
2473  * Set divider_val, Fmax, Fmix to use in Equations
2474  */
2475  FminBin = 28000000UL ;
2476  FmaxBin = 42500000UL ;
2477  if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2478  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2479  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2480  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2481  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2482  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2483  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2484  divider_val = 64 ;
2485  Fmax = FmaxBin ;
2486  Fmin = FminBin ;
2487  }
2488  FminBin = 42500000UL ;
2489  FmaxBin = 56000000UL ;
2490  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2491  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2492  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2493  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2494  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2495  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2496  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2497  divider_val = 64 ;
2498  Fmax = FmaxBin ;
2499  Fmin = FminBin ;
2500  }
2501  FminBin = 56000000UL ;
2502  FmaxBin = 85000000UL ;
2503  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2504  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2505  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2506  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2507  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2508  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2509  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2510  divider_val = 32 ;
2511  Fmax = FmaxBin ;
2512  Fmin = FminBin ;
2513  }
2514  FminBin = 85000000UL ;
2515  FmaxBin = 112000000UL ;
2516  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2517  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2518  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2519  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2520  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2521  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2522  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2523  divider_val = 32 ;
2524  Fmax = FmaxBin ;
2525  Fmin = FminBin ;
2526  }
2527  FminBin = 112000000UL ;
2528  FmaxBin = 170000000UL ;
2529  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2530  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2531  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2532  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2533  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2534  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2535  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2536  divider_val = 16 ;
2537  Fmax = FmaxBin ;
2538  Fmin = FminBin ;
2539  }
2540  FminBin = 170000000UL ;
2541  FmaxBin = 225000000UL ;
2542  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2543  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2544  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2545  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2546  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2547  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2548  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2549  divider_val = 16 ;
2550  Fmax = FmaxBin ;
2551  Fmin = FminBin ;
2552  }
2553  FminBin = 225000000UL ;
2554  FmaxBin = 300000000UL ;
2555  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2556  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2557  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2558  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2559  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2560  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2561  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4);
2562  divider_val = 8 ;
2563  Fmax = 340000000UL ;
2564  Fmin = FminBin ;
2565  }
2566  FminBin = 300000000UL ;
2567  FmaxBin = 340000000UL ;
2568  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2569  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2570  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2571  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2572  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2573  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2574  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2575  divider_val = 8 ;
2576  Fmax = FmaxBin ;
2577  Fmin = 225000000UL ;
2578  }
2579  FminBin = 340000000UL ;
2580  FmaxBin = 450000000UL ;
2581  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2582  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2583  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2584  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2585  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2586  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2);
2587  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2588  divider_val = 8 ;
2589  Fmax = FmaxBin ;
2590  Fmin = FminBin ;
2591  }
2592  FminBin = 450000000UL ;
2593  FmaxBin = 680000000UL ;
2594  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2595  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2596  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2597  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2598  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2599  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2600  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2601  divider_val = 4 ;
2602  Fmax = FmaxBin ;
2603  Fmin = FminBin ;
2604  }
2605  FminBin = 680000000UL ;
2606  FmaxBin = 900000000UL ;
2607  if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2608  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2609  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2610  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2611  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2612  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2613  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2614  divider_val = 4 ;
2615  Fmax = FmaxBin ;
2616  Fmin = FminBin ;
2617  }
2618 
2619  /* CHCAL_INT_MOD_RF
2620  * CHCAL_FRAC_MOD_RF
2621  * RFSYN_LPF_R
2622  * CHCAL_EN_INT_RF
2623  */
2624  /* Equation E3 RFSYN_VCO_BIAS */
2625  E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2626  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
2627 
2628  /* Equation E4 CHCAL_INT_MOD_RF */
2629  E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
2630  MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
2631 
2632  /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */
2633  E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
2634  (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
2635  (2*state->Fxtal*Kdbl_RF/10000);
2636 
2637  status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2638 
2639  /* Equation E5A RFSYN_LPF_R */
2640  E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2641  status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
2642 
2643  /* Euqation E5B CHCAL_EN_INIT_RF */
2644  status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2645  /*if (E5 == 0)
2646  * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2647  *else
2648  * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2649  */
2650 
2651  /*
2652  * Set TG Synth
2653  *
2654  * Look-Up table implementation for:
2655  * TG_LO_DIVVAL
2656  * TG_LO_SELVAL
2657  *
2658  * Set divider_val, Fmax, Fmix to use in Equations
2659  */
2660  if (state->TG_LO < 33000000UL)
2661  return -1;
2662 
2663  FminBin = 33000000UL ;
2664  FmaxBin = 50000000UL ;
2665  if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2666  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6);
2667  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2668  divider_val = 36 ;
2669  Fmax = FmaxBin ;
2670  Fmin = FminBin ;
2671  }
2672  FminBin = 50000000UL ;
2673  FmaxBin = 67000000UL ;
2674  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2675  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1);
2676  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2677  divider_val = 24 ;
2678  Fmax = FmaxBin ;
2679  Fmin = FminBin ;
2680  }
2681  FminBin = 67000000UL ;
2682  FmaxBin = 100000000UL ;
2683  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2684  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC);
2685  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2686  divider_val = 18 ;
2687  Fmax = FmaxBin ;
2688  Fmin = FminBin ;
2689  }
2690  FminBin = 100000000UL ;
2691  FmaxBin = 150000000UL ;
2692  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2693  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2694  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2695  divider_val = 12 ;
2696  Fmax = FmaxBin ;
2697  Fmin = FminBin ;
2698  }
2699  FminBin = 150000000UL ;
2700  FmaxBin = 200000000UL ;
2701  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2702  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2703  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2704  divider_val = 8 ;
2705  Fmax = FmaxBin ;
2706  Fmin = FminBin ;
2707  }
2708  FminBin = 200000000UL ;
2709  FmaxBin = 300000000UL ;
2710  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2711  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2712  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2713  divider_val = 6 ;
2714  Fmax = FmaxBin ;
2715  Fmin = FminBin ;
2716  }
2717  FminBin = 300000000UL ;
2718  FmaxBin = 400000000UL ;
2719  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2720  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2721  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2722  divider_val = 4 ;
2723  Fmax = FmaxBin ;
2724  Fmin = FminBin ;
2725  }
2726  FminBin = 400000000UL ;
2727  FmaxBin = 600000000UL ;
2728  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2729  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2730  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2731  divider_val = 3 ;
2732  Fmax = FmaxBin ;
2733  Fmin = FminBin ;
2734  }
2735  FminBin = 600000000UL ;
2736  FmaxBin = 900000000UL ;
2737  if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2738  status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2739  status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2740  divider_val = 2 ;
2741  Fmax = FmaxBin ;
2742  Fmin = FminBin ;
2743  }
2744 
2745  /* TG_DIV_VAL */
2746  tg_divval = (state->TG_LO*divider_val/100000) *
2747  (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
2748  (state->Fxtal/1000);
2749 
2750  status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
2751 
2752  if (state->TG_LO > 600000000UL)
2753  status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
2754 
2755  Fmax = 1800000000UL ;
2756  Fmin = 1200000000UL ;
2757 
2758  /* prevent overflow of 32 bit unsigned integer, use
2759  * following equation. Edit for v2.6.4
2760  */
2761  /* Fref_TF = Fref_TG * 1000 */
2762  Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
2763 
2764  /* Fvco = Fvco/10 */
2765  Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
2766 
2767  tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
2768 
2769  /* below equation is same as above but much harder to debug.
2770  *
2771  * static u32 MXL_GetXtalInt(u32 Xtal_Freq)
2772  * {
2773  * if ((Xtal_Freq % 1000000) == 0)
2774  * return (Xtal_Freq / 10000);
2775  * else
2776  * return (((Xtal_Freq / 1000000) + 1)*100);
2777  * }
2778  *
2779  * u32 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2780  * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) -
2781  * ((state->TG_LO/10000)*divider_val *
2782  * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
2783  * Xtal_Int/100) + 8;
2784  */
2785 
2786  status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
2787 
2788  /* add for 2.6.5 Special setting for QAM */
2789  if (state->Mod_Type == MXL_QAM) {
2790  if (state->config->qam_gain != 0)
2791  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,
2792  state->config->qam_gain);
2793  else if (state->RF_IN < 680000000)
2794  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2795  else
2796  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2797  }
2798 
2799  /* Off Chip Tracking Filter Control */
2800  if (state->TF_Type == MXL_TF_OFF) {
2801  /* Tracking Filter Off State; turn off all the banks */
2802  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2803  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2804  status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
2805  status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
2806  status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
2807  }
2808 
2809  if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
2810  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2811  status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2812 
2813  if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2814  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2815  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2816  status += MXL_SetGPIO(fe, 3, 0);
2817  status += MXL_SetGPIO(fe, 1, 1);
2818  status += MXL_SetGPIO(fe, 4, 1);
2819  }
2820  if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2821  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2822  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2823  status += MXL_SetGPIO(fe, 3, 1);
2824  status += MXL_SetGPIO(fe, 1, 0);
2825  status += MXL_SetGPIO(fe, 4, 1);
2826  }
2827  if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2828  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2829  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2830  status += MXL_SetGPIO(fe, 3, 1);
2831  status += MXL_SetGPIO(fe, 1, 0);
2832  status += MXL_SetGPIO(fe, 4, 0);
2833  }
2834  if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2835  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2836  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2837  status += MXL_SetGPIO(fe, 3, 1);
2838  status += MXL_SetGPIO(fe, 1, 1);
2839  status += MXL_SetGPIO(fe, 4, 0);
2840  }
2841  if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2842  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2843  status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
2844  status += MXL_SetGPIO(fe, 3, 1);
2845  status += MXL_SetGPIO(fe, 1, 1);
2846  status += MXL_SetGPIO(fe, 4, 0);
2847  }
2848  if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2849  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2850  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2851  status += MXL_SetGPIO(fe, 3, 1);
2852  status += MXL_SetGPIO(fe, 1, 1);
2853  status += MXL_SetGPIO(fe, 4, 0);
2854  }
2855  if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2856  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2857  status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
2858  status += MXL_SetGPIO(fe, 3, 1);
2859  status += MXL_SetGPIO(fe, 1, 1);
2860  status += MXL_SetGPIO(fe, 4, 1);
2861  }
2862  if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2863  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2864  status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
2865  status += MXL_SetGPIO(fe, 3, 1);
2866  status += MXL_SetGPIO(fe, 1, 1);
2867  status += MXL_SetGPIO(fe, 4, 1);
2868  }
2869  if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2870  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2871  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2872  status += MXL_SetGPIO(fe, 3, 1);
2873  status += MXL_SetGPIO(fe, 1, 1);
2874  status += MXL_SetGPIO(fe, 4, 1);
2875  }
2876  }
2877 
2878  if (state->TF_Type == MXL_TF_C_H) {
2879 
2880  /* Tracking Filter type C-H for Hauppauge only */
2881  status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2882 
2883  if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2884  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2885  status += MXL_SetGPIO(fe, 4, 0);
2886  status += MXL_SetGPIO(fe, 3, 1);
2887  status += MXL_SetGPIO(fe, 1, 1);
2888  }
2889  if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2890  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2891  status += MXL_SetGPIO(fe, 4, 1);
2892  status += MXL_SetGPIO(fe, 3, 0);
2893  status += MXL_SetGPIO(fe, 1, 1);
2894  }
2895  if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2896  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2897  status += MXL_SetGPIO(fe, 4, 1);
2898  status += MXL_SetGPIO(fe, 3, 0);
2899  status += MXL_SetGPIO(fe, 1, 0);
2900  }
2901  if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2902  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2903  status += MXL_SetGPIO(fe, 4, 1);
2904  status += MXL_SetGPIO(fe, 3, 1);
2905  status += MXL_SetGPIO(fe, 1, 0);
2906  }
2907  if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2908  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2909  status += MXL_SetGPIO(fe, 4, 1);
2910  status += MXL_SetGPIO(fe, 3, 1);
2911  status += MXL_SetGPIO(fe, 1, 0);
2912  }
2913  if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2914  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2915  status += MXL_SetGPIO(fe, 4, 1);
2916  status += MXL_SetGPIO(fe, 3, 1);
2917  status += MXL_SetGPIO(fe, 1, 0);
2918  }
2919  if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2920  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2921  status += MXL_SetGPIO(fe, 4, 1);
2922  status += MXL_SetGPIO(fe, 3, 1);
2923  status += MXL_SetGPIO(fe, 1, 1);
2924  }
2925  if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2926  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2927  status += MXL_SetGPIO(fe, 4, 1);
2928  status += MXL_SetGPIO(fe, 3, 1);
2929  status += MXL_SetGPIO(fe, 1, 1);
2930  }
2931  if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2932  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2933  status += MXL_SetGPIO(fe, 4, 1);
2934  status += MXL_SetGPIO(fe, 3, 1);
2935  status += MXL_SetGPIO(fe, 1, 1);
2936  }
2937  }
2938 
2939  if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
2940 
2941  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2942 
2943  if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
2944  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2945  status += MXL_SetGPIO(fe, 4, 0);
2946  status += MXL_SetGPIO(fe, 1, 1);
2947  status += MXL_SetGPIO(fe, 3, 1);
2948  }
2949  if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
2950  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2951  status += MXL_SetGPIO(fe, 4, 0);
2952  status += MXL_SetGPIO(fe, 1, 0);
2953  status += MXL_SetGPIO(fe, 3, 1);
2954  }
2955  if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
2956  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2957  status += MXL_SetGPIO(fe, 4, 1);
2958  status += MXL_SetGPIO(fe, 1, 0);
2959  status += MXL_SetGPIO(fe, 3, 1);
2960  }
2961  if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
2962  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2963  status += MXL_SetGPIO(fe, 4, 1);
2964  status += MXL_SetGPIO(fe, 1, 0);
2965  status += MXL_SetGPIO(fe, 3, 0);
2966  }
2967  if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
2968  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2969  status += MXL_SetGPIO(fe, 4, 1);
2970  status += MXL_SetGPIO(fe, 1, 1);
2971  status += MXL_SetGPIO(fe, 3, 0);
2972  }
2973  if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
2974  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2975  status += MXL_SetGPIO(fe, 4, 1);
2976  status += MXL_SetGPIO(fe, 1, 1);
2977  status += MXL_SetGPIO(fe, 3, 0);
2978  }
2979  if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
2980  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2981  status += MXL_SetGPIO(fe, 4, 1);
2982  status += MXL_SetGPIO(fe, 1, 1);
2983  status += MXL_SetGPIO(fe, 3, 1);
2984  }
2985  }
2986 
2987  if (state->TF_Type == MXL_TF_D_L) {
2988 
2989  /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */
2990  status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2991 
2992  /* if UHF and terrestrial => Turn off Tracking Filter */
2993  if (state->RF_IN >= 471000000 &&
2994  (state->RF_IN - 471000000)%6000000 != 0) {
2995  /* Turn off all the banks */
2996  status += MXL_SetGPIO(fe, 3, 1);
2997  status += MXL_SetGPIO(fe, 1, 1);
2998  status += MXL_SetGPIO(fe, 4, 1);
2999  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3000  status += MXL_ControlWrite(fe, AGC_IF, 10);
3001  } else {
3002  /* if VHF or cable => Turn on Tracking Filter */
3003  if (state->RF_IN >= 43000000 &&
3004  state->RF_IN < 140000000) {
3005 
3006  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3007  status += MXL_SetGPIO(fe, 4, 1);
3008  status += MXL_SetGPIO(fe, 1, 1);
3009  status += MXL_SetGPIO(fe, 3, 0);
3010  }
3011  if (state->RF_IN >= 140000000 &&
3012  state->RF_IN < 240000000) {
3013  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3014  status += MXL_SetGPIO(fe, 4, 1);
3015  status += MXL_SetGPIO(fe, 1, 0);
3016  status += MXL_SetGPIO(fe, 3, 0);
3017  }
3018  if (state->RF_IN >= 240000000 &&
3019  state->RF_IN < 340000000) {
3020  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3021  status += MXL_SetGPIO(fe, 4, 0);
3022  status += MXL_SetGPIO(fe, 1, 1);
3023  status += MXL_SetGPIO(fe, 3, 0);
3024  }
3025  if (state->RF_IN >= 340000000 &&
3026  state->RF_IN < 430000000) {
3027  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3028  status += MXL_SetGPIO(fe, 4, 0);
3029  status += MXL_SetGPIO(fe, 1, 0);
3030  status += MXL_SetGPIO(fe, 3, 1);
3031  }
3032  if (state->RF_IN >= 430000000 &&
3033  state->RF_IN < 470000000) {
3034  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3035  status += MXL_SetGPIO(fe, 4, 1);
3036  status += MXL_SetGPIO(fe, 1, 0);
3037  status += MXL_SetGPIO(fe, 3, 1);
3038  }
3039  if (state->RF_IN >= 470000000 &&
3040  state->RF_IN < 570000000) {
3041  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3042  status += MXL_SetGPIO(fe, 4, 0);
3043  status += MXL_SetGPIO(fe, 1, 0);
3044  status += MXL_SetGPIO(fe, 3, 1);
3045  }
3046  if (state->RF_IN >= 570000000 &&
3047  state->RF_IN < 620000000) {
3048  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3049  status += MXL_SetGPIO(fe, 4, 0);
3050  status += MXL_SetGPIO(fe, 1, 1);
3051  status += MXL_SetGPIO(fe, 3, 1);
3052  }
3053  if (state->RF_IN >= 620000000 &&
3054  state->RF_IN < 760000000) {
3055  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3056  status += MXL_SetGPIO(fe, 4, 0);
3057  status += MXL_SetGPIO(fe, 1, 1);
3058  status += MXL_SetGPIO(fe, 3, 1);
3059  }
3060  if (state->RF_IN >= 760000000 &&
3061  state->RF_IN <= 900000000) {
3062  status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3063  status += MXL_SetGPIO(fe, 4, 1);
3064  status += MXL_SetGPIO(fe, 1, 1);
3065  status += MXL_SetGPIO(fe, 3, 1);
3066  }
3067  }
3068  }
3069 
3070  if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
3071 
3072  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3073 
3074  if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3075  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3076  status += MXL_SetGPIO(fe, 4, 0);
3077  status += MXL_SetGPIO(fe, 1, 1);
3078  status += MXL_SetGPIO(fe, 3, 1);
3079  }
3080  if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3081  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3082  status += MXL_SetGPIO(fe, 4, 0);
3083  status += MXL_SetGPIO(fe, 1, 0);
3084  status += MXL_SetGPIO(fe, 3, 1);
3085  }
3086  if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3087  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3088  status += MXL_SetGPIO(fe, 4, 1);
3089  status += MXL_SetGPIO(fe, 1, 0);
3090  status += MXL_SetGPIO(fe, 3, 1);
3091  }
3092  if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3093  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3094  status += MXL_SetGPIO(fe, 4, 1);
3095  status += MXL_SetGPIO(fe, 1, 0);
3096  status += MXL_SetGPIO(fe, 3, 0);
3097  }
3098  if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3099  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3100  status += MXL_SetGPIO(fe, 4, 1);
3101  status += MXL_SetGPIO(fe, 1, 1);
3102  status += MXL_SetGPIO(fe, 3, 0);
3103  }
3104  if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3105  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3106  status += MXL_SetGPIO(fe, 4, 1);
3107  status += MXL_SetGPIO(fe, 1, 1);
3108  status += MXL_SetGPIO(fe, 3, 0);
3109  }
3110  if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3111  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3112  status += MXL_SetGPIO(fe, 4, 1);
3113  status += MXL_SetGPIO(fe, 1, 1);
3114  status += MXL_SetGPIO(fe, 3, 1);
3115  }
3116  }
3117 
3118  if (state->TF_Type == MXL_TF_F) {
3119 
3120  /* Tracking Filter type F */
3121  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3122 
3123  if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
3124  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3125  status += MXL_SetGPIO(fe, 4, 0);
3126  status += MXL_SetGPIO(fe, 1, 1);
3127  status += MXL_SetGPIO(fe, 3, 1);
3128  }
3129  if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
3130  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3131  status += MXL_SetGPIO(fe, 4, 0);
3132  status += MXL_SetGPIO(fe, 1, 0);
3133  status += MXL_SetGPIO(fe, 3, 1);
3134  }
3135  if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
3136  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3137  status += MXL_SetGPIO(fe, 4, 1);
3138  status += MXL_SetGPIO(fe, 1, 0);
3139  status += MXL_SetGPIO(fe, 3, 1);
3140  }
3141  if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
3142  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3143  status += MXL_SetGPIO(fe, 4, 1);
3144  status += MXL_SetGPIO(fe, 1, 0);
3145  status += MXL_SetGPIO(fe, 3, 0);
3146  }
3147  if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
3148  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3149  status += MXL_SetGPIO(fe, 4, 1);
3150  status += MXL_SetGPIO(fe, 1, 1);
3151  status += MXL_SetGPIO(fe, 3, 0);
3152  }
3153  if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
3154  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3155  status += MXL_SetGPIO(fe, 4, 1);
3156  status += MXL_SetGPIO(fe, 1, 1);
3157  status += MXL_SetGPIO(fe, 3, 0);
3158  }
3159  if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
3160  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3161  status += MXL_SetGPIO(fe, 4, 1);
3162  status += MXL_SetGPIO(fe, 1, 1);
3163  status += MXL_SetGPIO(fe, 3, 1);
3164  }
3165  }
3166 
3167  if (state->TF_Type == MXL_TF_E_2) {
3168 
3169  /* Tracking Filter type E_2 */
3170  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3171 
3172  if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3173  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3174  status += MXL_SetGPIO(fe, 4, 0);
3175  status += MXL_SetGPIO(fe, 1, 1);
3176  status += MXL_SetGPIO(fe, 3, 1);
3177  }
3178  if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3179  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3180  status += MXL_SetGPIO(fe, 4, 0);
3181  status += MXL_SetGPIO(fe, 1, 0);
3182  status += MXL_SetGPIO(fe, 3, 1);
3183  }
3184  if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3185  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3186  status += MXL_SetGPIO(fe, 4, 1);
3187  status += MXL_SetGPIO(fe, 1, 0);
3188  status += MXL_SetGPIO(fe, 3, 1);
3189  }
3190  if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3191  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3192  status += MXL_SetGPIO(fe, 4, 1);
3193  status += MXL_SetGPIO(fe, 1, 0);
3194  status += MXL_SetGPIO(fe, 3, 0);
3195  }
3196  if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3197  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3198  status += MXL_SetGPIO(fe, 4, 1);
3199  status += MXL_SetGPIO(fe, 1, 1);
3200  status += MXL_SetGPIO(fe, 3, 0);
3201  }
3202  if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3203  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3204  status += MXL_SetGPIO(fe, 4, 1);
3205  status += MXL_SetGPIO(fe, 1, 1);
3206  status += MXL_SetGPIO(fe, 3, 0);
3207  }
3208  if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3209  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3210  status += MXL_SetGPIO(fe, 4, 1);
3211  status += MXL_SetGPIO(fe, 1, 1);
3212  status += MXL_SetGPIO(fe, 3, 1);
3213  }
3214  }
3215 
3216  if (state->TF_Type == MXL_TF_G) {
3217 
3218  /* Tracking Filter type G add for v2.6.8 */
3219  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3220 
3221  if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
3222 
3223  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3224  status += MXL_SetGPIO(fe, 4, 0);
3225  status += MXL_SetGPIO(fe, 1, 1);
3226  status += MXL_SetGPIO(fe, 3, 1);
3227  }
3228  if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
3229  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3230  status += MXL_SetGPIO(fe, 4, 0);
3231  status += MXL_SetGPIO(fe, 1, 0);
3232  status += MXL_SetGPIO(fe, 3, 1);
3233  }
3234  if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
3235  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3236  status += MXL_SetGPIO(fe, 4, 1);
3237  status += MXL_SetGPIO(fe, 1, 0);
3238  status += MXL_SetGPIO(fe, 3, 1);
3239  }
3240  if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3241  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3242  status += MXL_SetGPIO(fe, 4, 1);
3243  status += MXL_SetGPIO(fe, 1, 0);
3244  status += MXL_SetGPIO(fe, 3, 0);
3245  }
3246  if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
3247  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3248  status += MXL_SetGPIO(fe, 4, 1);
3249  status += MXL_SetGPIO(fe, 1, 0);
3250  status += MXL_SetGPIO(fe, 3, 1);
3251  }
3252  if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3253  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3254  status += MXL_SetGPIO(fe, 4, 1);
3255  status += MXL_SetGPIO(fe, 1, 1);
3256  status += MXL_SetGPIO(fe, 3, 0);
3257  }
3258  if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
3259  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3260  status += MXL_SetGPIO(fe, 4, 1);
3261  status += MXL_SetGPIO(fe, 1, 1);
3262  status += MXL_SetGPIO(fe, 3, 0);
3263  }
3264  if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
3265  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3266  status += MXL_SetGPIO(fe, 4, 1);
3267  status += MXL_SetGPIO(fe, 1, 1);
3268  status += MXL_SetGPIO(fe, 3, 1);
3269  }
3270  }
3271 
3272  if (state->TF_Type == MXL_TF_E_NA) {
3273 
3274  /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */
3275  status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3276 
3277  /* if UHF and terrestrial=> Turn off Tracking Filter */
3278  if (state->RF_IN >= 471000000 &&
3279  (state->RF_IN - 471000000)%6000000 != 0) {
3280 
3281  /* Turn off all the banks */
3282  status += MXL_SetGPIO(fe, 3, 1);
3283  status += MXL_SetGPIO(fe, 1, 1);
3284  status += MXL_SetGPIO(fe, 4, 1);
3285  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3286 
3287  /* 2.6.12 Turn on RSSI */
3288  status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
3289  status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
3290  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
3291  status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
3292 
3293  /* RSSI reference point */
3294  status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
3295  status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
3296  status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
3297 
3298  /* following parameter is from analog OTA mode,
3299  * can be change to seek better performance */
3300  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
3301  } else {
3302  /* if VHF or Cable => Turn on Tracking Filter */
3303 
3304  /* 2.6.12 Turn off RSSI */
3305  status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
3306 
3307  /* change back from above condition */
3308  status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
3309 
3310 
3311  if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3312 
3313  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3314  status += MXL_SetGPIO(fe, 4, 0);
3315  status += MXL_SetGPIO(fe, 1, 1);
3316  status += MXL_SetGPIO(fe, 3, 1);
3317  }
3318  if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3319  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3320  status += MXL_SetGPIO(fe, 4, 0);
3321  status += MXL_SetGPIO(fe, 1, 0);
3322  status += MXL_SetGPIO(fe, 3, 1);
3323  }
3324  if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3325  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3326  status += MXL_SetGPIO(fe, 4, 1);
3327  status += MXL_SetGPIO(fe, 1, 0);
3328  status += MXL_SetGPIO(fe, 3, 1);
3329  }
3330  if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3331  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3332  status += MXL_SetGPIO(fe, 4, 1);
3333  status += MXL_SetGPIO(fe, 1, 0);
3334  status += MXL_SetGPIO(fe, 3, 0);
3335  }
3336  if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3337  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3338  status += MXL_SetGPIO(fe, 4, 1);
3339  status += MXL_SetGPIO(fe, 1, 1);
3340  status += MXL_SetGPIO(fe, 3, 0);
3341  }
3342  if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3343  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3344  status += MXL_SetGPIO(fe, 4, 1);
3345  status += MXL_SetGPIO(fe, 1, 1);
3346  status += MXL_SetGPIO(fe, 3, 0);
3347  }
3348  if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3349  status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3350  status += MXL_SetGPIO(fe, 4, 1);
3351  status += MXL_SetGPIO(fe, 1, 1);
3352  status += MXL_SetGPIO(fe, 3, 1);
3353  }
3354  }
3355  }
3356  return status ;
3357 }
3358 
3359 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3360 {
3361  u16 status = 0;
3362 
3363  if (GPIO_Num == 1)
3364  status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3365 
3366  /* GPIO2 is not available */
3367 
3368  if (GPIO_Num == 3) {
3369  if (GPIO_Val == 1) {
3370  status += MXL_ControlWrite(fe, GPIO_3, 0);
3371  status += MXL_ControlWrite(fe, GPIO_3B, 0);
3372  }
3373  if (GPIO_Val == 0) {
3374  status += MXL_ControlWrite(fe, GPIO_3, 1);
3375  status += MXL_ControlWrite(fe, GPIO_3B, 1);
3376  }
3377  if (GPIO_Val == 3) { /* tri-state */
3378  status += MXL_ControlWrite(fe, GPIO_3, 0);
3379  status += MXL_ControlWrite(fe, GPIO_3B, 1);
3380  }
3381  }
3382  if (GPIO_Num == 4) {
3383  if (GPIO_Val == 1) {
3384  status += MXL_ControlWrite(fe, GPIO_4, 0);
3385  status += MXL_ControlWrite(fe, GPIO_4B, 0);
3386  }
3387  if (GPIO_Val == 0) {
3388  status += MXL_ControlWrite(fe, GPIO_4, 1);
3389  status += MXL_ControlWrite(fe, GPIO_4B, 1);
3390  }
3391  if (GPIO_Val == 3) { /* tri-state */
3392  status += MXL_ControlWrite(fe, GPIO_4, 0);
3393  status += MXL_ControlWrite(fe, GPIO_4B, 1);
3394  }
3395  }
3396 
3397  return status;
3398 }
3399 
3400 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3401 {
3402  u16 status = 0;
3403 
3404  /* Will write ALL Matching Control Name */
3405  /* Write Matching INIT Control */
3406  status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
3407  /* Write Matching CH Control */
3408  status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
3409 #ifdef _MXL_INTERNAL
3410  /* Write Matching MXL Control */
3411  status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
3412 #endif
3413  return status;
3414 }
3415 
3416 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
3417  u32 value, u16 controlGroup)
3418 {
3419  struct mxl5005s_state *state = fe->tuner_priv;
3420  u16 i, j, k;
3421  u32 highLimit;
3422  u32 ctrlVal;
3423 
3424  if (controlGroup == 1) /* Initial Control */ {
3425 
3426  for (i = 0; i < state->Init_Ctrl_Num; i++) {
3427 
3428  if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3429 
3430  highLimit = 1 << state->Init_Ctrl[i].size;
3431  if (value < highLimit) {
3432  for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3433  state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3434  MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3435  (u8)(state->Init_Ctrl[i].bit[j]),
3436  (u8)((value>>j) & 0x01));
3437  }
3438  ctrlVal = 0;
3439  for (k = 0; k < state->Init_Ctrl[i].size; k++)
3440  ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3441  } else
3442  return -1;
3443  }
3444  }
3445  }
3446  if (controlGroup == 2) /* Chan change Control */ {
3447 
3448  for (i = 0; i < state->CH_Ctrl_Num; i++) {
3449 
3450  if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3451 
3452  highLimit = 1 << state->CH_Ctrl[i].size;
3453  if (value < highLimit) {
3454  for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3455  state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3456  MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3457  (u8)(state->CH_Ctrl[i].bit[j]),
3458  (u8)((value>>j) & 0x01));
3459  }
3460  ctrlVal = 0;
3461  for (k = 0; k < state->CH_Ctrl[i].size; k++)
3462  ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3463  } else
3464  return -1;
3465  }
3466  }
3467  }
3468 #ifdef _MXL_INTERNAL
3469  if (controlGroup == 3) /* Maxlinear Control */ {
3470 
3471  for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3472 
3473  if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3474 
3475  highLimit = (1 << state->MXL_Ctrl[i].size);
3476  if (value < highLimit) {
3477  for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3478  state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3479  MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3480  (u8)(state->MXL_Ctrl[i].bit[j]),
3481  (u8)((value>>j) & 0x01));
3482  }
3483  ctrlVal = 0;
3484  for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3485  ctrlVal += state->
3486  MXL_Ctrl[i].val[k] *
3487  (1 << k);
3488  } else
3489  return -1;
3490  }
3491  }
3492  }
3493 #endif
3494  return 0 ; /* successful return */
3495 }
3496 
3497 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3498 {
3499  struct mxl5005s_state *state = fe->tuner_priv;
3500  int i ;
3501 
3502  for (i = 0; i < 104; i++) {
3503  if (RegNum == state->TunerRegs[i].Reg_Num) {
3504  *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3505  return 0;
3506  }
3507  }
3508 
3509  return 1;
3510 }
3511 
3512 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3513 {
3514  struct mxl5005s_state *state = fe->tuner_priv;
3515  u32 ctrlVal ;
3516  u16 i, k ;
3517 
3518  for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3519 
3520  if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3521 
3522  ctrlVal = 0;
3523  for (k = 0; k < state->Init_Ctrl[i].size; k++)
3524  ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
3525  *value = ctrlVal;
3526  return 0;
3527  }
3528  }
3529 
3530  for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3531 
3532  if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3533 
3534  ctrlVal = 0;
3535  for (k = 0; k < state->CH_Ctrl[i].size; k++)
3536  ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3537  *value = ctrlVal;
3538  return 0;
3539 
3540  }
3541  }
3542 
3543 #ifdef _MXL_INTERNAL
3544  for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3545 
3546  if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3547 
3548  ctrlVal = 0;
3549  for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3550  ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
3551  *value = ctrlVal;
3552  return 0;
3553 
3554  }
3555  }
3556 #endif
3557  return 1;
3558 }
3559 
3560 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
3561  u8 bitVal)
3562 {
3563  struct mxl5005s_state *state = fe->tuner_priv;
3564  int i ;
3565 
3566  const u8 AND_MAP[8] = {
3567  0xFE, 0xFD, 0xFB, 0xF7,
3568  0xEF, 0xDF, 0xBF, 0x7F } ;
3569 
3570  const u8 OR_MAP[8] = {
3571  0x01, 0x02, 0x04, 0x08,
3572  0x10, 0x20, 0x40, 0x80 } ;
3573 
3574  for (i = 0; i < state->TunerRegs_Num; i++) {
3575  if (state->TunerRegs[i].Reg_Num == address) {
3576  if (bitVal)
3577  state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
3578  else
3579  state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
3580  break ;
3581  }
3582  }
3583 }
3584 
3585 static u32 MXL_Ceiling(u32 value, u32 resolution)
3586 {
3587  return value / resolution + (value % resolution > 0 ? 1 : 0);
3588 }
3589 
3590 /* Retrieve the Initialzation Registers */
3591 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
3592  u8 *RegVal, int *count)
3593 {
3594  u16 status = 0;
3595  int i ;
3596 
3597  u8 RegAddr[] = {
3598  11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
3599  76, 77, 91, 134, 135, 137, 147,
3600  156, 166, 167, 168, 25 };
3601 
3602  *count = ARRAY_SIZE(RegAddr);
3603 
3604  status += MXL_BlockInit(fe);
3605 
3606  for (i = 0 ; i < *count; i++) {
3607  RegNum[i] = RegAddr[i];
3608  status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3609  }
3610 
3611  return status;
3612 }
3613 
3614 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3615  int *count)
3616 {
3617  u16 status = 0;
3618  int i ;
3619 
3620 /* add 77, 166, 167, 168 register for 2.6.12 */
3621 #ifdef _MXL_PRODUCTION
3622  u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
3623  107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3624 #else
3625  u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
3626  107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3627  /*
3628  u8 RegAddr[171];
3629  for (i = 0; i <= 170; i++)
3630  RegAddr[i] = i;
3631  */
3632 #endif
3633 
3634  *count = ARRAY_SIZE(RegAddr);
3635 
3636  for (i = 0 ; i < *count; i++) {
3637  RegNum[i] = RegAddr[i];
3638  status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3639  }
3640 
3641  return status;
3642 }
3643 
3644 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
3645  u8 *RegVal, int *count)
3646 {
3647  u16 status = 0;
3648  int i;
3649 
3650  u8 RegAddr[] = {43, 136};
3651 
3652  *count = ARRAY_SIZE(RegAddr);
3653 
3654  for (i = 0; i < *count; i++) {
3655  RegNum[i] = RegAddr[i];
3656  status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3657  }
3658 
3659  return status;
3660 }
3661 
3662 static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
3663 {
3664  if (state == 1) /* Load_Start */
3665  *MasterReg = 0xF3;
3666  if (state == 2) /* Power_Down */
3667  *MasterReg = 0x41;
3668  if (state == 3) /* Synth_Reset */
3669  *MasterReg = 0xB1;
3670  if (state == 4) /* Seq_Off */
3671  *MasterReg = 0xF1;
3672 
3673  return 0;
3674 }
3675 
3676 #ifdef _MXL_PRODUCTION
3677 static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
3678 {
3679  struct mxl5005s_state *state = fe->tuner_priv;
3680  u16 status = 0 ;
3681 
3682  if (VCO_Range == 1) {
3683  status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3684  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3685  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3686  status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3687  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3688  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3689  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3690  if (state->Mode == 0 && state->IF_Mode == 1) {
3691  /* Analog Low IF Mode */
3692  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3693  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3694  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3695  status += MXL_ControlWrite(fe,
3696  CHCAL_FRAC_MOD_RF, 180224);
3697  }
3698  if (state->Mode == 0 && state->IF_Mode == 0) {
3699  /* Analog Zero IF Mode */
3700  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3701  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3702  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3703  status += MXL_ControlWrite(fe,
3704  CHCAL_FRAC_MOD_RF, 222822);
3705  }
3706  if (state->Mode == 1) /* Digital Mode */ {
3707  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3708  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3709  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3710  status += MXL_ControlWrite(fe,
3711  CHCAL_FRAC_MOD_RF, 229376);
3712  }
3713  }
3714 
3715  if (VCO_Range == 2) {
3716  status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3717  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3718  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3719  status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3720  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3721  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3722  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3723  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3724  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3725  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3726  if (state->Mode == 0 && state->IF_Mode == 1) {
3727  /* Analog Low IF Mode */
3728  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3729  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3730  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3731  status += MXL_ControlWrite(fe,
3732  CHCAL_FRAC_MOD_RF, 206438);
3733  }
3734  if (state->Mode == 0 && state->IF_Mode == 0) {
3735  /* Analog Zero IF Mode */
3736  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3737  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3738  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3739  status += MXL_ControlWrite(fe,
3740  CHCAL_FRAC_MOD_RF, 206438);
3741  }
3742  if (state->Mode == 1) /* Digital Mode */ {
3743  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3744  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3745  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3746  status += MXL_ControlWrite(fe,
3747  CHCAL_FRAC_MOD_RF, 16384);
3748  }
3749  }
3750 
3751  if (VCO_Range == 3) {
3752  status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3753  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3754  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3755  status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3756  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3757  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3758  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3759  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3760  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3761  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3762  if (state->Mode == 0 && state->IF_Mode == 1) {
3763  /* Analog Low IF Mode */
3764  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3765  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3766  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3767  status += MXL_ControlWrite(fe,
3768  CHCAL_FRAC_MOD_RF, 173670);
3769  }
3770  if (state->Mode == 0 && state->IF_Mode == 0) {
3771  /* Analog Zero IF Mode */
3772  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3773  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3774  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3775  status += MXL_ControlWrite(fe,
3776  CHCAL_FRAC_MOD_RF, 173670);
3777  }
3778  if (state->Mode == 1) /* Digital Mode */ {
3779  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3780  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3781  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3782  status += MXL_ControlWrite(fe,
3783  CHCAL_FRAC_MOD_RF, 245760);
3784  }
3785  }
3786 
3787  if (VCO_Range == 4) {
3788  status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3789  status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3790  status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3791  status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3792  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3793  status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3794  status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3795  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3796  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3797  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3798  if (state->Mode == 0 && state->IF_Mode == 1) {
3799  /* Analog Low IF Mode */
3800  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3801  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3802  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3803  status += MXL_ControlWrite(fe,
3804  CHCAL_FRAC_MOD_RF, 206438);
3805  }
3806  if (state->Mode == 0 && state->IF_Mode == 0) {
3807  /* Analog Zero IF Mode */
3808  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3809  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3810  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3811  status += MXL_ControlWrite(fe,
3812  CHCAL_FRAC_MOD_RF, 206438);
3813  }
3814  if (state->Mode == 1) /* Digital Mode */ {
3815  status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3816  status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3817  status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3818  status += MXL_ControlWrite(fe,
3819  CHCAL_FRAC_MOD_RF, 212992);
3820  }
3821  }
3822 
3823  return status;
3824 }
3825 
3826 static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
3827 {
3828  struct mxl5005s_state *state = fe->tuner_priv;
3829  u16 status = 0;
3830 
3831  if (Hystersis == 1)
3832  status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
3833 
3834  return status;
3835 }
3836 #endif
3837 /* End: Reference driver code found in the Realtek driver that
3838  * is copyright MaxLinear */
3839 
3840 /* ----------------------------------------------------------------
3841  * Begin: Everything after here is new code to adapt the
3842  * proprietary Realtek driver into a Linux API tuner.
3843  * Copyright (C) 2008 Steven Toth <[email protected]>
3844  */
3845 static int mxl5005s_reset(struct dvb_frontend *fe)
3846 {
3847  struct mxl5005s_state *state = fe->tuner_priv;
3848  int ret = 0;
3849 
3850  u8 buf[2] = { 0xff, 0x00 };
3851  struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3852  .buf = buf, .len = 2 };
3853 
3854  dprintk(2, "%s()\n", __func__);
3855 
3856  if (fe->ops.i2c_gate_ctrl)
3857  fe->ops.i2c_gate_ctrl(fe, 1);
3858 
3859  if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3860  printk(KERN_WARNING "mxl5005s I2C reset failed\n");
3861  ret = -EREMOTEIO;
3862  }
3863 
3864  if (fe->ops.i2c_gate_ctrl)
3865  fe->ops.i2c_gate_ctrl(fe, 0);
3866 
3867  return ret;
3868 }
3869 
3870 /* Write a single byte to a single reg, latch the value if required by
3871  * following the transaction with the latch byte.
3872  */
3873 static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
3874 {
3875  struct mxl5005s_state *state = fe->tuner_priv;
3876  u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
3877  struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3878  .buf = buf, .len = 3 };
3879 
3880  if (latch == 0)
3881  msg.len = 2;
3882 
3883  dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr);
3884 
3885  if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3886  printk(KERN_WARNING "mxl5005s I2C write failed\n");
3887  return -EREMOTEIO;
3888  }
3889  return 0;
3890 }
3891 
3892 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
3893  u8 *datatable, u8 len)
3894 {
3895  int ret = 0, i;
3896 
3897  if (fe->ops.i2c_gate_ctrl)
3898  fe->ops.i2c_gate_ctrl(fe, 1);
3899 
3900  for (i = 0 ; i < len-1; i++) {
3901  ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
3902  if (ret < 0)
3903  break;
3904  }
3905 
3906  ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
3907 
3908  if (fe->ops.i2c_gate_ctrl)
3909  fe->ops.i2c_gate_ctrl(fe, 0);
3910 
3911  return ret;
3912 }
3913 
3914 static int mxl5005s_init(struct dvb_frontend *fe)
3915 {
3916  struct mxl5005s_state *state = fe->tuner_priv;
3917 
3918  dprintk(1, "%s()\n", __func__);
3919  state->current_mode = MXL_QAM;
3920  return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
3921 }
3922 
3923 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
3924  u32 bandwidth)
3925 {
3926  struct mxl5005s_state *state = fe->tuner_priv;
3927 
3928  u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
3929  u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
3930  int TableLen;
3931 
3932  dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
3933 
3934  mxl5005s_reset(fe);
3935 
3936  /* Tuner initialization stage 0 */
3937  MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
3938  AddrTable[0] = MASTER_CONTROL_ADDR;
3939  ByteTable[0] |= state->config->AgcMasterByte;
3940 
3941  mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
3942 
3943  mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
3944 
3945  /* Tuner initialization stage 1 */
3946  MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
3947 
3948  mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
3949 
3950  return 0;
3951 }
3952 
3953 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
3954  u32 bandwidth)
3955 {
3956  struct mxl5005s_state *state = fe->tuner_priv;
3957  struct mxl5005s_config *c = state->config;
3958 
3959  InitTunerControls(fe);
3960 
3961  /* Set MxL5005S parameters. */
3962  MXL5005_TunerConfig(
3963  fe,
3964  c->mod_mode,
3965  c->if_mode,
3966  bandwidth,
3967  c->if_freq,
3968  c->xtal_freq,
3969  c->agc_mode,
3970  c->top,
3971  c->output_load,
3972  c->clock_out,
3973  c->div_out,
3974  c->cap_select,
3975  c->rssi_enable,
3976  mod_type,
3977  c->tracking_filter);
3978 
3979  return 0;
3980 }
3981 
3982 static int mxl5005s_set_params(struct dvb_frontend *fe)
3983 {
3984  struct mxl5005s_state *state = fe->tuner_priv;
3985  struct dtv_frontend_properties *c = &fe->dtv_property_cache;
3986  u32 delsys = c->delivery_system;
3987  u32 bw = c->bandwidth_hz;
3988  u32 req_mode, req_bw = 0;
3989  int ret;
3990 
3991  dprintk(1, "%s()\n", __func__);
3992 
3993  switch (delsys) {
3994  case SYS_ATSC:
3995  req_mode = MXL_ATSC;
3996  req_bw = MXL5005S_BANDWIDTH_6MHZ;
3997  break;
3998  case SYS_DVBC_ANNEX_B:
3999  req_mode = MXL_QAM;
4000  req_bw = MXL5005S_BANDWIDTH_6MHZ;
4001  break;
4002  default: /* Assume DVB-T */
4003  req_mode = MXL_DVBT;
4004  switch (bw) {
4005  case 6000000:
4006  req_bw = MXL5005S_BANDWIDTH_6MHZ;
4007  break;
4008  case 7000000:
4009  req_bw = MXL5005S_BANDWIDTH_7MHZ;
4010  break;
4011  case 8000000:
4012  case 0:
4013  req_bw = MXL5005S_BANDWIDTH_8MHZ;
4014  break;
4015  default:
4016  return -EINVAL;
4017  }
4018  }
4019 
4020  /* Change tuner for new modulation type if reqd */
4021  if (req_mode != state->current_mode ||
4022  req_bw != state->Chan_Bandwidth) {
4023  state->current_mode = req_mode;
4024  ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4025 
4026  } else
4027  ret = 0;
4028 
4029  if (ret == 0) {
4030  dprintk(1, "%s() freq=%d\n", __func__, c->frequency);
4031  ret = mxl5005s_SetRfFreqHz(fe, c->frequency);
4032  }
4033 
4034  return ret;
4035 }
4036 
4037 static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4038 {
4039  struct mxl5005s_state *state = fe->tuner_priv;
4040  dprintk(1, "%s()\n", __func__);
4041 
4042  *frequency = state->RF_IN;
4043 
4044  return 0;
4045 }
4046 
4047 static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4048 {
4049  struct mxl5005s_state *state = fe->tuner_priv;
4050  dprintk(1, "%s()\n", __func__);
4051 
4052  *bandwidth = state->Chan_Bandwidth;
4053 
4054  return 0;
4055 }
4056 
4057 static int mxl5005s_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
4058 {
4059  struct mxl5005s_state *state = fe->tuner_priv;
4060  dprintk(1, "%s()\n", __func__);
4061 
4062  *frequency = state->IF_OUT;
4063 
4064  return 0;
4065 }
4066 
4067 static int mxl5005s_release(struct dvb_frontend *fe)
4068 {
4069  dprintk(1, "%s()\n", __func__);
4070  kfree(fe->tuner_priv);
4071  fe->tuner_priv = NULL;
4072  return 0;
4073 }
4074 
4075 static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4076  .info = {
4077  .name = "MaxLinear MXL5005S",
4078  .frequency_min = 48000000,
4079  .frequency_max = 860000000,
4080  .frequency_step = 50000,
4081  },
4082 
4083  .release = mxl5005s_release,
4084  .init = mxl5005s_init,
4085 
4086  .set_params = mxl5005s_set_params,
4087  .get_frequency = mxl5005s_get_frequency,
4088  .get_bandwidth = mxl5005s_get_bandwidth,
4089  .get_if_frequency = mxl5005s_get_if_frequency,
4090 };
4091 
4092 struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4093  struct i2c_adapter *i2c,
4094  struct mxl5005s_config *config)
4095 {
4096  struct mxl5005s_state *state = NULL;
4097  dprintk(1, "%s()\n", __func__);
4098 
4099  state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4100  if (state == NULL)
4101  return NULL;
4102 
4103  state->frontend = fe;
4104  state->config = config;
4105  state->i2c = i2c;
4106 
4107  printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n",
4108  config->i2c_address);
4109 
4110  memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
4111  sizeof(struct dvb_tuner_ops));
4112 
4113  fe->tuner_priv = state;
4114  return fe;
4115 }
4116 EXPORT_SYMBOL(mxl5005s_attach);
4117 
4118 MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
4119 MODULE_AUTHOR("Steven Toth");
4120 MODULE_LICENSE("GPL");
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