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hw.h
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1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2012 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <[email protected]>
24  e1000-devel Mailing List <[email protected]>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_HW_H_
30 #define _E1000_HW_H_
31 
32 #include <linux/types.h>
33 
34 struct e1000_hw;
35 struct e1000_adapter;
36 
37 #include "defines.h"
38 
39 enum e1e_registers {
40  E1000_CTRL = 0x00000, /* Device Control - RW */
41  E1000_STATUS = 0x00008, /* Device Status - RO */
42  E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
43  E1000_EERD = 0x00014, /* EEPROM Read - RW */
44  E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
45  E1000_FLA = 0x0001C, /* Flash Access - RW */
46  E1000_MDIC = 0x00020, /* MDI Control - RW */
47  E1000_SCTL = 0x00024, /* SerDes Control - RW */
48  E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
49  E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
50  E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
51  E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
52  E1000_FCT = 0x00030, /* Flow Control Type - RW */
53  E1000_VET = 0x00038, /* VLAN Ether Type - RW */
54  E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
55  E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
56  E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
57  E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
58  E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
59  E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
60  E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
61  E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
62  E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
63  E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
64 #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
65  E1000_RCTL = 0x00100, /* Rx Control - RW */
66  E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
67  E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
68  E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
69  E1000_TCTL = 0x00400, /* Tx Control - RW */
70  E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
71  E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
72  E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
73  E1000_LEDCTL = 0x00E00, /* LED Control - RW */
74  E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
75  E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
76  E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
77 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
78  E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
79  E1000_PBS = 0x01008, /* Packet Buffer Size */
80  E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
81  E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
82  E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
83  E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
84  E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
85  E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
86  E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
87  E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
88 /*
89  * Convenience macros
90  *
91  * Note: "_n" is the queue number of the register to be written to.
92  *
93  * Example usage:
94  * E1000_RDBAL(current_rx_queue)
95  */
96  E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
97 #define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
98  E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
99 #define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
100  E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
101 #define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
102  E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
103 #define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
104  E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
105 #define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
106  E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
107  E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
108 #define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
109  E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
110 
111  E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
112  E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
113 #define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
114  E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
115 #define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
116  E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
117 #define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
118  E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
119 #define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
120  E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
121 #define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
122  E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
123  E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
124 #define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
125  E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
126  E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
127 #define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
128  E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
129  E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
130  E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
131  E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
132  E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
133  E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
134  E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
135  E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
136  E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
137  E1000_COLC = 0x04028, /* Collision Count - R/clr */
138  E1000_DC = 0x04030, /* Defer Count - R/clr */
139  E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
140  E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
141  E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
142  E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
143  E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
144  E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
145  E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
146  E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
147  E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
148  E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
149  E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
150  E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
151  E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
152  E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
153  E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
154  E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
155  E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
156  E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
157  E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
158  E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
159  E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
160  E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
161  E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
162  E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
163  E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
164  E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
165  E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
166  E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
167  E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
168  E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
169  E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
170  E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
171  E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
172  E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
173  E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
174  E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
175  E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
176  E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
177  E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
178  E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
179  E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
180  E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
181  E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
182  E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
183  E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
184  E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
185  E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
186  E1000_IAC = 0x04100, /* Interrupt Assertion Count */
187  E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
188  E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
189  E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
190  E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
191  E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
192  E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
193  E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
194  E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
195  E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
196  E1000_RFCTL = 0x05008, /* Receive Filter Control */
197  E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
198  E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
199 #define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
200 #define E1000_RA (E1000_RAL(0))
201  E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
202 #define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
203  E1000_SHRAL_PCH_LPT_BASE = 0x05408,
204 #define E1000_SHRAL_PCH_LPT(_n) (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
205  E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
206 #define E1000_SHRAH_PCH_LPT(_n) (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
207  E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
208 #define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
209  E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
210 #define E1000_SHRAH(_n) (E1000_SHRAH_BASE + ((_n) * 8))
211  E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
212  E1000_WUC = 0x05800, /* Wakeup Control - RW */
213  E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
214  E1000_WUS = 0x05810, /* Wakeup Status - RO */
215  E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
216  E1000_MANC = 0x05820, /* Management Control - RW */
217  E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
218  E1000_HOST_IF = 0x08800, /* Host Interface */
219 
220  E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
221  E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
222  E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
223 #define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
224  E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
225  E1000_GCR = 0x05B00, /* PCI-Ex Control */
226  E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
227  E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
228  E1000_SWSM = 0x05B50, /* SW Semaphore */
229  E1000_FWSM = 0x05B54, /* FW Semaphore */
230  E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
231  E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
232 #define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
233  E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
234 #define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
235  E1000_FFLT_DBG = 0x05F04, /* Debug Register */
236  E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
237 #define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
238 #define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
239  E1000_HICR = 0x08F00, /* Host Interface Control */
240 };
241 
242 #define E1000_MAX_PHY_ADDR 4
243 
244 /* IGP01E1000 Specific Registers */
245 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
246 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
247 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
248 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
249 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
250 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
251 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
252 #define IGP_PAGE_SHIFT 5
253 #define PHY_REG_MASK 0x1F
254 
255 #define BM_WUC_PAGE 800
256 #define BM_WUC_ADDRESS_OPCODE 0x11
257 #define BM_WUC_DATA_OPCODE 0x12
258 #define BM_WUC_ENABLE_PAGE 769
259 #define BM_WUC_ENABLE_REG 17
260 #define BM_WUC_ENABLE_BIT (1 << 2)
261 #define BM_WUC_HOST_WU_BIT (1 << 4)
262 #define BM_WUC_ME_WU_BIT (1 << 5)
263 
264 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
265 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
266 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
267 
268 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
269 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
270 
271 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
272 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
273 
274 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
275 
276 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
277 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
278 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
279 
280 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
281 
282 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
283 #define IGP01E1000_PSSR_MDIX 0x0800
284 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
285 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
286 
287 #define IGP02E1000_PHY_CHANNEL_NUM 4
288 #define IGP02E1000_PHY_AGC_A 0x11B1
289 #define IGP02E1000_PHY_AGC_B 0x12B1
290 #define IGP02E1000_PHY_AGC_C 0x14B1
291 #define IGP02E1000_PHY_AGC_D 0x18B1
292 
293 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
294 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
295 #define IGP02E1000_AGC_RANGE 15
296 
297 /* manage.c */
298 #define E1000_VFTA_ENTRY_SHIFT 5
299 #define E1000_VFTA_ENTRY_MASK 0x7F
300 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
301 
302 #define E1000_HICR_EN 0x01 /* Enable bit - RO */
303 /* Driver sets this bit when done to put command in RAM */
304 #define E1000_HICR_C 0x02
305 #define E1000_HICR_FW_RESET_ENABLE 0x40
306 #define E1000_HICR_FW_RESET 0x80
307 
308 #define E1000_FWSM_MODE_MASK 0xE
309 #define E1000_FWSM_MODE_SHIFT 1
310 
311 #define E1000_MNG_IAMT_MODE 0x3
312 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
313 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
314 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
315 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
316 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
317 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
318 
319 /* nvm.c */
320 #define E1000_STM_OPCODE 0xDB00
321 
322 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
323 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
324 #define E1000_KMRNCTRLSTA_REN 0x00200000
325 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
326 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
327 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
328 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
329 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
330 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
331 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
332 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
333 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
334 
335 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
336 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
337 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
338 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
339 
340 /* IFE PHY Extended Status Control */
341 #define IFE_PESC_POLARITY_REVERSED 0x0100
342 
343 /* IFE PHY Special Control */
344 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
345 #define IFE_PSC_FORCE_POLARITY 0x0020
346 
347 /* IFE PHY Special Control and LED Control */
348 #define IFE_PSCL_PROBE_MODE 0x0020
349 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
350 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
351 
352 /* IFE PHY MDIX Control */
353 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
354 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
355 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
356 
357 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
358 
359 #define E1000_DEV_ID_82571EB_COPPER 0x105E
360 #define E1000_DEV_ID_82571EB_FIBER 0x105F
361 #define E1000_DEV_ID_82571EB_SERDES 0x1060
362 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
363 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
364 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
365 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
366 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
367 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
368 #define E1000_DEV_ID_82572EI_COPPER 0x107D
369 #define E1000_DEV_ID_82572EI_FIBER 0x107E
370 #define E1000_DEV_ID_82572EI_SERDES 0x107F
371 #define E1000_DEV_ID_82572EI 0x10B9
372 #define E1000_DEV_ID_82573E 0x108B
373 #define E1000_DEV_ID_82573E_IAMT 0x108C
374 #define E1000_DEV_ID_82573L 0x109A
375 #define E1000_DEV_ID_82574L 0x10D3
376 #define E1000_DEV_ID_82574LA 0x10F6
377 #define E1000_DEV_ID_82583V 0x150C
378 
379 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
380 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
381 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
382 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
383 
384 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
385 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
386 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
387 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
388 #define E1000_DEV_ID_ICH8_IFE 0x104C
389 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
390 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
391 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
392 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
393 #define E1000_DEV_ID_ICH9_BM 0x10E5
394 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
395 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
396 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
397 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
398 #define E1000_DEV_ID_ICH9_IFE 0x10C0
399 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
400 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
401 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
402 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
403 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
404 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
405 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
406 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
407 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
408 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
409 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
410 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
411 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
412 #define E1000_DEV_ID_PCH2_LV_V 0x1503
413 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
414 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
415 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
416 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
417 
418 #define E1000_REVISION_4 4
419 
420 #define E1000_FUNC_1 1
421 
422 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
423 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
424 
425 enum e1000_mac_type {
426  e1000_82571,
427  e1000_82572,
428  e1000_82573,
429  e1000_82574,
430  e1000_82583,
431  e1000_80003es2lan,
432  e1000_ich8lan,
433  e1000_ich9lan,
434  e1000_ich10lan,
435  e1000_pchlan,
436  e1000_pch2lan,
437  e1000_pch_lpt,
438 };
439 
440 enum e1000_media_type {
441  e1000_media_type_unknown = 0,
442  e1000_media_type_copper = 1,
443  e1000_media_type_fiber = 2,
444  e1000_media_type_internal_serdes = 3,
445  e1000_num_media_types
446 };
447 
448 enum e1000_nvm_type {
449  e1000_nvm_unknown = 0,
450  e1000_nvm_none,
451  e1000_nvm_eeprom_spi,
452  e1000_nvm_flash_hw,
453  e1000_nvm_flash_sw
454 };
455 
456 enum e1000_nvm_override {
457  e1000_nvm_override_none = 0,
458  e1000_nvm_override_spi_small,
459  e1000_nvm_override_spi_large
460 };
461 
462 enum e1000_phy_type {
463  e1000_phy_unknown = 0,
464  e1000_phy_none,
465  e1000_phy_m88,
466  e1000_phy_igp,
467  e1000_phy_igp_2,
468  e1000_phy_gg82563,
469  e1000_phy_igp_3,
470  e1000_phy_ife,
471  e1000_phy_bm,
472  e1000_phy_82578,
473  e1000_phy_82577,
474  e1000_phy_82579,
475  e1000_phy_i217,
476 };
477 
478 enum e1000_bus_width {
479  e1000_bus_width_unknown = 0,
480  e1000_bus_width_pcie_x1,
481  e1000_bus_width_pcie_x2,
482  e1000_bus_width_pcie_x4 = 4,
483  e1000_bus_width_32,
484  e1000_bus_width_64,
485  e1000_bus_width_reserved
486 };
487 
488 enum e1000_1000t_rx_status {
489  e1000_1000t_rx_status_not_ok = 0,
490  e1000_1000t_rx_status_ok,
491  e1000_1000t_rx_status_undefined = 0xFF
492 };
493 
494 enum e1000_rev_polarity{
495  e1000_rev_polarity_normal = 0,
496  e1000_rev_polarity_reversed,
497  e1000_rev_polarity_undefined = 0xFF
498 };
499 
500 enum e1000_fc_mode {
501  e1000_fc_none = 0,
502  e1000_fc_rx_pause,
503  e1000_fc_tx_pause,
504  e1000_fc_full,
505  e1000_fc_default = 0xFF
506 };
507 
508 enum e1000_ms_type {
509  e1000_ms_hw_default = 0,
510  e1000_ms_force_master,
511  e1000_ms_force_slave,
512  e1000_ms_auto
513 };
514 
515 enum e1000_smart_speed {
516  e1000_smart_speed_default = 0,
517  e1000_smart_speed_on,
518  e1000_smart_speed_off
519 };
520 
521 enum e1000_serdes_link_state {
522  e1000_serdes_link_down = 0,
523  e1000_serdes_link_autoneg_progress,
524  e1000_serdes_link_autoneg_complete,
525  e1000_serdes_link_forced_up
526 };
527 
528 /* Receive Descriptor */
529 struct e1000_rx_desc {
530  __le64 buffer_addr; /* Address of the descriptor's data buffer */
531  __le16 length; /* Length of data DMAed into data buffer */
532  __le16 csum; /* Packet checksum */
533  u8 status; /* Descriptor status */
534  u8 errors; /* Descriptor Errors */
535  __le16 special;
536 };
537 
538 /* Receive Descriptor - Extended */
539 union e1000_rx_desc_extended {
540  struct {
541  __le64 buffer_addr;
542  __le64 reserved;
543  } read;
544  struct {
545  struct {
546  __le32 mrq; /* Multiple Rx Queues */
547  union {
548  __le32 rss; /* RSS Hash */
549  struct {
550  __le16 ip_id; /* IP id */
551  __le16 csum; /* Packet Checksum */
552  } csum_ip;
553  } hi_dword;
554  } lower;
555  struct {
556  __le32 status_error; /* ext status/error */
557  __le16 length;
558  __le16 vlan; /* VLAN tag */
559  } upper;
560  } wb; /* writeback */
561 };
562 
563 #define MAX_PS_BUFFERS 4
564 /* Receive Descriptor - Packet Split */
565 union e1000_rx_desc_packet_split {
566  struct {
567  /* one buffer for protocol header(s), three data buffers */
568  __le64 buffer_addr[MAX_PS_BUFFERS];
569  } read;
570  struct {
571  struct {
572  __le32 mrq; /* Multiple Rx Queues */
573  union {
574  __le32 rss; /* RSS Hash */
575  struct {
576  __le16 ip_id; /* IP id */
577  __le16 csum; /* Packet Checksum */
578  } csum_ip;
579  } hi_dword;
580  } lower;
581  struct {
582  __le32 status_error; /* ext status/error */
583  __le16 length0; /* length of buffer 0 */
584  __le16 vlan; /* VLAN tag */
585  } middle;
586  struct {
587  __le16 header_status;
588  __le16 length[3]; /* length of buffers 1-3 */
589  } upper;
590  __le64 reserved;
591  } wb; /* writeback */
592 };
593 
594 /* Transmit Descriptor */
595 struct e1000_tx_desc {
596  __le64 buffer_addr; /* Address of the descriptor's data buffer */
597  union {
598  __le32 data;
599  struct {
600  __le16 length; /* Data buffer length */
601  u8 cso; /* Checksum offset */
602  u8 cmd; /* Descriptor control */
603  } flags;
604  } lower;
605  union {
606  __le32 data;
607  struct {
608  u8 status; /* Descriptor status */
609  u8 css; /* Checksum start */
610  __le16 special;
611  } fields;
612  } upper;
613 };
614 
615 /* Offload Context Descriptor */
616 struct e1000_context_desc {
617  union {
618  __le32 ip_config;
619  struct {
620  u8 ipcss; /* IP checksum start */
621  u8 ipcso; /* IP checksum offset */
622  __le16 ipcse; /* IP checksum end */
623  } ip_fields;
624  } lower_setup;
625  union {
626  __le32 tcp_config;
627  struct {
628  u8 tucss; /* TCP checksum start */
629  u8 tucso; /* TCP checksum offset */
630  __le16 tucse; /* TCP checksum end */
631  } tcp_fields;
632  } upper_setup;
633  __le32 cmd_and_length;
634  union {
635  __le32 data;
636  struct {
637  u8 status; /* Descriptor status */
638  u8 hdr_len; /* Header length */
639  __le16 mss; /* Maximum segment size */
640  } fields;
641  } tcp_seg_setup;
642 };
643 
644 /* Offload data descriptor */
645 struct e1000_data_desc {
646  __le64 buffer_addr; /* Address of the descriptor's buffer address */
647  union {
648  __le32 data;
649  struct {
650  __le16 length; /* Data buffer length */
651  u8 typ_len_ext;
652  u8 cmd;
653  } flags;
654  } lower;
655  union {
656  __le32 data;
657  struct {
658  u8 status; /* Descriptor status */
659  u8 popts; /* Packet Options */
660  __le16 special; /* */
661  } fields;
662  } upper;
663 };
664 
665 /* Statistics counters collected by the MAC */
666 struct e1000_hw_stats {
667  u64 crcerrs;
668  u64 algnerrc;
669  u64 symerrs;
670  u64 rxerrc;
671  u64 mpc;
672  u64 scc;
673  u64 ecol;
674  u64 mcc;
675  u64 latecol;
676  u64 colc;
677  u64 dc;
678  u64 tncrs;
679  u64 sec;
680  u64 cexterr;
681  u64 rlec;
682  u64 xonrxc;
683  u64 xontxc;
684  u64 xoffrxc;
685  u64 xofftxc;
686  u64 fcruc;
687  u64 prc64;
688  u64 prc127;
689  u64 prc255;
690  u64 prc511;
691  u64 prc1023;
692  u64 prc1522;
693  u64 gprc;
694  u64 bprc;
695  u64 mprc;
696  u64 gptc;
697  u64 gorc;
698  u64 gotc;
699  u64 rnbc;
700  u64 ruc;
701  u64 rfc;
702  u64 roc;
703  u64 rjc;
704  u64 mgprc;
705  u64 mgpdc;
706  u64 mgptc;
707  u64 tor;
708  u64 tot;
709  u64 tpr;
710  u64 tpt;
711  u64 ptc64;
712  u64 ptc127;
713  u64 ptc255;
714  u64 ptc511;
715  u64 ptc1023;
716  u64 ptc1522;
717  u64 mptc;
718  u64 bptc;
719  u64 tsctc;
720  u64 tsctfc;
721  u64 iac;
722  u64 icrxptc;
723  u64 icrxatc;
724  u64 ictxptc;
725  u64 ictxatc;
726  u64 ictxqec;
727  u64 ictxqmtc;
728  u64 icrxdmtc;
729  u64 icrxoc;
730 };
731 
732 struct e1000_phy_stats {
733  u32 idle_errors;
734  u32 receive_errors;
735 };
736 
737 struct e1000_host_mng_dhcp_cookie {
738  u32 signature;
739  u8 status;
740  u8 reserved0;
741  u16 vlan_id;
742  u32 reserved1;
743  u16 reserved2;
744  u8 reserved3;
745  u8 checksum;
746 };
747 
748 /* Host Interface "Rev 1" */
749 struct e1000_host_command_header {
750  u8 command_id;
751  u8 command_length;
752  u8 command_options;
753  u8 checksum;
754 };
755 
756 #define E1000_HI_MAX_DATA_LENGTH 252
757 struct e1000_host_command_info {
758  struct e1000_host_command_header command_header;
759  u8 command_data[E1000_HI_MAX_DATA_LENGTH];
760 };
761 
762 /* Host Interface "Rev 2" */
763 struct e1000_host_mng_command_header {
764  u8 command_id;
765  u8 checksum;
766  u16 reserved1;
767  u16 reserved2;
768  u16 command_length;
769 };
770 
771 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
772 struct e1000_host_mng_command_info {
773  struct e1000_host_mng_command_header command_header;
774  u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
775 };
776 
777 /* Function pointers and static data for the MAC. */
778 struct e1000_mac_operations {
779  s32 (*id_led_init)(struct e1000_hw *);
780  s32 (*blink_led)(struct e1000_hw *);
781  bool (*check_mng_mode)(struct e1000_hw *);
782  s32 (*check_for_link)(struct e1000_hw *);
783  s32 (*cleanup_led)(struct e1000_hw *);
784  void (*clear_hw_cntrs)(struct e1000_hw *);
785  void (*clear_vfta)(struct e1000_hw *);
786  s32 (*get_bus_info)(struct e1000_hw *);
787  void (*set_lan_id)(struct e1000_hw *);
788  s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
789  s32 (*led_on)(struct e1000_hw *);
790  s32 (*led_off)(struct e1000_hw *);
791  void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
792  s32 (*reset_hw)(struct e1000_hw *);
793  s32 (*init_hw)(struct e1000_hw *);
794  s32 (*setup_link)(struct e1000_hw *);
795  s32 (*setup_physical_interface)(struct e1000_hw *);
796  s32 (*setup_led)(struct e1000_hw *);
797  void (*write_vfta)(struct e1000_hw *, u32, u32);
798  void (*config_collision_dist)(struct e1000_hw *);
799  void (*rar_set)(struct e1000_hw *, u8 *, u32);
800  s32 (*read_mac_addr)(struct e1000_hw *);
801 };
802 
803 /*
804  * When to use various PHY register access functions:
805  *
806  * Func Caller
807  * Function Does Does When to use
808  * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
809  * X_reg L,P,A n/a for simple PHY reg accesses
810  * X_reg_locked P,A L for multiple accesses of different regs
811  * on different pages
812  * X_reg_page A L,P for multiple accesses of different regs
813  * on the same page
814  *
815  * Where X=[read|write], L=locking, P=sets page, A=register access
816  *
817  */
818 struct e1000_phy_operations {
819  s32 (*acquire)(struct e1000_hw *);
820  s32 (*cfg_on_link_up)(struct e1000_hw *);
821  s32 (*check_polarity)(struct e1000_hw *);
822  s32 (*check_reset_block)(struct e1000_hw *);
823  s32 (*commit)(struct e1000_hw *);
824  s32 (*force_speed_duplex)(struct e1000_hw *);
825  s32 (*get_cfg_done)(struct e1000_hw *hw);
826  s32 (*get_cable_length)(struct e1000_hw *);
827  s32 (*get_info)(struct e1000_hw *);
828  s32 (*set_page)(struct e1000_hw *, u16);
829  s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
830  s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
831  s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
832  void (*release)(struct e1000_hw *);
833  s32 (*reset)(struct e1000_hw *);
834  s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
835  s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
836  s32 (*write_reg)(struct e1000_hw *, u32, u16);
837  s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
838  s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
839  void (*power_up)(struct e1000_hw *);
840  void (*power_down)(struct e1000_hw *);
841 };
842 
843 /* Function pointers for the NVM. */
844 struct e1000_nvm_operations {
845  s32 (*acquire)(struct e1000_hw *);
846  s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
847  void (*release)(struct e1000_hw *);
848  void (*reload)(struct e1000_hw *);
849  s32 (*update)(struct e1000_hw *);
850  s32 (*valid_led_default)(struct e1000_hw *, u16 *);
851  s32 (*validate)(struct e1000_hw *);
852  s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
853 };
854 
855 struct e1000_mac_info {
856  struct e1000_mac_operations ops;
857  u8 addr[ETH_ALEN];
858  u8 perm_addr[ETH_ALEN];
859 
860  enum e1000_mac_type type;
861 
862  u32 collision_delta;
863  u32 ledctl_default;
864  u32 ledctl_mode1;
865  u32 ledctl_mode2;
866  u32 mc_filter_type;
867  u32 tx_packet_delta;
868  u32 txcw;
869 
870  u16 current_ifs_val;
871  u16 ifs_max_val;
872  u16 ifs_min_val;
873  u16 ifs_ratio;
874  u16 ifs_step_size;
875  u16 mta_reg_count;
876 
877  /* Maximum size of the MTA register table in all supported adapters */
878  #define MAX_MTA_REG 128
879  u32 mta_shadow[MAX_MTA_REG];
880  u16 rar_entry_count;
881 
882  u8 forced_speed_duplex;
883 
884  bool adaptive_ifs;
885  bool has_fwsm;
886  bool arc_subsystem_valid;
887  bool autoneg;
888  bool autoneg_failed;
889  bool get_link_status;
890  bool in_ifs_mode;
891  bool serdes_has_link;
892  bool tx_pkt_filtering;
893  enum e1000_serdes_link_state serdes_link_state;
894 };
895 
896 struct e1000_phy_info {
897  struct e1000_phy_operations ops;
898 
899  enum e1000_phy_type type;
900 
901  enum e1000_1000t_rx_status local_rx;
902  enum e1000_1000t_rx_status remote_rx;
903  enum e1000_ms_type ms_type;
904  enum e1000_ms_type original_ms_type;
905  enum e1000_rev_polarity cable_polarity;
906  enum e1000_smart_speed smart_speed;
907 
908  u32 addr;
909  u32 id;
910  u32 reset_delay_us; /* in usec */
911  u32 revision;
912 
913  enum e1000_media_type media_type;
914 
915  u16 autoneg_advertised;
916  u16 autoneg_mask;
917  u16 cable_length;
918  u16 max_cable_length;
919  u16 min_cable_length;
920 
921  u8 mdix;
922 
923  bool disable_polarity_correction;
924  bool is_mdix;
925  bool polarity_correction;
926  bool speed_downgraded;
927  bool autoneg_wait_to_complete;
928 };
929 
930 struct e1000_nvm_info {
931  struct e1000_nvm_operations ops;
932 
933  enum e1000_nvm_type type;
934  enum e1000_nvm_override override;
935 
936  u32 flash_bank_size;
937  u32 flash_base_addr;
938 
939  u16 word_size;
940  u16 delay_usec;
941  u16 address_bits;
942  u16 opcode_bits;
943  u16 page_size;
944 };
945 
946 struct e1000_bus_info {
947  enum e1000_bus_width width;
948 
949  u16 func;
950 };
951 
952 struct e1000_fc_info {
953  u32 high_water; /* Flow control high-water mark */
954  u32 low_water; /* Flow control low-water mark */
955  u16 pause_time; /* Flow control pause timer */
956  u16 refresh_time; /* Flow control refresh timer */
957  bool send_xon; /* Flow control send XON */
958  bool strict_ieee; /* Strict IEEE mode */
959  enum e1000_fc_mode current_mode; /* FC mode in effect */
960  enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
961 };
962 
963 struct e1000_dev_spec_82571 {
964  bool laa_is_present;
965  u32 smb_counter;
966 };
967 
968 struct e1000_dev_spec_80003es2lan {
969  bool mdic_wa_enable;
970 };
971 
972 struct e1000_shadow_ram {
973  u16 value;
974  bool modified;
975 };
976 
977 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
978 
979 struct e1000_dev_spec_ich8lan {
980  bool kmrn_lock_loss_workaround_enabled;
981  struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
982  bool nvm_k1_enabled;
983  bool eee_disable;
984  u16 eee_lp_ability;
985 };
986 
987 struct e1000_hw {
988  struct e1000_adapter *adapter;
989 
990  void __iomem *hw_addr;
991  void __iomem *flash_address;
992 
993  struct e1000_mac_info mac;
994  struct e1000_fc_info fc;
995  struct e1000_phy_info phy;
996  struct e1000_nvm_info nvm;
997  struct e1000_bus_info bus;
998  struct e1000_host_mng_dhcp_cookie mng_cookie;
999 
1000  union {
1001  struct e1000_dev_spec_82571 e82571;
1002  struct e1000_dev_spec_80003es2lan e80003es2lan;
1003  struct e1000_dev_spec_ich8lan ich8lan;
1004  } dev_spec;
1005 };
1006 
1007 #endif
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