defines.h File Reference

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Macros
#define	E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */
#define	E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */
#define	E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */
#define	E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
#define	E1000_TXD_CMD_IC   0x04000000 /* Insert Checksum */
#define	E1000_TXD_CMD_RS   0x08000000 /* Report Status */
#define	E1000_TXD_CMD_RPS   0x10000000 /* Report Packet Sent */
#define	E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
#define	E1000_TXD_CMD_VLE   0x40000000 /* Add VLAN tag */
#define	E1000_TXD_CMD_IDE   0x80000000 /* Enable Tidv register */
#define	E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */
#define	E1000_TXD_STAT_EC   0x00000002 /* Excess Collisions */
#define	E1000_TXD_STAT_LC   0x00000004 /* Late Collisions */
#define	E1000_TXD_STAT_TU   0x00000008 /* Transmit underrun */
#define	E1000_TXD_CMD_TCP   0x01000000 /* TCP packet */
#define	E1000_TXD_CMD_IP   0x02000000 /* IP packet */
#define	E1000_TXD_CMD_TSE   0x04000000 /* TCP Seg enable */
#define	E1000_TXD_STAT_TC   0x00000004 /* Tx Underrun */
#define	REQ_TX_DESCRIPTOR_MULTIPLE   8
#define	REQ_RX_DESCRIPTOR_MULTIPLE   8
#define	E1000_WUC_APME   0x00000001 /* APM Enable */
#define	E1000_WUC_PME_EN   0x00000002 /* PME Enable */
#define	E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
#define	E1000_WUFC_LNKC   0x00000001 /* Link Status Change Wakeup Enable */
#define	E1000_WUFC_MAG   0x00000002 /* Magic Packet Wakeup Enable */
#define	E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
#define	E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
#define	E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
#define	E1000_WUFC_ARP   0x00000020 /* ARP Request Packet Wakeup Enable */
#define	E1000_WUS_LNKC   E1000_WUFC_LNKC
#define	E1000_WUS_MAG   E1000_WUFC_MAG
#define	E1000_WUS_EX   E1000_WUFC_EX
#define	E1000_WUS_MC   E1000_WUFC_MC
#define	E1000_WUS_BC   E1000_WUFC_BC
#define	E1000_CTRL_EXT_LPCD   0x00000004 /* LCD Power Cycle Done */
#define	E1000_CTRL_EXT_SDP3_DATA   0x00000080 /* Value of SW Definable Pin 3 */
#define	E1000_CTRL_EXT_FORCE_SMBUS   0x00000800 /* Force SMBus mode */
#define	E1000_CTRL_EXT_EE_RST   0x00002000 /* Reinitialize from EEPROM */
#define	E1000_CTRL_EXT_SPD_BYPS   0x00008000 /* Speed Select Bypass */
#define	E1000_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
#define	E1000_CTRL_EXT_DMA_DYN_CLK_EN   0x00080000 /* DMA Dynamic Clock Gating */
#define	E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000
#define	E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES   0x00C00000
#define	E1000_CTRL_EXT_EIAME   0x01000000
#define	E1000_CTRL_EXT_DRV_LOAD   0x10000000 /* Driver loaded bit for FW */
#define	E1000_CTRL_EXT_IAME   0x08000000 /* Interrupt acknowledge Auto-mask */
#define	E1000_CTRL_EXT_INT_TIMER_CLR   0x20000000 /* Clear Interrupt timers after IMS clear */
#define	E1000_CTRL_EXT_PBA_CLR   0x80000000 /* PBA Clear */
#define	E1000_CTRL_EXT_LSECCK   0x00001000
#define	E1000_CTRL_EXT_PHYPDEN   0x00100000
#define	E1000_RXD_STAT_DD   0x01 /* Descriptor Done */
#define	E1000_RXD_STAT_EOP   0x02 /* End of Packet */
#define	E1000_RXD_STAT_IXSM   0x04 /* Ignore checksum */
#define	E1000_RXD_STAT_VP   0x08 /* IEEE VLAN Packet */
#define	E1000_RXD_STAT_UDPCS   0x10 /* UDP xsum calculated */
#define	E1000_RXD_STAT_TCPCS   0x20 /* TCP xsum calculated */
#define	E1000_RXD_ERR_CE   0x01 /* CRC Error */
#define	E1000_RXD_ERR_SE   0x02 /* Symbol Error */
#define	E1000_RXD_ERR_SEQ   0x04 /* Sequence Error */
#define	E1000_RXD_ERR_CXE   0x10 /* Carrier Extension Error */
#define	E1000_RXD_ERR_TCPE   0x20 /* TCP/UDP Checksum Error */
#define	E1000_RXD_ERR_IPE   0x40 /* IP Checksum Error */
#define	E1000_RXD_ERR_RXE   0x80 /* Rx Data Error */
#define	E1000_RXD_SPC_VLAN_MASK   0x0FFF /* VLAN ID is in lower 12 bits */
#define	E1000_RXDEXT_STATERR_CE   0x01000000
#define	E1000_RXDEXT_STATERR_SE   0x02000000
#define	E1000_RXDEXT_STATERR_SEQ   0x04000000
#define	E1000_RXDEXT_STATERR_CXE   0x10000000
#define	E1000_RXDEXT_STATERR_RXE   0x80000000
#define	E1000_RXD_ERR_FRAME_ERR_MASK
#define	E1000_RXDEXT_ERR_FRAME_ERR_MASK
#define	E1000_MRQC_RSS_FIELD_MASK   0xFFFF0000
#define	E1000_MRQC_RSS_FIELD_IPV4_TCP   0x00010000
#define	E1000_MRQC_RSS_FIELD_IPV4   0x00020000
#define	E1000_MRQC_RSS_FIELD_IPV6_TCP_EX   0x00040000
#define	E1000_MRQC_RSS_FIELD_IPV6   0x00100000
#define	E1000_MRQC_RSS_FIELD_IPV6_TCP   0x00200000
#define	E1000_RXDPS_HDRSTAT_HDRSP   0x00008000
#define	E1000_MANC_SMBUS_EN   0x00000001 /* SMBus Enabled - RO */
#define	E1000_MANC_ASF_EN   0x00000002 /* ASF Enabled - RO */
#define	E1000_MANC_ARP_EN   0x00002000 /* Enable ARP Request Filtering */
#define	E1000_MANC_RCV_TCO_EN   0x00020000 /* Receive TCO Packets Enabled */
#define	E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
#define	E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
#define	E1000_MANC_EN_MNG2HOST   0x00200000
#define	E1000_MANC2H_PORT_623   0x00000020 /* Port 0x26f */
#define	E1000_MANC2H_PORT_664   0x00000040 /* Port 0x298 */
#define	E1000_MDEF_PORT_623   0x00000800 /* Port 0x26f */
#define	E1000_MDEF_PORT_664   0x00000400 /* Port 0x298 */
#define	E1000_RCTL_EN   0x00000002 /* enable */
#define	E1000_RCTL_SBP   0x00000004 /* store bad packet */
#define	E1000_RCTL_UPE   0x00000008 /* unicast promiscuous enable */
#define	E1000_RCTL_MPE   0x00000010 /* multicast promiscuous enab */
#define	E1000_RCTL_LPE   0x00000020 /* long packet enable */
#define	E1000_RCTL_LBM_NO   0x00000000 /* no loopback mode */
#define	E1000_RCTL_LBM_MAC   0x00000040 /* MAC loopback mode */
#define	E1000_RCTL_LBM_TCVR   0x000000C0 /* tcvr loopback mode */
#define	E1000_RCTL_DTYP_PS   0x00000400 /* Packet Split descriptor */
#define	E1000_RCTL_RDMTS_HALF   0x00000000 /* Rx desc min threshold size */
#define	E1000_RCTL_MO_SHIFT   12 /* multicast offset shift */
#define	E1000_RCTL_MO_3   0x00003000 /* multicast offset 15:4 */
#define	E1000_RCTL_BAM   0x00008000 /* broadcast enable */
#define	E1000_RCTL_SZ_2048   0x00000000 /* Rx buffer size 2048 */
#define	E1000_RCTL_SZ_1024   0x00010000 /* Rx buffer size 1024 */
#define	E1000_RCTL_SZ_512   0x00020000 /* Rx buffer size 512 */
#define	E1000_RCTL_SZ_256   0x00030000 /* Rx buffer size 256 */
#define	E1000_RCTL_SZ_16384   0x00010000 /* Rx buffer size 16384 */
#define	E1000_RCTL_SZ_8192   0x00020000 /* Rx buffer size 8192 */
#define	E1000_RCTL_SZ_4096   0x00030000 /* Rx buffer size 4096 */
#define	E1000_RCTL_VFE   0x00040000 /* vlan filter enable */
#define	E1000_RCTL_CFIEN   0x00080000 /* canonical form enable */
#define	E1000_RCTL_CFI   0x00100000 /* canonical form indicator */
#define	E1000_RCTL_DPF   0x00400000 /* Discard Pause Frames */
#define	E1000_RCTL_PMCF   0x00800000 /* pass MAC control frames */
#define	E1000_RCTL_BSEX   0x02000000 /* Buffer size extension */
#define	E1000_RCTL_SECRC   0x04000000 /* Strip Ethernet CRC */
#define	E1000_PSRCTL_BSIZE0_MASK   0x0000007F
#define	E1000_PSRCTL_BSIZE1_MASK   0x00003F00
#define	E1000_PSRCTL_BSIZE2_MASK   0x003F0000
#define	E1000_PSRCTL_BSIZE3_MASK   0x3F000000
#define	E1000_PSRCTL_BSIZE0_SHIFT   7 /* Shift _right_ 7 */
#define	E1000_PSRCTL_BSIZE1_SHIFT   2 /* Shift _right_ 2 */
#define	E1000_PSRCTL_BSIZE2_SHIFT   6 /* Shift _left_ 6 */
#define	E1000_PSRCTL_BSIZE3_SHIFT   14 /* Shift _left_ 14 */
#define	E1000_SWFW_EEP_SM   0x1
#define	E1000_SWFW_PHY0_SM   0x2
#define	E1000_SWFW_PHY1_SM   0x4
#define	E1000_SWFW_CSR_SM   0x8
#define	E1000_CTRL_FD   0x00000001 /* Full duplex.0=half; 1=full */
#define	E1000_CTRL_GIO_MASTER_DISABLE   0x00000004 /*Blocks new Master requests */
#define	E1000_CTRL_LRST   0x00000008 /* Link reset. 0=normal,1=reset */
#define	E1000_CTRL_ASDE   0x00000020 /* Auto-speed detect enable */
#define	E1000_CTRL_SLU   0x00000040 /* Set link up (Force Link) */
#define	E1000_CTRL_ILOS   0x00000080 /* Invert Loss-Of Signal */
#define	E1000_CTRL_SPD_SEL   0x00000300 /* Speed Select Mask */
#define	E1000_CTRL_SPD_10   0x00000000 /* Force 10Mb */
#define	E1000_CTRL_SPD_100   0x00000100 /* Force 100Mb */
#define	E1000_CTRL_SPD_1000   0x00000200 /* Force 1Gb */
#define	E1000_CTRL_FRCSPD   0x00000800 /* Force Speed */
#define	E1000_CTRL_FRCDPX   0x00001000 /* Force Duplex */
#define	E1000_CTRL_LANPHYPC_OVERRIDE   0x00010000 /* SW control of LANPHYPC */
#define	E1000_CTRL_LANPHYPC_VALUE   0x00020000 /* SW value of LANPHYPC */
#define	E1000_CTRL_SWDPIN0   0x00040000 /* SWDPIN 0 value */
#define	E1000_CTRL_SWDPIN1   0x00080000 /* SWDPIN 1 value */
#define	E1000_CTRL_SWDPIO0   0x00400000 /* SWDPIN 0 Input or output */
#define	E1000_CTRL_RST   0x04000000 /* Global reset */
#define	E1000_CTRL_RFCE   0x08000000 /* Receive Flow Control enable */
#define	E1000_CTRL_TFCE   0x10000000 /* Transmit flow control enable */
#define	E1000_CTRL_VME   0x40000000 /* IEEE VLAN mode enable */
#define	E1000_CTRL_PHY_RST   0x80000000 /* PHY Reset */
#define	E1000_STATUS_FD   0x00000001 /* Full duplex.0=half,1=full */
#define	E1000_STATUS_LU   0x00000002 /* Link up.0=no,1=link */
#define	E1000_STATUS_FUNC_MASK   0x0000000C /* PCI Function Mask */
#define	E1000_STATUS_FUNC_SHIFT   2
#define	E1000_STATUS_FUNC_1   0x00000004 /* Function 1 */
#define	E1000_STATUS_TXOFF   0x00000010 /* transmission paused */
#define	E1000_STATUS_SPEED_10   0x00000000 /* Speed 10Mb/s */
#define	E1000_STATUS_SPEED_100   0x00000040 /* Speed 100Mb/s */
#define	E1000_STATUS_SPEED_1000   0x00000080 /* Speed 1000Mb/s */
#define	E1000_STATUS_LAN_INIT_DONE   0x00000200 /* Lan Init Completion by NVM */
#define	E1000_STATUS_PHYRA   0x00000400 /* PHY Reset Asserted */
#define	E1000_STATUS_GIO_MASTER_ENABLE   0x00080000 /* Status of Master requests. */
#define	HALF_DUPLEX   1
#define	FULL_DUPLEX   2
#define	ADVERTISE_10_HALF   0x0001
#define	ADVERTISE_10_FULL   0x0002
#define	ADVERTISE_100_HALF   0x0004
#define	ADVERTISE_100_FULL   0x0008
#define	ADVERTISE_1000_HALF   0x0010 /* Not used, just FYI */
#define	ADVERTISE_1000_FULL   0x0020
#define	E1000_ALL_SPEED_DUPLEX
#define	E1000_ALL_NOT_GIG
#define	E1000_ALL_100_SPEED   (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
#define	E1000_ALL_10_SPEED   (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
#define	E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
#define	AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
#define	E1000_PHY_LED0_MODE_MASK   0x00000007
#define	E1000_PHY_LED0_IVRT   0x00000008
#define	E1000_PHY_LED0_MASK   0x0000001F
#define	E1000_LEDCTL_LED0_MODE_MASK   0x0000000F
#define	E1000_LEDCTL_LED0_MODE_SHIFT   0
#define	E1000_LEDCTL_LED0_IVRT   0x00000040
#define	E1000_LEDCTL_LED0_BLINK   0x00000080
#define	E1000_LEDCTL_MODE_LINK_UP   0x2
#define	E1000_LEDCTL_MODE_LED_ON   0xE
#define	E1000_LEDCTL_MODE_LED_OFF   0xF
#define	E1000_TXD_DTYP_D   0x00100000 /* Data Descriptor */
#define	E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */
#define	E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */
#define	E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */
#define	E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
#define	E1000_TXD_CMD_IC   0x04000000 /* Insert Checksum */
#define	E1000_TXD_CMD_RS   0x08000000 /* Report Status */
#define	E1000_TXD_CMD_RPS   0x10000000 /* Report Packet Sent */
#define	E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
#define	E1000_TXD_CMD_VLE   0x40000000 /* Add VLAN tag */
#define	E1000_TXD_CMD_IDE   0x80000000 /* Enable Tidv register */
#define	E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */
#define	E1000_TXD_STAT_EC   0x00000002 /* Excess Collisions */
#define	E1000_TXD_STAT_LC   0x00000004 /* Late Collisions */
#define	E1000_TXD_STAT_TU   0x00000008 /* Transmit underrun */
#define	E1000_TXD_CMD_TCP   0x01000000 /* TCP packet */
#define	E1000_TXD_CMD_IP   0x02000000 /* IP packet */
#define	E1000_TXD_CMD_TSE   0x04000000 /* TCP Seg enable */
#define	E1000_TXD_STAT_TC   0x00000004 /* Tx Underrun */
#define	E1000_TCTL_EN   0x00000002 /* enable Tx */
#define	E1000_TCTL_PSP   0x00000008 /* pad short packets */
#define	E1000_TCTL_CT   0x00000ff0 /* collision threshold */
#define	E1000_TCTL_COLD   0x003ff000 /* collision distance */
#define	E1000_TCTL_RTLC   0x01000000 /* Re-transmit on late collision */
#define	E1000_TCTL_MULR   0x10000000 /* Multiple request support */
#define	E1000_SCTL_DISABLE_SERDES_LOOPBACK   0x0400
#define	E1000_RXCSUM_TUOFL   0x00000200 /* TCP / UDP checksum offload */
#define	E1000_RXCSUM_IPPCSE   0x00001000 /* IP payload checksum enable */
#define	E1000_RXCSUM_PCSD   0x00002000 /* packet checksum disabled */
#define	E1000_RFCTL_NFSW_DIS   0x00000040
#define	E1000_RFCTL_NFSR_DIS   0x00000080
#define	E1000_RFCTL_ACK_DIS   0x00001000
#define	E1000_RFCTL_EXTEN   0x00008000
#define	E1000_RFCTL_IPV6_EX_DIS   0x00010000
#define	E1000_RFCTL_NEW_IPV6_EXT_DIS   0x00020000
#define	E1000_COLLISION_THRESHOLD   15
#define	E1000_CT_SHIFT   4
#define	E1000_COLLISION_DISTANCE   63
#define	E1000_COLD_SHIFT   12
#define	DEFAULT_82543_TIPG_IPGT_COPPER   8
#define	E1000_TIPG_IPGT_MASK   0x000003FF
#define	DEFAULT_82543_TIPG_IPGR1   8
#define	E1000_TIPG_IPGR1_SHIFT   10
#define	DEFAULT_82543_TIPG_IPGR2   6
#define	DEFAULT_80003ES2LAN_TIPG_IPGR2   7
#define	E1000_TIPG_IPGR2_SHIFT   20
#define	MAX_JUMBO_FRAME_SIZE   0x3F00
#define	E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP   0x00000020
#define	E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE   0x00000001
#define	E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE   0x00000008
#define	E1000_EXTCNF_CTRL_SWFLAG   0x00000020
#define	E1000_EXTCNF_CTRL_GATE_PHY_CFG   0x00000080
#define	E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
#define	E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT   16
#define	E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
#define	E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT   16
#define	E1000_PHY_CTRL_D0A_LPLU   0x00000002
#define	E1000_PHY_CTRL_NOND0A_LPLU   0x00000004
#define	E1000_PHY_CTRL_NOND0A_GBE_DISABLE   0x00000008
#define	E1000_PHY_CTRL_GBE_DISABLE   0x00000040
#define	E1000_KABGTXD_BGSQLBIAS   0x00050000
#define	E1000_PBA_8K   0x0008 /* 8KB */
#define	E1000_PBA_16K   0x0010 /* 16KB */
#define	E1000_PBS_16K   E1000_PBA_16K
#define	IFS_MAX   80
#define	IFS_MIN   40
#define	IFS_RATIO   4
#define	IFS_STEP   10
#define	MIN_NUM_XMITS   1000
#define	E1000_SWSM_SMBI   0x00000001 /* Driver Semaphore bit */
#define	E1000_SWSM_SWESMBI   0x00000002 /* FW Semaphore bit */
#define	E1000_SWSM_DRV_LOAD   0x00000008 /* Driver Loaded Bit */
#define	E1000_SWSM2_LOCK   0x00000002 /* Secondary driver semaphore bit */
#define	E1000_ICR_TXDW   0x00000001 /* Transmit desc written back */
#define	E1000_ICR_LSC   0x00000004 /* Link Status Change */
#define	E1000_ICR_RXSEQ   0x00000008 /* Rx sequence error */
#define	E1000_ICR_RXDMT0   0x00000010 /* Rx desc min. threshold (0) */
#define	E1000_ICR_RXT0   0x00000080 /* Rx timer intr (ring 0) */
#define	E1000_ICR_INT_ASSERTED   0x80000000 /* If this bit asserted, the driver should claim the interrupt */
#define	E1000_ICR_RXQ0   0x00100000 /* Rx Queue 0 Interrupt */
#define	E1000_ICR_RXQ1   0x00200000 /* Rx Queue 1 Interrupt */
#define	E1000_ICR_TXQ0   0x00400000 /* Tx Queue 0 Interrupt */
#define	E1000_ICR_TXQ1   0x00800000 /* Tx Queue 1 Interrupt */
#define	E1000_ICR_OTHER   0x01000000 /* Other Interrupts */
#define	E1000_PBA_ECC_COUNTER_MASK   0xFFF00000 /* ECC counter mask */
#define	E1000_PBA_ECC_COUNTER_SHIFT   20 /* ECC counter shift value */
#define	E1000_PBA_ECC_CORR_EN   0x00000001 /* ECC correction enable */
#define	E1000_PBA_ECC_STAT_CLR   0x00000002 /* Clear ECC error counter */
#define	E1000_PBA_ECC_INT_EN   0x00000004 /* Enable ICR bit 5 for ECC */
#define	IMS_ENABLE_MASK
#define	E1000_IMS_TXDW   E1000_ICR_TXDW /* Transmit desc written back */
#define	E1000_IMS_LSC   E1000_ICR_LSC /* Link Status Change */
#define	E1000_IMS_RXSEQ   E1000_ICR_RXSEQ /* Rx sequence error */
#define	E1000_IMS_RXDMT0   E1000_ICR_RXDMT0 /* Rx desc min. threshold */
#define	E1000_IMS_RXT0   E1000_ICR_RXT0 /* Rx timer intr */
#define	E1000_IMS_RXQ0   E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
#define	E1000_IMS_RXQ1   E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
#define	E1000_IMS_TXQ0   E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
#define	E1000_IMS_TXQ1   E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
#define	E1000_IMS_OTHER   E1000_ICR_OTHER /* Other Interrupts */
#define	E1000_ICS_LSC   E1000_ICR_LSC /* Link Status Change */
#define	E1000_ICS_RXSEQ   E1000_ICR_RXSEQ /* Rx sequence error */
#define	E1000_ICS_RXDMT0   E1000_ICR_RXDMT0 /* Rx desc min. threshold */
#define	E1000_TXDCTL_PTHRESH   0x0000003F /* TXDCTL Prefetch Threshold */
#define	E1000_TXDCTL_HTHRESH   0x00003F00 /* TXDCTL Host Threshold */
#define	E1000_TXDCTL_WTHRESH   0x003F0000 /* TXDCTL Writeback Threshold */
#define	E1000_TXDCTL_GRAN   0x01000000 /* TXDCTL Granularity */
#define	E1000_TXDCTL_FULL_TX_DESC_WB   0x01010000 /* GRAN=1, WTHRESH=1 */
#define	E1000_TXDCTL_MAX_TX_DESC_PREFETCH   0x0100001F /* GRAN=1, PTHRESH=31 */
#define	E1000_TXDCTL_COUNT_DESC   0x00400000
#define	FLOW_CONTROL_ADDRESS_LOW   0x00C28001
#define	FLOW_CONTROL_ADDRESS_HIGH   0x00000100
#define	FLOW_CONTROL_TYPE   0x8808
#define	E1000_VLAN_FILTER_TBL_SIZE   128 /* VLAN Filter Table (4096 bits) */
#define	E1000_RAR_ENTRIES   15
#define	E1000_RAH_AV   0x80000000 /* Receive descriptor valid */
#define	E1000_RAL_MAC_ADDR_LEN   4
#define	E1000_RAH_MAC_ADDR_LEN   2
#define	E1000_ERR_NVM   1
#define	E1000_ERR_PHY   2
#define	E1000_ERR_CONFIG   3
#define	E1000_ERR_PARAM   4
#define	E1000_ERR_MAC_INIT   5
#define	E1000_ERR_PHY_TYPE   6
#define	E1000_ERR_RESET   9
#define	E1000_ERR_MASTER_REQUESTS_PENDING   10
#define	E1000_ERR_HOST_INTERFACE_COMMAND   11
#define	E1000_BLK_PHY_RESET   12
#define	E1000_ERR_SWFW_SYNC   13
#define	E1000_NOT_IMPLEMENTED   14
#define	E1000_ERR_INVALID_ARGUMENT   16
#define	E1000_ERR_NO_SPACE   17
#define	E1000_ERR_NVM_PBA_SECTION   18
#define	FIBER_LINK_UP_LIMIT   50
#define	COPPER_LINK_UP_LIMIT   10
#define	PHY_AUTO_NEG_LIMIT   45
#define	PHY_FORCE_LIMIT   20
#define	MASTER_DISABLE_TIMEOUT   800
#define	PHY_CFG_TIMEOUT   100
#define	MDIO_OWNERSHIP_TIMEOUT   10
#define	AUTO_READ_DONE_TIMEOUT   10
#define	E1000_FCRTH_RTH   0x0000FFF8 /* Mask Bits[15:3] for RTH */
#define	E1000_FCRTL_RTL   0x0000FFF8 /* Mask Bits[15:3] for RTL */
#define	E1000_FCRTL_XONE   0x80000000 /* Enable XON frame transmission */
#define	E1000_TXCW_FD   0x00000020 /* TXCW full duplex */
#define	E1000_TXCW_PAUSE   0x00000080 /* TXCW sym pause request */
#define	E1000_TXCW_ASM_DIR   0x00000100 /* TXCW astm pause direction */
#define	E1000_TXCW_PAUSE_MASK   0x00000180 /* TXCW pause request mask */
#define	E1000_TXCW_ANE   0x80000000 /* Auto-neg enable */
#define	E1000_RXCW_CW   0x0000ffff /* RxConfigWord mask */
#define	E1000_RXCW_IV   0x08000000 /* Receive config invalid */
#define	E1000_RXCW_C   0x20000000 /* Receive config */
#define	E1000_RXCW_SYNCH   0x40000000 /* Receive config synch */
#define	E1000_GCR_RXD_NO_SNOOP   0x00000001
#define	E1000_GCR_RXDSCW_NO_SNOOP   0x00000002
#define	E1000_GCR_RXDSCR_NO_SNOOP   0x00000004
#define	E1000_GCR_TXD_NO_SNOOP   0x00000008
#define	E1000_GCR_TXDSCW_NO_SNOOP   0x00000010
#define	E1000_GCR_TXDSCR_NO_SNOOP   0x00000020
#define	PCIE_NO_SNOOP_ALL
#define	MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */
#define	MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */
#define	MII_CR_POWER_DOWN   0x0800 /* Power down */
#define	MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */
#define	MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */
#define	MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */
#define	MII_CR_SPEED_1000   0x0040
#define	MII_CR_SPEED_100   0x2000
#define	MII_CR_SPEED_10   0x0000
#define	MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */
#define	MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */
#define	NWAY_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */
#define	NWAY_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */
#define	NWAY_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */
#define	NWAY_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */
#define	NWAY_AR_PAUSE   0x0400 /* Pause operation desired */
#define	NWAY_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */
#define	NWAY_LPAR_100TX_FD_CAPS   0x0100 /* LP 100TX Full Dplx Capable */
#define	NWAY_LPAR_PAUSE   0x0400 /* LP Pause operation desired */
#define	NWAY_LPAR_ASM_DIR   0x0800 /* LP Asymmetric Pause Direction bit */
#define	NWAY_ER_LP_NWAY_CAPS   0x0001 /* LP has Auto Neg Capability */
#define	CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */
#define	CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */
#define	CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */
#define	CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */
#define	SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */
#define	SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */
#define	PHY_CONTROL   0x00 /* Control Register */
#define	PHY_STATUS   0x01 /* Status Register */
#define	PHY_ID1   0x02 /* Phy Id Reg (word 1) */
#define	PHY_ID2   0x03 /* Phy Id Reg (word 2) */
#define	PHY_AUTONEG_ADV   0x04 /* Autoneg Advertisement */
#define	PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
#define	PHY_AUTONEG_EXP   0x06 /* Autoneg Expansion Reg */
#define	PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
#define	PHY_1000T_STATUS   0x0A /* 1000Base-T Status Reg */
#define	PHY_EXT_STATUS   0x0F /* Extended Status Reg */
#define	PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
#define	E1000_EECD_SK   0x00000001 /* NVM Clock */
#define	E1000_EECD_CS   0x00000002 /* NVM Chip Select */
#define	E1000_EECD_DI   0x00000004 /* NVM Data In */
#define	E1000_EECD_DO   0x00000008 /* NVM Data Out */
#define	E1000_EECD_REQ   0x00000040 /* NVM Access Request */
#define	E1000_EECD_GNT   0x00000080 /* NVM Access Grant */
#define	E1000_EECD_PRES   0x00000100 /* NVM Present */
#define	E1000_EECD_SIZE   0x00000200 /* NVM Size (0=64 word 1=256 word) */
#define	E1000_EECD_ADDR_BITS   0x00000400
#define	E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
#define	E1000_EECD_AUTO_RD   0x00000200 /* NVM Auto Read done */
#define	E1000_EECD_SIZE_EX_MASK   0x00007800 /* NVM Size */
#define	E1000_EECD_SIZE_EX_SHIFT   11
#define	E1000_EECD_FLUPD   0x00080000 /* Update FLASH */
#define	E1000_EECD_AUPDEN   0x00100000 /* Enable Autonomous FLASH update */
#define	E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
#define	E1000_EECD_SEC1VAL_VALID_MASK   (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
#define	E1000_NVM_RW_REG_DATA   16 /* Offset to data in NVM read/write registers */
#define	E1000_NVM_RW_REG_DONE   2 /* Offset to READ/WRITE done bit */
#define	E1000_NVM_RW_REG_START   1 /* Start operation */
#define	E1000_NVM_RW_ADDR_SHIFT   2 /* Shift to the address bits */
#define	E1000_NVM_POLL_WRITE   1 /* Flag for polling for write complete */
#define	E1000_NVM_POLL_READ   0 /* Flag for polling for read complete */
#define	E1000_FLASH_UPDATES   2000
#define	NVM_COMPAT   0x0003
#define	NVM_ID_LED_SETTINGS   0x0004
#define	NVM_INIT_CONTROL2_REG   0x000F
#define	NVM_INIT_CONTROL3_PORT_B   0x0014
#define	NVM_INIT_3GIO_3   0x001A
#define	NVM_INIT_CONTROL3_PORT_A   0x0024
#define	NVM_CFG   0x0012
#define	NVM_ALT_MAC_ADDR_PTR   0x0037
#define	NVM_CHECKSUM_REG   0x003F
#define	E1000_NVM_INIT_CTRL2_MNGM   0x6000 /* Manageability Operation Mode mask */
#define	E1000_NVM_CFG_DONE_PORT_0   0x40000 /* MNG config cycle done */
#define	E1000_NVM_CFG_DONE_PORT_1   0x80000 /* ...for second port */
#define	NVM_WORD0F_PAUSE_MASK   0x3000
#define	NVM_WORD0F_PAUSE   0x1000
#define	NVM_WORD0F_ASM_DIR   0x2000
#define	NVM_WORD1A_ASPM_MASK   0x000C
#define	NVM_COMPAT_LOM   0x0800
#define	E1000_PBANUM_LENGTH   11
#define	NVM_SUM   0xBABA
#define	NVM_PBA_OFFSET_0   8
#define	NVM_PBA_OFFSET_1   9
#define	NVM_PBA_PTR_GUARD   0xFAFA
#define	NVM_WORD_SIZE_BASE_SHIFT   6
#define	NVM_MAX_RETRY_SPI   5000 /* Max wait of 5ms, for RDY signal */
#define	NVM_READ_OPCODE_SPI   0x03 /* NVM read opcode */
#define	NVM_WRITE_OPCODE_SPI   0x02 /* NVM write opcode */
#define	NVM_A8_OPCODE_SPI   0x08 /* opcode bit-3 = address bit-8 */
#define	NVM_WREN_OPCODE_SPI   0x06 /* NVM set Write Enable latch */
#define	NVM_RDSR_OPCODE_SPI   0x05 /* NVM read Status register */
#define	NVM_STATUS_RDY_SPI   0x01
#define	ID_LED_RESERVED_0000   0x0000
#define	ID_LED_RESERVED_FFFF   0xFFFF
#define	ID_LED_DEFAULT
#define	ID_LED_DEF1_DEF2   0x1
#define	ID_LED_DEF1_ON2   0x2
#define	ID_LED_DEF1_OFF2   0x3
#define	ID_LED_ON1_DEF2   0x4
#define	ID_LED_ON1_ON2   0x5
#define	ID_LED_ON1_OFF2   0x6
#define	ID_LED_OFF1_DEF2   0x7
#define	ID_LED_OFF1_ON2   0x8
#define	ID_LED_OFF1_OFF2   0x9
#define	IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
#define	IGP_ACTIVITY_LED_ENABLE   0x0300
#define	IGP_LED3_MODE   0x07000000
#define	PCI_HEADER_TYPE_REGISTER   0x0E
#define	PCIE_LINK_STATUS   0x12
#define	PCI_HEADER_TYPE_MULTIFUNC   0x80
#define	PCIE_LINK_WIDTH_MASK   0x3F0
#define	PCIE_LINK_WIDTH_SHIFT   4
#define	PHY_REVISION_MASK   0xFFFFFFF0
#define	MAX_PHY_REG_ADDRESS   0x1F /* 5 bit address bus (0-0x1F) */
#define	MAX_PHY_MULTI_PAGE_REG   0xF
#define	M88E1000_E_PHY_ID   0x01410C50
#define	M88E1000_I_PHY_ID   0x01410C30
#define	M88E1011_I_PHY_ID   0x01410C20
#define	IGP01E1000_I_PHY_ID   0x02A80380
#define	M88E1111_I_PHY_ID   0x01410CC0
#define	GG82563_E_PHY_ID   0x01410CA0
#define	IGP03E1000_E_PHY_ID   0x02A80390
#define	IFE_E_PHY_ID   0x02A80330
#define	IFE_PLUS_E_PHY_ID   0x02A80320
#define	IFE_C_E_PHY_ID   0x02A80310
#define	BME1000_E_PHY_ID   0x01410CB0
#define	BME1000_E_PHY_ID_R2   0x01410CB1
#define	I82577_E_PHY_ID   0x01540050
#define	I82578_E_PHY_ID   0x004DD040
#define	I82579_E_PHY_ID   0x01540090
#define	I217_E_PHY_ID   0x015400A0
#define	M88E1000_PHY_SPEC_CTRL   0x10 /* PHY Specific Control Register */
#define	M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */
#define	M88E1000_EXT_PHY_SPEC_CTRL   0x14 /* Extended PHY Specific Control */
#define	M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */
#define	M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */
#define	M88E1000_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reversal enabled */
#define	M88E1000_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */
#define	M88E1000_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */
#define	M88E1000_PSCR_AUTO_X_1000T   0x0040
#define	M88E1000_PSCR_AUTO_X_MODE   0x0060
#define	M88E1000_PSCR_ASSERT_CRS_ON_TX   0x0800 /* 1=Assert CRS on Transmit */
#define	M88E1000_PSSR_REV_POLARITY   0x0002 /* 1=Polarity reversed */
#define	M88E1000_PSSR_DOWNSHIFT   0x0020 /* 1=Downshifted */
#define	M88E1000_PSSR_MDIX   0x0040 /* 1=MDIX; 0=MDI */
#define	M88E1000_PSSR_CABLE_LENGTH   0x0380
#define	M88E1000_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */
#define	M88E1000_PSSR_1000MBS   0x8000 /* 10=1000Mbs */
#define	M88E1000_PSSR_CABLE_LENGTH_SHIFT   7
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK   0x0C00
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK   0x0300
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X   0x0100
#define	M88E1000_EPSCR_TX_CLK_25   0x0070 /* 25 MHz TX_CLK */
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK   0x0E00
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X   0x0800
#define	I82578_EPSCR_DOWNSHIFT_ENABLE   0x0020
#define	I82578_EPSCR_DOWNSHIFT_COUNTER_MASK   0x001C
#define	BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
#define	PHY_PAGE_SHIFT   5
#define	PHY_REG(page, reg)
#define	GG82563_PAGE_SHIFT   5
#define	GG82563_REG(page, reg)   (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
#define	GG82563_MIN_ALT_REG   30
#define	GG82563_PHY_SPEC_CTRL   GG82563_REG(0, 16) /* PHY Specific Control */
#define	GG82563_PHY_PAGE_SELECT   GG82563_REG(0, 22) /* Page Select */
#define	GG82563_PHY_SPEC_CTRL_2   GG82563_REG(0, 26) /* PHY Specific Control 2 */
#define	GG82563_PHY_PAGE_SELECT_ALT   GG82563_REG(0, 29) /* Alternate Page Select */
#define	GG82563_PHY_MAC_SPEC_CTRL   GG82563_REG(2, 21) /* MAC Specific Control Register */
#define	GG82563_PHY_DSP_DISTANCE   GG82563_REG(5, 26) /* DSP Distance */
#define	GG82563_PHY_KMRN_MODE_CTRL   GG82563_REG(193, 16) /* Kumeran Mode Control */
#define	GG82563_PHY_PWR_MGMT_CTRL   GG82563_REG(193, 20) /* Power Management Control */
#define	GG82563_PHY_INBAND_CTRL   GG82563_REG(194, 18) /* Inband Control */
#define	E1000_MDIC_REG_SHIFT   16
#define	E1000_MDIC_PHY_SHIFT   21
#define	E1000_MDIC_OP_WRITE   0x04000000
#define	E1000_MDIC_OP_READ   0x08000000
#define	E1000_MDIC_READY   0x10000000
#define	E1000_MDIC_ERROR   0x40000000
#define	E1000_GEN_POLL_TIMEOUT   640
#define	E1000_FWSM_WLOCK_MAC_MASK   0x0380
#define	E1000_FWSM_WLOCK_MAC_SHIFT   7

Macro Definition Documentation

#define ADVERTISE_1000_FULL   0x0020

Definition at line 275 of file defines.h.

#define ADVERTISE_1000_HALF   0x0010 /* Not used, just FYI */

Definition at line 274 of file defines.h.

#define ADVERTISE_100_FULL   0x0008

Definition at line 273 of file defines.h.

#define ADVERTISE_100_HALF   0x0004

Definition at line 272 of file defines.h.

#define ADVERTISE_10_FULL   0x0002

Definition at line 271 of file defines.h.

#define ADVERTISE_10_HALF   0x0001

Definition at line 270 of file defines.h.

#define AUTO_READ_DONE_TIMEOUT   10

Definition at line 520 of file defines.h.

#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX

Definition at line 287 of file defines.h.

#define BME1000_E_PHY_ID   0x01410CB0

Definition at line 741 of file defines.h.

#define BME1000_E_PHY_ID_R2   0x01410CB1

Definition at line 742 of file defines.h.

#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */

Definition at line 804 of file defines.h.

#define COPPER_LINK_UP_LIMIT   10

Definition at line 510 of file defines.h.

#define CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */

Definition at line 588 of file defines.h.

#define CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */

Definition at line 587 of file defines.h.

#define CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */

Definition at line 592 of file defines.h.

#define CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */

Definition at line 590 of file defines.h.

#define DEFAULT_80003ES2LAN_TIPG_IPGR2   7

Definition at line 365 of file defines.h.

#define DEFAULT_82543_TIPG_IPGR1   8

Definition at line 361 of file defines.h.

#define DEFAULT_82543_TIPG_IPGR2   6

Definition at line 364 of file defines.h.

#define DEFAULT_82543_TIPG_IPGT_COPPER   8

Definition at line 357 of file defines.h.

#define E1000_ALL_100_SPEED   (ADVERTISE_100_HALF | ADVERTISE_100_FULL)

Definition at line 283 of file defines.h.

#define E1000_ALL_10_SPEED   (ADVERTISE_10_HALF | ADVERTISE_10_FULL)

Definition at line 284 of file defines.h.

#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)

Definition at line 285 of file defines.h.

#define E1000_ALL_NOT_GIG

Value:

( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
                ADVERTISE_100_HALF |  ADVERTISE_100_FULL)

Definition at line 281 of file defines.h.

#define E1000_ALL_SPEED_DUPLEX

Value:

( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
                ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
                             ADVERTISE_1000_FULL)

Definition at line 278 of file defines.h.

#define E1000_BLK_PHY_RESET   12

Definition at line 501 of file defines.h.

#define E1000_COLD_SHIFT   12

Definition at line 354 of file defines.h.

#define E1000_COLLISION_DISTANCE   63

Definition at line 353 of file defines.h.

#define E1000_COLLISION_THRESHOLD   15

Definition at line 351 of file defines.h.

#define E1000_CT_SHIFT   4

Definition at line 352 of file defines.h.

#define E1000_CTRL_ASDE   0x00000020 /* Auto-speed detect enable */

Definition at line 225 of file defines.h.

#define E1000_CTRL_EXT_DMA_DYN_CLK_EN   0x00080000 /* DMA Dynamic Clock Gating */

Definition at line 83 of file defines.h.

#define E1000_CTRL_EXT_DRV_LOAD   0x10000000 /* Driver loaded bit for FW */

Definition at line 87 of file defines.h.

#define E1000_CTRL_EXT_EE_RST   0x00002000 /* Reinitialize from EEPROM */

Definition at line 80 of file defines.h.

#define E1000_CTRL_EXT_EIAME   0x01000000

Definition at line 86 of file defines.h.

#define E1000_CTRL_EXT_FORCE_SMBUS   0x00000800 /* Force SMBus mode */

Definition at line 79 of file defines.h.

#define E1000_CTRL_EXT_IAME   0x08000000 /* Interrupt acknowledge Auto-mask */

Definition at line 88 of file defines.h.

#define E1000_CTRL_EXT_INT_TIMER_CLR   0x20000000 /* Clear Interrupt timers after IMS clear */

Definition at line 89 of file defines.h.

#define E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000

Definition at line 84 of file defines.h.

#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES   0x00C00000

Definition at line 85 of file defines.h.

#define E1000_CTRL_EXT_LPCD   0x00000004 /* LCD Power Cycle Done */

Definition at line 77 of file defines.h.

#define E1000_CTRL_EXT_LSECCK   0x00001000

Definition at line 91 of file defines.h.

#define E1000_CTRL_EXT_PBA_CLR   0x80000000 /* PBA Clear */

Definition at line 90 of file defines.h.

#define E1000_CTRL_EXT_PHYPDEN   0x00100000

Definition at line 92 of file defines.h.

#define E1000_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */

Definition at line 82 of file defines.h.

#define E1000_CTRL_EXT_SDP3_DATA   0x00000080 /* Value of SW Definable Pin 3 */

Definition at line 78 of file defines.h.

#define E1000_CTRL_EXT_SPD_BYPS   0x00008000 /* Speed Select Bypass */

Definition at line 81 of file defines.h.

#define E1000_CTRL_FD   0x00000001 /* Full duplex.0=half; 1=full */

Definition at line 222 of file defines.h.

#define E1000_CTRL_FRCDPX   0x00001000 /* Force Duplex */

Definition at line 233 of file defines.h.

#define E1000_CTRL_FRCSPD   0x00000800 /* Force Speed */

Definition at line 232 of file defines.h.

#define E1000_CTRL_GIO_MASTER_DISABLE   0x00000004 /*Blocks new Master requests */

Definition at line 223 of file defines.h.

#define E1000_CTRL_ILOS   0x00000080 /* Invert Loss-Of Signal */

Definition at line 227 of file defines.h.

#define E1000_CTRL_LANPHYPC_OVERRIDE   0x00010000 /* SW control of LANPHYPC */

Definition at line 234 of file defines.h.

#define E1000_CTRL_LANPHYPC_VALUE   0x00020000 /* SW value of LANPHYPC */

Definition at line 235 of file defines.h.

#define E1000_CTRL_LRST   0x00000008 /* Link reset. 0=normal,1=reset */

Definition at line 224 of file defines.h.

#define E1000_CTRL_PHY_RST   0x80000000 /* PHY Reset */

Definition at line 243 of file defines.h.

#define E1000_CTRL_RFCE   0x08000000 /* Receive Flow Control enable */

Definition at line 240 of file defines.h.

#define E1000_CTRL_RST   0x04000000 /* Global reset */

Definition at line 239 of file defines.h.

#define E1000_CTRL_SLU   0x00000040 /* Set link up (Force Link) */

Definition at line 226 of file defines.h.

#define E1000_CTRL_SPD_10   0x00000000 /* Force 10Mb */

Definition at line 229 of file defines.h.

#define E1000_CTRL_SPD_100   0x00000100 /* Force 100Mb */

Definition at line 230 of file defines.h.

#define E1000_CTRL_SPD_1000   0x00000200 /* Force 1Gb */

Definition at line 231 of file defines.h.

#define E1000_CTRL_SPD_SEL   0x00000300 /* Speed Select Mask */

Definition at line 228 of file defines.h.

#define E1000_CTRL_SWDPIN0   0x00040000 /* SWDPIN 0 value */

Definition at line 236 of file defines.h.

#define E1000_CTRL_SWDPIN1   0x00080000 /* SWDPIN 1 value */

Definition at line 237 of file defines.h.

#define E1000_CTRL_SWDPIO0   0x00400000 /* SWDPIN 0 Input or output */

Definition at line 238 of file defines.h.

#define E1000_CTRL_TFCE   0x10000000 /* Transmit flow control enable */

Definition at line 241 of file defines.h.

#define E1000_CTRL_VME   0x40000000 /* IEEE VLAN mode enable */

Definition at line 242 of file defines.h.

#define E1000_EECD_ADDR_BITS   0x00000400

Definition at line 625 of file defines.h.

#define E1000_EECD_AUPDEN   0x00100000 /* Enable Autonomous FLASH update */

Definition at line 631 of file defines.h.

#define E1000_EECD_AUTO_RD   0x00000200 /* NVM Auto Read done */

Definition at line 627 of file defines.h.

#define E1000_EECD_CS   0x00000002 /* NVM Chip Select */

Definition at line 617 of file defines.h.

#define E1000_EECD_DI   0x00000004 /* NVM Data In */

Definition at line 618 of file defines.h.

#define E1000_EECD_DO   0x00000008 /* NVM Data Out */

Definition at line 619 of file defines.h.

#define E1000_EECD_FLUPD   0x00080000 /* Update FLASH */

Definition at line 630 of file defines.h.

#define E1000_EECD_GNT   0x00000080 /* NVM Access Grant */

Definition at line 621 of file defines.h.

#define E1000_EECD_PRES   0x00000100 /* NVM Present */

Definition at line 622 of file defines.h.

#define E1000_EECD_REQ   0x00000040 /* NVM Access Request */

Definition at line 620 of file defines.h.

#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */

Definition at line 632 of file defines.h.

#define E1000_EECD_SEC1VAL_VALID_MASK   (E1000_EECD_AUTO_RD | E1000_EECD_PRES)

Definition at line 633 of file defines.h.

#define E1000_EECD_SIZE   0x00000200 /* NVM Size (0=64 word 1=256 word) */

Definition at line 623 of file defines.h.

#define E1000_EECD_SIZE_EX_MASK   0x00007800 /* NVM Size */

Definition at line 628 of file defines.h.

#define E1000_EECD_SIZE_EX_SHIFT   11

Definition at line 629 of file defines.h.

#define E1000_EECD_SK   0x00000001 /* NVM Clock */

Definition at line 616 of file defines.h.

#define E1000_ERR_CONFIG   3

Definition at line 494 of file defines.h.

#define E1000_ERR_HOST_INTERFACE_COMMAND   11

Definition at line 500 of file defines.h.

#define E1000_ERR_INVALID_ARGUMENT   16

Definition at line 504 of file defines.h.

#define E1000_ERR_MAC_INIT   5

Definition at line 496 of file defines.h.

#define E1000_ERR_MASTER_REQUESTS_PENDING   10

Definition at line 499 of file defines.h.

#define E1000_ERR_NO_SPACE   17

Definition at line 505 of file defines.h.

#define E1000_ERR_NVM   1

Definition at line 492 of file defines.h.

#define E1000_ERR_NVM_PBA_SECTION   18

Definition at line 506 of file defines.h.

#define E1000_ERR_PARAM   4

Definition at line 495 of file defines.h.

#define E1000_ERR_PHY   2

Definition at line 493 of file defines.h.

#define E1000_ERR_PHY_TYPE   6

Definition at line 497 of file defines.h.

#define E1000_ERR_RESET   9

Definition at line 498 of file defines.h.

#define E1000_ERR_SWFW_SYNC   13

Definition at line 502 of file defines.h.

#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000

Definition at line 378 of file defines.h.

#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT   16

Definition at line 379 of file defines.h.

#define E1000_EXTCNF_CTRL_GATE_PHY_CFG   0x00000080

Definition at line 375 of file defines.h.

#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE   0x00000001

Definition at line 372 of file defines.h.

#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP   0x00000020

Definition at line 371 of file defines.h.

#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE   0x00000008

Definition at line 373 of file defines.h.

#define E1000_EXTCNF_CTRL_SWFLAG   0x00000020

Definition at line 374 of file defines.h.

#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000

Definition at line 376 of file defines.h.

#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT   16

Definition at line 377 of file defines.h.

#define E1000_FCRTH_RTH   0x0000FFF8 /* Mask Bits[15:3] for RTH */

Definition at line 523 of file defines.h.

#define E1000_FCRTL_RTL   0x0000FFF8 /* Mask Bits[15:3] for RTL */

Definition at line 524 of file defines.h.

#define E1000_FCRTL_XONE   0x80000000 /* Enable XON frame transmission */

Definition at line 525 of file defines.h.

#define E1000_FLASH_UPDATES   2000

Definition at line 641 of file defines.h.

#define E1000_FWSM_WLOCK_MAC_MASK   0x0380

Definition at line 859 of file defines.h.

#define E1000_FWSM_WLOCK_MAC_SHIFT   7

Definition at line 860 of file defines.h.

#define E1000_GCR_RXD_NO_SNOOP   0x00000001

Definition at line 541 of file defines.h.

#define E1000_GCR_RXDSCR_NO_SNOOP   0x00000004

Definition at line 543 of file defines.h.

#define E1000_GCR_RXDSCW_NO_SNOOP   0x00000002

Definition at line 542 of file defines.h.

#define E1000_GCR_TXD_NO_SNOOP   0x00000008

Definition at line 544 of file defines.h.

#define E1000_GCR_TXDSCR_NO_SNOOP   0x00000020

Definition at line 546 of file defines.h.

#define E1000_GCR_TXDSCW_NO_SNOOP   0x00000010

Definition at line 545 of file defines.h.

#define E1000_GEN_POLL_TIMEOUT   640

Definition at line 856 of file defines.h.

#define E1000_ICR_INT_ASSERTED   0x80000000 /* If this bit asserted, the driver should claim the interrupt */

Definition at line 413 of file defines.h.

#define E1000_ICR_LSC   0x00000004 /* Link Status Change */

Definition at line 409 of file defines.h.

#define E1000_ICR_OTHER   0x01000000 /* Other Interrupts */

Definition at line 418 of file defines.h.

#define E1000_ICR_RXDMT0   0x00000010 /* Rx desc min. threshold (0) */

Definition at line 411 of file defines.h.

#define E1000_ICR_RXQ0   0x00100000 /* Rx Queue 0 Interrupt */

Definition at line 414 of file defines.h.

#define E1000_ICR_RXQ1   0x00200000 /* Rx Queue 1 Interrupt */

Definition at line 415 of file defines.h.

#define E1000_ICR_RXSEQ   0x00000008 /* Rx sequence error */

Definition at line 410 of file defines.h.

#define E1000_ICR_RXT0   0x00000080 /* Rx timer intr (ring 0) */

Definition at line 412 of file defines.h.

#define E1000_ICR_TXDW   0x00000001 /* Transmit desc written back */

Definition at line 408 of file defines.h.

#define E1000_ICR_TXQ0   0x00400000 /* Tx Queue 0 Interrupt */

Definition at line 416 of file defines.h.

#define E1000_ICR_TXQ1   0x00800000 /* Tx Queue 1 Interrupt */

Definition at line 417 of file defines.h.

#define E1000_ICS_LSC   E1000_ICR_LSC /* Link Status Change */

Definition at line 456 of file defines.h.

#define E1000_ICS_RXDMT0   E1000_ICR_RXDMT0 /* Rx desc min. threshold */

Definition at line 458 of file defines.h.

#define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ /* Rx sequence error */

Definition at line 457 of file defines.h.

#define E1000_IMS_LSC   E1000_ICR_LSC /* Link Status Change */

Definition at line 445 of file defines.h.

#define E1000_IMS_OTHER   E1000_ICR_OTHER /* Other Interrupts */

Definition at line 453 of file defines.h.

#define E1000_IMS_RXDMT0   E1000_ICR_RXDMT0 /* Rx desc min. threshold */

Definition at line 447 of file defines.h.

#define E1000_IMS_RXQ0   E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */

Definition at line 449 of file defines.h.

#define E1000_IMS_RXQ1   E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */

Definition at line 450 of file defines.h.

#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ /* Rx sequence error */

Definition at line 446 of file defines.h.

#define E1000_IMS_RXT0   E1000_ICR_RXT0 /* Rx timer intr */

Definition at line 448 of file defines.h.

#define E1000_IMS_TXDW   E1000_ICR_TXDW /* Transmit desc written back */

Definition at line 444 of file defines.h.

#define E1000_IMS_TXQ0   E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */

Definition at line 451 of file defines.h.

#define E1000_IMS_TXQ1   E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */

Definition at line 452 of file defines.h.

#define E1000_KABGTXD_BGSQLBIAS   0x00050000

Definition at line 386 of file defines.h.

#define E1000_LEDCTL_LED0_BLINK   0x00000080

Definition at line 297 of file defines.h.

#define E1000_LEDCTL_LED0_IVRT   0x00000040

Definition at line 296 of file defines.h.

#define E1000_LEDCTL_LED0_MODE_MASK   0x0000000F

Definition at line 294 of file defines.h.

#define E1000_LEDCTL_LED0_MODE_SHIFT   0

Definition at line 295 of file defines.h.

#define E1000_LEDCTL_MODE_LED_OFF   0xF

Definition at line 301 of file defines.h.

#define E1000_LEDCTL_MODE_LED_ON   0xE

Definition at line 300 of file defines.h.

#define E1000_LEDCTL_MODE_LINK_UP   0x2

Definition at line 299 of file defines.h.

#define E1000_MANC2H_PORT_623   0x00000020 /* Port 0x26f */

Definition at line 152 of file defines.h.

#define E1000_MANC2H_PORT_664   0x00000040 /* Port 0x298 */

Definition at line 153 of file defines.h.

#define E1000_MANC_ARP_EN   0x00002000 /* Enable ARP Request Filtering */

Definition at line 144 of file defines.h.

#define E1000_MANC_ASF_EN   0x00000002 /* ASF Enabled - RO */

Definition at line 143 of file defines.h.

#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */

Definition at line 146 of file defines.h.

#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000

Definition at line 148 of file defines.h.

#define E1000_MANC_EN_MNG2HOST   0x00200000

Definition at line 150 of file defines.h.

#define E1000_MANC_RCV_TCO_EN   0x00020000 /* Receive TCO Packets Enabled */

Definition at line 145 of file defines.h.

#define E1000_MANC_SMBUS_EN   0x00000001 /* SMBus Enabled - RO */

Definition at line 142 of file defines.h.

#define E1000_MDEF_PORT_623   0x00000800 /* Port 0x26f */

Definition at line 154 of file defines.h.

#define E1000_MDEF_PORT_664   0x00000400 /* Port 0x298 */

Definition at line 155 of file defines.h.

#define E1000_MDIC_ERROR   0x40000000

Definition at line 853 of file defines.h.

#define E1000_MDIC_OP_READ   0x08000000

Definition at line 851 of file defines.h.

#define E1000_MDIC_OP_WRITE   0x04000000

Definition at line 850 of file defines.h.

#define E1000_MDIC_PHY_SHIFT   21

Definition at line 849 of file defines.h.

#define E1000_MDIC_READY   0x10000000

Definition at line 852 of file defines.h.

#define E1000_MDIC_REG_SHIFT   16

Definition at line 848 of file defines.h.

#define E1000_MRQC_RSS_FIELD_IPV4   0x00020000

Definition at line 134 of file defines.h.

#define E1000_MRQC_RSS_FIELD_IPV4_TCP   0x00010000

Definition at line 133 of file defines.h.

#define E1000_MRQC_RSS_FIELD_IPV6   0x00100000

Definition at line 136 of file defines.h.

#define E1000_MRQC_RSS_FIELD_IPV6_TCP   0x00200000

Definition at line 137 of file defines.h.

#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX   0x00040000

Definition at line 135 of file defines.h.

#define E1000_MRQC_RSS_FIELD_MASK   0xFFFF0000

Definition at line 132 of file defines.h.

#define E1000_NOT_IMPLEMENTED   14

Definition at line 503 of file defines.h.

#define E1000_NVM_CFG_DONE_PORT_0   0x40000 /* MNG config cycle done */

Definition at line 656 of file defines.h.

#define E1000_NVM_CFG_DONE_PORT_1   0x80000 /* ...for second port */

Definition at line 657 of file defines.h.

#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */

Definition at line 626 of file defines.h.

#define E1000_NVM_INIT_CTRL2_MNGM   0x6000 /* Manageability Operation Mode mask */

Definition at line 654 of file defines.h.

#define E1000_NVM_POLL_READ   0 /* Flag for polling for read complete */

Definition at line 640 of file defines.h.

#define E1000_NVM_POLL_WRITE   1 /* Flag for polling for write complete */

Definition at line 639 of file defines.h.

#define E1000_NVM_RW_ADDR_SHIFT   2 /* Shift to the address bits */

Definition at line 638 of file defines.h.

#define E1000_NVM_RW_REG_DATA   16 /* Offset to data in NVM read/write registers */

Definition at line 635 of file defines.h.

#define E1000_NVM_RW_REG_DONE   2 /* Offset to READ/WRITE done bit */

Definition at line 636 of file defines.h.

#define E1000_NVM_RW_REG_START   1 /* Start operation */

Definition at line 637 of file defines.h.

#define E1000_PBA_16K   0x0010 /* 16KB */

Definition at line 390 of file defines.h.

#define E1000_PBA_8K   0x0008 /* 8KB */

Definition at line 389 of file defines.h.

#define E1000_PBA_ECC_CORR_EN   0x00000001 /* ECC correction enable */

Definition at line 423 of file defines.h.

#define E1000_PBA_ECC_COUNTER_MASK   0xFFF00000 /* ECC counter mask */

Definition at line 421 of file defines.h.

#define E1000_PBA_ECC_COUNTER_SHIFT   20 /* ECC counter shift value */

Definition at line 422 of file defines.h.

#define E1000_PBA_ECC_INT_EN   0x00000004 /* Enable ICR bit 5 for ECC */

Definition at line 425 of file defines.h.

#define E1000_PBA_ECC_STAT_CLR   0x00000002 /* Clear ECC error counter */

Definition at line 424 of file defines.h.

#define E1000_PBANUM_LENGTH   11

Definition at line 671 of file defines.h.

#define E1000_PBS_16K   E1000_PBA_16K

Definition at line 392 of file defines.h.

#define E1000_PHY_CTRL_D0A_LPLU   0x00000002

Definition at line 381 of file defines.h.

#define E1000_PHY_CTRL_GBE_DISABLE   0x00000040

Definition at line 384 of file defines.h.

#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE   0x00000008

Definition at line 383 of file defines.h.

#define E1000_PHY_CTRL_NOND0A_LPLU   0x00000004

Definition at line 382 of file defines.h.

#define E1000_PHY_LED0_IVRT   0x00000008

Definition at line 291 of file defines.h.

#define E1000_PHY_LED0_MASK   0x0000001F

Definition at line 292 of file defines.h.

#define E1000_PHY_LED0_MODE_MASK   0x00000007

Definition at line 290 of file defines.h.

#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F

Definition at line 205 of file defines.h.

#define E1000_PSRCTL_BSIZE0_SHIFT   7 /* Shift _right_ 7 */

Definition at line 210 of file defines.h.

#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00

Definition at line 206 of file defines.h.

#define E1000_PSRCTL_BSIZE1_SHIFT   2 /* Shift _right_ 2 */

Definition at line 211 of file defines.h.

#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000

Definition at line 207 of file defines.h.

#define E1000_PSRCTL_BSIZE2_SHIFT   6 /* Shift _left_ 6 */

Definition at line 212 of file defines.h.

#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000

Definition at line 208 of file defines.h.

#define E1000_PSRCTL_BSIZE3_SHIFT   14 /* Shift _left_ 14 */

Definition at line 213 of file defines.h.

#define E1000_RAH_AV   0x80000000 /* Receive descriptor valid */

Definition at line 487 of file defines.h.

#define E1000_RAH_MAC_ADDR_LEN   2

Definition at line 489 of file defines.h.

#define E1000_RAL_MAC_ADDR_LEN   4

Definition at line 488 of file defines.h.

#define E1000_RAR_ENTRIES   15

Definition at line 486 of file defines.h.

#define E1000_RCTL_BAM   0x00008000 /* broadcast enable */

Definition at line 170 of file defines.h.

#define E1000_RCTL_BSEX   0x02000000 /* Buffer size extension */

Definition at line 185 of file defines.h.

#define E1000_RCTL_CFI   0x00100000 /* canonical form indicator */

Definition at line 182 of file defines.h.

#define E1000_RCTL_CFIEN   0x00080000 /* canonical form enable */

Definition at line 181 of file defines.h.

#define E1000_RCTL_DPF   0x00400000 /* Discard Pause Frames */

Definition at line 183 of file defines.h.

#define E1000_RCTL_DTYP_PS   0x00000400 /* Packet Split descriptor */

Definition at line 166 of file defines.h.

#define E1000_RCTL_EN   0x00000002 /* enable */

Definition at line 158 of file defines.h.

#define E1000_RCTL_LBM_MAC   0x00000040 /* MAC loopback mode */

Definition at line 164 of file defines.h.

#define E1000_RCTL_LBM_NO   0x00000000 /* no loopback mode */

Definition at line 163 of file defines.h.

#define E1000_RCTL_LBM_TCVR   0x000000C0 /* tcvr loopback mode */

Definition at line 165 of file defines.h.

#define E1000_RCTL_LPE   0x00000020 /* long packet enable */

Definition at line 162 of file defines.h.

#define E1000_RCTL_MO_3   0x00003000 /* multicast offset 15:4 */

Definition at line 169 of file defines.h.

#define E1000_RCTL_MO_SHIFT   12 /* multicast offset shift */

Definition at line 168 of file defines.h.

#define E1000_RCTL_MPE   0x00000010 /* multicast promiscuous enab */

Definition at line 161 of file defines.h.

#define E1000_RCTL_PMCF   0x00800000 /* pass MAC control frames */

Definition at line 184 of file defines.h.

#define E1000_RCTL_RDMTS_HALF   0x00000000 /* Rx desc min threshold size */

Definition at line 167 of file defines.h.

#define E1000_RCTL_SBP   0x00000004 /* store bad packet */

Definition at line 159 of file defines.h.

#define E1000_RCTL_SECRC   0x04000000 /* Strip Ethernet CRC */

Definition at line 186 of file defines.h.

#define E1000_RCTL_SZ_1024   0x00010000 /* Rx buffer size 1024 */

Definition at line 173 of file defines.h.

#define E1000_RCTL_SZ_16384   0x00010000 /* Rx buffer size 16384 */

Definition at line 177 of file defines.h.

#define E1000_RCTL_SZ_2048   0x00000000 /* Rx buffer size 2048 */

Definition at line 172 of file defines.h.

#define E1000_RCTL_SZ_256   0x00030000 /* Rx buffer size 256 */

Definition at line 175 of file defines.h.

#define E1000_RCTL_SZ_4096   0x00030000 /* Rx buffer size 4096 */

Definition at line 179 of file defines.h.

#define E1000_RCTL_SZ_512   0x00020000 /* Rx buffer size 512 */

Definition at line 174 of file defines.h.

#define E1000_RCTL_SZ_8192   0x00020000 /* Rx buffer size 8192 */

Definition at line 178 of file defines.h.

#define E1000_RCTL_UPE   0x00000008 /* unicast promiscuous enable */

Definition at line 160 of file defines.h.

#define E1000_RCTL_VFE   0x00040000 /* vlan filter enable */

Definition at line 180 of file defines.h.

#define E1000_RFCTL_ACK_DIS   0x00001000

Definition at line 345 of file defines.h.

#define E1000_RFCTL_EXTEN   0x00008000

Definition at line 346 of file defines.h.

#define E1000_RFCTL_IPV6_EX_DIS   0x00010000

Definition at line 347 of file defines.h.

#define E1000_RFCTL_NEW_IPV6_EXT_DIS   0x00020000

Definition at line 348 of file defines.h.

#define E1000_RFCTL_NFSR_DIS   0x00000080

Definition at line 344 of file defines.h.

#define E1000_RFCTL_NFSW_DIS   0x00000040

Definition at line 343 of file defines.h.

#define E1000_RXCSUM_IPPCSE   0x00001000 /* IP payload checksum enable */

Definition at line 339 of file defines.h.

#define E1000_RXCSUM_PCSD   0x00002000 /* packet checksum disabled */

Definition at line 340 of file defines.h.

#define E1000_RXCSUM_TUOFL   0x00000200 /* TCP / UDP checksum offload */

Definition at line 338 of file defines.h.

#define E1000_RXCW_C   0x20000000 /* Receive config */

Definition at line 537 of file defines.h.

#define E1000_RXCW_CW   0x0000ffff /* RxConfigWord mask */

Definition at line 535 of file defines.h.

#define E1000_RXCW_IV   0x08000000 /* Receive config invalid */

Definition at line 536 of file defines.h.

#define E1000_RXCW_SYNCH   0x40000000 /* Receive config synch */

Definition at line 538 of file defines.h.

#define E1000_RXD_ERR_CE   0x01 /* CRC Error */

Definition at line 101 of file defines.h.

#define E1000_RXD_ERR_CXE   0x10 /* Carrier Extension Error */

Definition at line 104 of file defines.h.

#define E1000_RXD_ERR_FRAME_ERR_MASK

Value:

( \
    E1000_RXD_ERR_CE  |                \
    E1000_RXD_ERR_SE  |                \
    E1000_RXD_ERR_SEQ |                \
    E1000_RXD_ERR_CXE |                \
    E1000_RXD_ERR_RXE)

Definition at line 117 of file defines.h.

#define E1000_RXD_ERR_IPE   0x40 /* IP Checksum Error */

Definition at line 106 of file defines.h.

#define E1000_RXD_ERR_RXE   0x80 /* Rx Data Error */

Definition at line 107 of file defines.h.

#define E1000_RXD_ERR_SE   0x02 /* Symbol Error */

Definition at line 102 of file defines.h.

#define E1000_RXD_ERR_SEQ   0x04 /* Sequence Error */

Definition at line 103 of file defines.h.

#define E1000_RXD_ERR_TCPE   0x20 /* TCP/UDP Checksum Error */

Definition at line 105 of file defines.h.

#define E1000_RXD_SPC_VLAN_MASK   0x0FFF /* VLAN ID is in lower 12 bits */

Definition at line 108 of file defines.h.

#define E1000_RXD_STAT_DD   0x01 /* Descriptor Done */

Definition at line 95 of file defines.h.

#define E1000_RXD_STAT_EOP   0x02 /* End of Packet */

Definition at line 96 of file defines.h.

#define E1000_RXD_STAT_IXSM   0x04 /* Ignore checksum */

Definition at line 97 of file defines.h.

#define E1000_RXD_STAT_TCPCS   0x20 /* TCP xsum calculated */

Definition at line 100 of file defines.h.

#define E1000_RXD_STAT_UDPCS   0x10 /* UDP xsum calculated */

Definition at line 99 of file defines.h.

#define E1000_RXD_STAT_VP   0x08 /* IEEE VLAN Packet */

Definition at line 98 of file defines.h.

#define E1000_RXDEXT_ERR_FRAME_ERR_MASK

Value:

( \
    E1000_RXDEXT_STATERR_CE  |            \
    E1000_RXDEXT_STATERR_SE  |            \
    E1000_RXDEXT_STATERR_SEQ |            \
    E1000_RXDEXT_STATERR_CXE |            \
    E1000_RXDEXT_STATERR_RXE)

Definition at line 125 of file defines.h.

#define E1000_RXDEXT_STATERR_CE   0x01000000

Definition at line 110 of file defines.h.

#define E1000_RXDEXT_STATERR_CXE   0x10000000

Definition at line 113 of file defines.h.

#define E1000_RXDEXT_STATERR_RXE   0x80000000

Definition at line 114 of file defines.h.

#define E1000_RXDEXT_STATERR_SE   0x02000000

Definition at line 111 of file defines.h.

#define E1000_RXDEXT_STATERR_SEQ   0x04000000

Definition at line 112 of file defines.h.

#define E1000_RXDPS_HDRSTAT_HDRSP   0x00008000

Definition at line 139 of file defines.h.

#define E1000_SCTL_DISABLE_SERDES_LOOPBACK   0x0400

Definition at line 335 of file defines.h.

#define E1000_STATUS_FD   0x00000001 /* Full duplex.0=half,1=full */

Definition at line 251 of file defines.h.

#define E1000_STATUS_FUNC_1   0x00000004 /* Function 1 */

Definition at line 255 of file defines.h.

#define E1000_STATUS_FUNC_MASK   0x0000000C /* PCI Function Mask */

Definition at line 253 of file defines.h.

#define E1000_STATUS_FUNC_SHIFT   2

Definition at line 254 of file defines.h.

#define E1000_STATUS_GIO_MASTER_ENABLE   0x00080000 /* Status of Master requests. */

Definition at line 262 of file defines.h.

#define E1000_STATUS_LAN_INIT_DONE   0x00000200 /* Lan Init Completion by NVM */

Definition at line 260 of file defines.h.

#define E1000_STATUS_LU   0x00000002 /* Link up.0=no,1=link */

Definition at line 252 of file defines.h.

#define E1000_STATUS_PHYRA   0x00000400 /* PHY Reset Asserted */

Definition at line 261 of file defines.h.

#define E1000_STATUS_SPEED_10   0x00000000 /* Speed 10Mb/s */

Definition at line 257 of file defines.h.

#define E1000_STATUS_SPEED_100   0x00000040 /* Speed 100Mb/s */

Definition at line 258 of file defines.h.

#define E1000_STATUS_SPEED_1000   0x00000080 /* Speed 1000Mb/s */

Definition at line 259 of file defines.h.

#define E1000_STATUS_TXOFF   0x00000010 /* transmission paused */

Definition at line 256 of file defines.h.

#define E1000_SWFW_CSR_SM   0x8

Definition at line 219 of file defines.h.

#define E1000_SWFW_EEP_SM   0x1

Definition at line 216 of file defines.h.

#define E1000_SWFW_PHY0_SM   0x2

Definition at line 217 of file defines.h.

#define E1000_SWFW_PHY1_SM   0x4

Definition at line 218 of file defines.h.

#define E1000_SWSM2_LOCK   0x00000002 /* Secondary driver semaphore bit */

Definition at line 405 of file defines.h.

#define E1000_SWSM_DRV_LOAD   0x00000008 /* Driver Loaded Bit */

Definition at line 403 of file defines.h.

#define E1000_SWSM_SMBI   0x00000001 /* Driver Semaphore bit */

Definition at line 401 of file defines.h.

#define E1000_SWSM_SWESMBI   0x00000002 /* FW Semaphore bit */

Definition at line 402 of file defines.h.

#define E1000_TCTL_COLD   0x003ff000 /* collision distance */

Definition at line 328 of file defines.h.

#define E1000_TCTL_CT   0x00000ff0 /* collision threshold */

Definition at line 327 of file defines.h.

#define E1000_TCTL_EN   0x00000002 /* enable Tx */

Definition at line 325 of file defines.h.

#define E1000_TCTL_MULR   0x10000000 /* Multiple request support */

Definition at line 330 of file defines.h.

#define E1000_TCTL_PSP   0x00000008 /* pad short packets */

Definition at line 326 of file defines.h.

#define E1000_TCTL_RTLC   0x01000000 /* Re-transmit on late collision */

Definition at line 329 of file defines.h.

#define E1000_TIPG_IPGR1_SHIFT   10

Definition at line 362 of file defines.h.

#define E1000_TIPG_IPGR2_SHIFT   20

Definition at line 366 of file defines.h.

#define E1000_TIPG_IPGT_MASK   0x000003FF

Definition at line 359 of file defines.h.

#define E1000_TXCW_ANE   0x80000000 /* Auto-neg enable */

Definition at line 532 of file defines.h.

#define E1000_TXCW_ASM_DIR   0x00000100 /* TXCW astm pause direction */

Definition at line 530 of file defines.h.

#define E1000_TXCW_FD   0x00000020 /* TXCW full duplex */

Definition at line 528 of file defines.h.

#define E1000_TXCW_PAUSE   0x00000080 /* TXCW sym pause request */

Definition at line 529 of file defines.h.

#define E1000_TXCW_PAUSE_MASK   0x00000180 /* TXCW pause request mask */

Definition at line 531 of file defines.h.

#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */

Definition at line 312 of file defines.h.

#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */

Definition at line 312 of file defines.h.

#define E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */

Definition at line 307 of file defines.h.

#define E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */

Definition at line 307 of file defines.h.

#define E1000_TXD_CMD_IC   0x04000000 /* Insert Checksum */

Definition at line 309 of file defines.h.

#define E1000_TXD_CMD_IC   0x04000000 /* Insert Checksum */

Definition at line 309 of file defines.h.

#define E1000_TXD_CMD_IDE   0x80000000 /* Enable Tidv register */

Definition at line 314 of file defines.h.

#define E1000_TXD_CMD_IDE   0x80000000 /* Enable Tidv register */

Definition at line 314 of file defines.h.

#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */

Definition at line 308 of file defines.h.

#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */

Definition at line 308 of file defines.h.

#define E1000_TXD_CMD_IP   0x02000000 /* IP packet */

Definition at line 320 of file defines.h.

#define E1000_TXD_CMD_IP   0x02000000 /* IP packet */

Definition at line 320 of file defines.h.

#define E1000_TXD_CMD_RPS   0x10000000 /* Report Packet Sent */

Definition at line 311 of file defines.h.

#define E1000_TXD_CMD_RPS   0x10000000 /* Report Packet Sent */

Definition at line 311 of file defines.h.

#define E1000_TXD_CMD_RS   0x08000000 /* Report Status */

Definition at line 310 of file defines.h.

#define E1000_TXD_CMD_RS   0x08000000 /* Report Status */

Definition at line 310 of file defines.h.

#define E1000_TXD_CMD_TCP   0x01000000 /* TCP packet */

Definition at line 319 of file defines.h.

#define E1000_TXD_CMD_TCP   0x01000000 /* TCP packet */

Definition at line 319 of file defines.h.

#define E1000_TXD_CMD_TSE   0x04000000 /* TCP Seg enable */

Definition at line 321 of file defines.h.

#define E1000_TXD_CMD_TSE   0x04000000 /* TCP Seg enable */

Definition at line 321 of file defines.h.

#define E1000_TXD_CMD_VLE   0x40000000 /* Add VLAN tag */

Definition at line 313 of file defines.h.

#define E1000_TXD_CMD_VLE   0x40000000 /* Add VLAN tag */

Definition at line 313 of file defines.h.

#define E1000_TXD_DTYP_D   0x00100000 /* Data Descriptor */

Definition at line 304 of file defines.h.

#define E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */

Definition at line 305 of file defines.h.

#define E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */

Definition at line 305 of file defines.h.

#define E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */

Definition at line 306 of file defines.h.

#define E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */

Definition at line 306 of file defines.h.

#define E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */

Definition at line 315 of file defines.h.

#define E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */

Definition at line 315 of file defines.h.

#define E1000_TXD_STAT_EC   0x00000002 /* Excess Collisions */

Definition at line 316 of file defines.h.

#define E1000_TXD_STAT_EC   0x00000002 /* Excess Collisions */

Definition at line 316 of file defines.h.

#define E1000_TXD_STAT_LC   0x00000004 /* Late Collisions */

Definition at line 317 of file defines.h.

#define E1000_TXD_STAT_LC   0x00000004 /* Late Collisions */

Definition at line 317 of file defines.h.

#define E1000_TXD_STAT_TC   0x00000004 /* Tx Underrun */

Definition at line 322 of file defines.h.

#define E1000_TXD_STAT_TC   0x00000004 /* Tx Underrun */

Definition at line 322 of file defines.h.

#define E1000_TXD_STAT_TU   0x00000008 /* Transmit underrun */

Definition at line 318 of file defines.h.

#define E1000_TXD_STAT_TU   0x00000008 /* Transmit underrun */

Definition at line 318 of file defines.h.

#define E1000_TXDCTL_COUNT_DESC   0x00400000

Definition at line 468 of file defines.h.

#define E1000_TXDCTL_FULL_TX_DESC_WB   0x01010000 /* GRAN=1, WTHRESH=1 */

Definition at line 465 of file defines.h.

#define E1000_TXDCTL_GRAN   0x01000000 /* TXDCTL Granularity */

Definition at line 464 of file defines.h.

#define E1000_TXDCTL_HTHRESH   0x00003F00 /* TXDCTL Host Threshold */

Definition at line 462 of file defines.h.

#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH   0x0100001F /* GRAN=1, PTHRESH=31 */

Definition at line 466 of file defines.h.

#define E1000_TXDCTL_PTHRESH   0x0000003F /* TXDCTL Prefetch Threshold */

Definition at line 461 of file defines.h.

#define E1000_TXDCTL_WTHRESH   0x003F0000 /* TXDCTL Writeback Threshold */

Definition at line 463 of file defines.h.

#define E1000_VLAN_FILTER_TBL_SIZE   128 /* VLAN Filter Table (4096 bits) */

Definition at line 476 of file defines.h.

#define E1000_WUC_APME   0x00000001 /* APM Enable */

Definition at line 57 of file defines.h.

#define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */

Definition at line 59 of file defines.h.

#define E1000_WUC_PME_EN   0x00000002 /* PME Enable */

Definition at line 58 of file defines.h.

#define E1000_WUFC_ARP   0x00000020 /* ARP Request Packet Wakeup Enable */

Definition at line 67 of file defines.h.

#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */

Definition at line 66 of file defines.h.

#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */

Definition at line 64 of file defines.h.

#define E1000_WUFC_LNKC   0x00000001 /* Link Status Change Wakeup Enable */

Definition at line 62 of file defines.h.

#define E1000_WUFC_MAG   0x00000002 /* Magic Packet Wakeup Enable */

Definition at line 63 of file defines.h.

#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */

Definition at line 65 of file defines.h.

#define E1000_WUS_BC   E1000_WUFC_BC

Definition at line 74 of file defines.h.

#define E1000_WUS_EX   E1000_WUFC_EX

Definition at line 72 of file defines.h.

#define E1000_WUS_LNKC   E1000_WUFC_LNKC

Definition at line 70 of file defines.h.

#define E1000_WUS_MAG   E1000_WUFC_MAG

Definition at line 71 of file defines.h.

#define E1000_WUS_MC   E1000_WUFC_MC

Definition at line 73 of file defines.h.

#define FIBER_LINK_UP_LIMIT   50

Definition at line 509 of file defines.h.

#define FLOW_CONTROL_ADDRESS_HIGH   0x00000100

Definition at line 472 of file defines.h.

#define FLOW_CONTROL_ADDRESS_LOW   0x00C28001

Definition at line 471 of file defines.h.

#define FLOW_CONTROL_TYPE   0x8808

Definition at line 473 of file defines.h.

#define FULL_DUPLEX   2

Definition at line 267 of file defines.h.

#define GG82563_E_PHY_ID   0x01410CA0

Definition at line 736 of file defines.h.

#define GG82563_MIN_ALT_REG   30

Definition at line 819 of file defines.h.

#define GG82563_PAGE_SHIFT   5

Definition at line 816 of file defines.h.

#define GG82563_PHY_DSP_DISTANCE   GG82563_REG(5, 26) /* DSP Distance */

Definition at line 834 of file defines.h.

#define GG82563_PHY_INBAND_CTRL   GG82563_REG(194, 18) /* Inband Control */

Definition at line 844 of file defines.h.

#define GG82563_PHY_KMRN_MODE_CTRL   GG82563_REG(193, 16) /* Kumeran Mode Control */

Definition at line 838 of file defines.h.

#define GG82563_PHY_MAC_SPEC_CTRL   GG82563_REG(2, 21) /* MAC Specific Control Register */

Definition at line 831 of file defines.h.

#define GG82563_PHY_PAGE_SELECT   GG82563_REG(0, 22) /* Page Select */

Definition at line 824 of file defines.h.

#define GG82563_PHY_PAGE_SELECT_ALT   GG82563_REG(0, 29) /* Alternate Page Select */

Definition at line 828 of file defines.h.

#define GG82563_PHY_PWR_MGMT_CTRL   GG82563_REG(193, 20) /* Power Management Control */

Definition at line 840 of file defines.h.

#define GG82563_PHY_SPEC_CTRL   GG82563_REG(0, 16) /* PHY Specific Control */

Definition at line 822 of file defines.h.

#define GG82563_PHY_SPEC_CTRL_2   GG82563_REG(0, 26) /* PHY Specific Control 2 */

Definition at line 826 of file defines.h.

#define GG82563_REG	(		page,
			reg
	)		(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))

Definition at line 817 of file defines.h.

#define HALF_DUPLEX   1

Definition at line 266 of file defines.h.

#define I217_E_PHY_ID   0x015400A0

Definition at line 746 of file defines.h.

#define I82577_E_PHY_ID   0x01540050

Definition at line 743 of file defines.h.

#define I82578_E_PHY_ID   0x004DD040

Definition at line 744 of file defines.h.

#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK   0x001C

Definition at line 801 of file defines.h.

#define I82578_EPSCR_DOWNSHIFT_ENABLE   0x0020

Definition at line 800 of file defines.h.

#define I82579_E_PHY_ID   0x01540090

Definition at line 745 of file defines.h.

#define ID_LED_DEF1_DEF2   0x1

Definition at line 700 of file defines.h.

#define ID_LED_DEF1_OFF2   0x3

Definition at line 702 of file defines.h.

#define ID_LED_DEF1_ON2   0x2

Definition at line 701 of file defines.h.

#define ID_LED_DEFAULT

Value:

((ID_LED_OFF1_ON2  << 12) | \
                  (ID_LED_OFF1_OFF2 <<  8) | \
                  (ID_LED_DEF1_DEF2 <<  4) | \
                  (ID_LED_DEF1_DEF2))

Definition at line 696 of file defines.h.

#define ID_LED_OFF1_DEF2   0x7

Definition at line 706 of file defines.h.

#define ID_LED_OFF1_OFF2   0x9

Definition at line 708 of file defines.h.

#define ID_LED_OFF1_ON2   0x8

Definition at line 707 of file defines.h.

#define ID_LED_ON1_DEF2   0x4

Definition at line 703 of file defines.h.

#define ID_LED_ON1_OFF2   0x6

Definition at line 705 of file defines.h.

#define ID_LED_ON1_ON2   0x5

Definition at line 704 of file defines.h.

#define ID_LED_RESERVED_0000   0x0000

Definition at line 694 of file defines.h.

#define ID_LED_RESERVED_FFFF   0xFFFF

Definition at line 695 of file defines.h.

#define IFE_C_E_PHY_ID   0x02A80310

Definition at line 740 of file defines.h.

#define IFE_E_PHY_ID   0x02A80330

Definition at line 738 of file defines.h.

#define IFE_PLUS_E_PHY_ID   0x02A80320

Definition at line 739 of file defines.h.

#define IFS_MAX   80

Definition at line 394 of file defines.h.

#define IFS_MIN   40

Definition at line 395 of file defines.h.

#define IFS_RATIO   4

Definition at line 396 of file defines.h.

#define IFS_STEP   10

Definition at line 397 of file defines.h.

#define IGP01E1000_I_PHY_ID   0x02A80380

Definition at line 734 of file defines.h.

#define IGP03E1000_E_PHY_ID   0x02A80390

Definition at line 737 of file defines.h.

#define IGP_ACTIVITY_LED_ENABLE   0x0300

Definition at line 711 of file defines.h.

#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF

Definition at line 710 of file defines.h.

#define IGP_LED3_MODE   0x07000000

Definition at line 712 of file defines.h.

#define IMS_ENABLE_MASK

Value:

( \
    E1000_IMS_RXT0   |    \
    E1000_IMS_TXDW   |    \
    E1000_IMS_RXDMT0 |    \
    E1000_IMS_RXSEQ  |    \
    E1000_IMS_LSC)

Definition at line 436 of file defines.h.

#define M88E1000_E_PHY_ID   0x01410C50

Definition at line 731 of file defines.h.

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000

Definition at line 787 of file defines.h.

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK   0x0C00

Definition at line 786 of file defines.h.

#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X   0x0100

Definition at line 793 of file defines.h.

#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK   0x0300

Definition at line 792 of file defines.h.

#define M88E1000_EPSCR_TX_CLK_25   0x0070 /* 25 MHz TX_CLK */

Definition at line 794 of file defines.h.

#define M88E1000_EXT_PHY_SPEC_CTRL   0x14 /* Extended PHY Specific Control */

Definition at line 751 of file defines.h.

#define M88E1000_I_PHY_ID   0x01410C30

Definition at line 732 of file defines.h.

#define M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */

Definition at line 754 of file defines.h.

#define M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */

Definition at line 753 of file defines.h.

#define M88E1000_PHY_SPEC_CTRL   0x10 /* PHY Specific Control Register */

Definition at line 749 of file defines.h.

#define M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */

Definition at line 750 of file defines.h.

#define M88E1000_PSCR_ASSERT_CRS_ON_TX   0x0800 /* 1=Assert CRS on Transmit */

Definition at line 769 of file defines.h.

#define M88E1000_PSCR_AUTO_X_1000T   0x0040

Definition at line 762 of file defines.h.

#define M88E1000_PSCR_AUTO_X_MODE   0x0060

Definition at line 764 of file defines.h.

#define M88E1000_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */

Definition at line 758 of file defines.h.

#define M88E1000_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */

Definition at line 760 of file defines.h.

#define M88E1000_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reversal enabled */

Definition at line 757 of file defines.h.

#define M88E1000_PSSR_1000MBS   0x8000 /* 10=1000Mbs */

Definition at line 778 of file defines.h.

#define M88E1000_PSSR_CABLE_LENGTH   0x0380

Definition at line 776 of file defines.h.

#define M88E1000_PSSR_CABLE_LENGTH_SHIFT   7

Definition at line 780 of file defines.h.

#define M88E1000_PSSR_DOWNSHIFT   0x0020 /* 1=Downshifted */

Definition at line 773 of file defines.h.

#define M88E1000_PSSR_MDIX   0x0040 /* 1=MDIX; 0=MDI */

Definition at line 774 of file defines.h.

#define M88E1000_PSSR_REV_POLARITY   0x0002 /* 1=Polarity reversed */

Definition at line 772 of file defines.h.

#define M88E1000_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */

Definition at line 777 of file defines.h.

#define M88E1011_I_PHY_ID   0x01410C20

Definition at line 733 of file defines.h.

#define M88E1111_I_PHY_ID   0x01410CC0

Definition at line 735 of file defines.h.

#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X   0x0800

Definition at line 798 of file defines.h.

#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK   0x0E00

Definition at line 797 of file defines.h.

#define MASTER_DISABLE_TIMEOUT   800

Definition at line 514 of file defines.h.

#define MAX_JUMBO_FRAME_SIZE   0x3F00

Definition at line 368 of file defines.h.

#define MAX_PHY_MULTI_PAGE_REG   0xF

Definition at line 724 of file defines.h.

#define MAX_PHY_REG_ADDRESS   0x1F /* 5 bit address bus (0-0x1F) */

Definition at line 723 of file defines.h.

#define MDIO_OWNERSHIP_TIMEOUT   10

Definition at line 518 of file defines.h.

#define MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */

Definition at line 559 of file defines.h.

#define MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */

Definition at line 556 of file defines.h.

#define MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */

Definition at line 560 of file defines.h.

#define MII_CR_POWER_DOWN   0x0800 /* Power down */

Definition at line 558 of file defines.h.

#define MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */

Definition at line 561 of file defines.h.

#define MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */

Definition at line 557 of file defines.h.

#define MII_CR_SPEED_10   0x0000

Definition at line 564 of file defines.h.

#define MII_CR_SPEED_100   0x2000

Definition at line 563 of file defines.h.

#define MII_CR_SPEED_1000   0x0040

Definition at line 562 of file defines.h.

#define MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */

Definition at line 568 of file defines.h.

#define MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */

Definition at line 567 of file defines.h.

#define MIN_NUM_XMITS   1000

Definition at line 398 of file defines.h.

#define NVM_A8_OPCODE_SPI   0x08 /* opcode bit-3 = address bit-8 */

Definition at line 686 of file defines.h.

#define NVM_ALT_MAC_ADDR_PTR   0x0037

Definition at line 651 of file defines.h.

#define NVM_CFG   0x0012

Definition at line 650 of file defines.h.

#define NVM_CHECKSUM_REG   0x003F

Definition at line 652 of file defines.h.

#define NVM_COMPAT   0x0003

Definition at line 644 of file defines.h.

#define NVM_COMPAT_LOM   0x0800

Definition at line 668 of file defines.h.

#define NVM_ID_LED_SETTINGS   0x0004

Definition at line 645 of file defines.h.

#define NVM_INIT_3GIO_3   0x001A

Definition at line 648 of file defines.h.

#define NVM_INIT_CONTROL2_REG   0x000F

Definition at line 646 of file defines.h.

#define NVM_INIT_CONTROL3_PORT_A   0x0024

Definition at line 649 of file defines.h.

#define NVM_INIT_CONTROL3_PORT_B   0x0014

Definition at line 647 of file defines.h.

#define NVM_MAX_RETRY_SPI   5000 /* Max wait of 5ms, for RDY signal */

Definition at line 683 of file defines.h.

#define NVM_PBA_OFFSET_0   8

Definition at line 677 of file defines.h.

#define NVM_PBA_OFFSET_1   9

Definition at line 678 of file defines.h.

#define NVM_PBA_PTR_GUARD   0xFAFA

Definition at line 679 of file defines.h.

#define NVM_RDSR_OPCODE_SPI   0x05 /* NVM read Status register */

Definition at line 688 of file defines.h.

#define NVM_READ_OPCODE_SPI   0x03 /* NVM read opcode */

Definition at line 684 of file defines.h.

#define NVM_STATUS_RDY_SPI   0x01

Definition at line 691 of file defines.h.

#define NVM_SUM   0xBABA

Definition at line 674 of file defines.h.

#define NVM_WORD0F_ASM_DIR   0x2000

Definition at line 662 of file defines.h.

#define NVM_WORD0F_PAUSE   0x1000

Definition at line 661 of file defines.h.

#define NVM_WORD0F_PAUSE_MASK   0x3000

Definition at line 660 of file defines.h.

#define NVM_WORD1A_ASPM_MASK   0x000C

Definition at line 665 of file defines.h.

#define NVM_WORD_SIZE_BASE_SHIFT   6

Definition at line 680 of file defines.h.

#define NVM_WREN_OPCODE_SPI   0x06 /* NVM set Write Enable latch */

Definition at line 687 of file defines.h.

#define NVM_WRITE_OPCODE_SPI   0x02 /* NVM write opcode */

Definition at line 685 of file defines.h.

#define NWAY_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */

Definition at line 574 of file defines.h.

#define NWAY_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */

Definition at line 573 of file defines.h.

#define NWAY_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */

Definition at line 572 of file defines.h.

#define NWAY_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */

Definition at line 571 of file defines.h.

#define NWAY_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */

Definition at line 576 of file defines.h.

#define NWAY_AR_PAUSE   0x0400 /* Pause operation desired */

Definition at line 575 of file defines.h.

#define NWAY_ER_LP_NWAY_CAPS   0x0001 /* LP has Auto Neg Capability */

Definition at line 584 of file defines.h.

#define NWAY_LPAR_100TX_FD_CAPS   0x0100 /* LP 100TX Full Dplx Capable */

Definition at line 579 of file defines.h.

#define NWAY_LPAR_ASM_DIR   0x0800 /* LP Asymmetric Pause Direction bit */

Definition at line 581 of file defines.h.

#define NWAY_LPAR_PAUSE   0x0400 /* LP Pause operation desired */

Definition at line 580 of file defines.h.

#define PCI_HEADER_TYPE_MULTIFUNC   0x80

Definition at line 718 of file defines.h.

#define PCI_HEADER_TYPE_REGISTER   0x0E

Definition at line 715 of file defines.h.

#define PCIE_LINK_STATUS   0x12

Definition at line 716 of file defines.h.

#define PCIE_LINK_WIDTH_MASK   0x3F0

Definition at line 719 of file defines.h.

#define PCIE_LINK_WIDTH_SHIFT   4

Definition at line 720 of file defines.h.

#define PCIE_NO_SNOOP_ALL

Value:

(E1000_GCR_RXD_NO_SNOOP         | \
               E1000_GCR_RXDSCW_NO_SNOOP      | \
               E1000_GCR_RXDSCR_NO_SNOOP      | \
               E1000_GCR_TXD_NO_SNOOP         | \
               E1000_GCR_TXDSCW_NO_SNOOP      | \
               E1000_GCR_TXDSCR_NO_SNOOP)

Definition at line 548 of file defines.h.

#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */

Definition at line 609 of file defines.h.

#define PHY_1000T_STATUS   0x0A /* 1000Base-T Status Reg */

Definition at line 610 of file defines.h.

#define PHY_AUTO_NEG_LIMIT   45

Definition at line 511 of file defines.h.

#define PHY_AUTONEG_ADV   0x04 /* Autoneg Advertisement */

Definition at line 606 of file defines.h.

#define PHY_AUTONEG_EXP   0x06 /* Autoneg Expansion Reg */

Definition at line 608 of file defines.h.

#define PHY_CFG_TIMEOUT   100

Definition at line 516 of file defines.h.

#define PHY_CONTROL   0x00 /* Control Register */

Definition at line 602 of file defines.h.

#define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */

Definition at line 613 of file defines.h.

#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */

Definition at line 611 of file defines.h.

#define PHY_FORCE_LIMIT   20

Definition at line 512 of file defines.h.

#define PHY_ID1   0x02 /* Phy Id Reg (word 1) */

Definition at line 604 of file defines.h.

#define PHY_ID2   0x03 /* Phy Id Reg (word 2) */

Definition at line 605 of file defines.h.

#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */

Definition at line 607 of file defines.h.

#define PHY_PAGE_SHIFT   5

Definition at line 807 of file defines.h.

#define PHY_REG	(		page,
			reg
	)

Value:

(((page) << PHY_PAGE_SHIFT) | \
                           ((reg) & MAX_PHY_REG_ADDRESS))

Definition at line 808 of file defines.h.

#define PHY_REVISION_MASK   0xFFFFFFF0

Definition at line 722 of file defines.h.

#define PHY_STATUS   0x01 /* Status Register */

Definition at line 603 of file defines.h.

#define REQ_RX_DESCRIPTOR_MULTIPLE   8

Definition at line 53 of file defines.h.

#define REQ_TX_DESCRIPTOR_MULTIPLE   8

Definition at line 52 of file defines.h.

#define SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */

Definition at line 597 of file defines.h.

#define SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */

Definition at line 596 of file defines.h.