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enum | Interrupt_B_Ack_Bits {
G1_Gate_Error_Confirm = _bit1,
G1_TC_Error_Confirm = _bit2,
AO_BC_TC_Trigger_Error_Confirm = _bit3,
AO_BC_TC_Error_Confirm = _bit4,
AO_UI2_TC_Error_Confrim = _bit5,
AO_UI2_TC_Interrupt_Ack = _bit6,
AO_UC_TC_Interrupt_Ack = _bit7,
AO_BC_TC_Interrupt_Ack = _bit8,
AO_START1_Interrupt_Ack = _bit9,
AO_UPDATE_Interrupt_Ack = _bit10,
AO_START_Interrupt_Ack = _bit11,
AO_STOP_Interrupt_Ack = _bit12,
AO_Error_Interrupt_Ack = _bit13,
G1_TC_Interrupt_Ack = _bit14,
G1_Gate_Interrupt_Ack = _bit15
} |
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enum | Joint_Status_2_Bits { AO_TMRDACWRs_In_Progress_St = 0x20
} |
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enum | AO_FIFO_Mode_Bits { AO_FIFO_Mode_HF_to_F = (3 << 14),
AO_FIFO_Mode_F = (2 << 14),
AO_FIFO_Mode_HF = (1 << 14),
AO_FIFO_Mode_E = (0 << 14)
} |
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enum | Clock_and_FOUT_bits {
FOUT_Enable = _bit15,
FOUT_Timebase_Select = _bit14,
DIO_Serial_Out_Divide_By_2 = _bit13,
Slow_Internal_Time_Divide_By_2 = _bit12,
Slow_Internal_Timebase = _bit11,
G_Source_Divide_By_2 = _bit10,
Clock_To_Board_Divide_By_2 = _bit9,
Clock_To_Board = _bit8,
AI_Output_Divide_By_2 = _bit7,
AI_Source_Divide_By_2 = _bit6,
AO_Output_Divide_By_2 = _bit5,
AO_Source_Divide_By_2 = _bit4,
FOUT_Divider_mask = 0xf
} |
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enum | RTSI_Trig_Direction_Bits { Drive_RTSI_Clock_Bit = 0x1,
Use_RTSI_Clock_Bit = 0x2
} |
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enum | ai_convert_output_selection { AI_CONVERT_Output_High_Z = 0,
AI_CONVERT_Output_Ground = 1,
AI_CONVERT_Output_Enable_Low = 2,
AI_CONVERT_Output_Enable_High = 3
} |
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enum | Second_IRQ_A_Enable_Bits {
AI_SC_TC_Second_Irq_Enable = _bit0,
AI_START1_Second_Irq_Enable = _bit1,
AI_START2_Second_Irq_Enable = _bit2,
AI_START_Second_Irq_Enable = _bit3,
AI_STOP_Second_Irq_Enable = _bit4,
AI_Error_Second_Irq_Enable = _bit5,
G0_TC_Second_Irq_Enable = _bit6,
AI_FIFO_Second_Irq_Enable = _bit7,
G0_Gate_Second_Irq_Enable = _bit8,
Pass_Thru_0_Second_Irq_Enable = _bit9
} |
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enum | Second_IRQ_B_Enable_Bits {
AO_BC_TC_Second_Irq_Enable = _bit0,
AO_START1_Second_Irq_Enable = _bit1,
AO_UPDATE_Second_Irq_Enable = _bit2,
AO_START_Second_Irq_Enable = _bit3,
AO_STOP_Second_Irq_Enable = _bit4,
AO_Error_Second_Irq_Enable = _bit5,
AO_UC_TC_Second_Irq_Enable = _bit6,
AO_UI2_TC_Second_Irq_Enable = _bit7,
AO_FIFO_Second_Irq_Enable = _bit8,
G1_TC_Second_Irq_Enable = _bit9,
G1_Gate_Second_Irq_Enable = _bit10,
Pass_Thru_1_Second_Irq_Enable = _bit11
} |
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enum | AO_Personal_Bits {
AO_Interval_Buffer_Mode = 1 << 3,
AO_BC_Source_Select = 1 << 4,
AO_UPDATE_Pulse_Width = 1 << 5,
AO_UPDATE_Pulse_Timebase = 1 << 6,
AO_UPDATE_Original_Pulse = 1 << 7,
AO_DMA_PIO_Control = 1 << 8,
AO_AOFREQ_Polarity = 1 << 9,
AO_FIFO_Enable = 1 << 10,
AO_FIFO_Flags_Polarity = 1 << 11,
AO_TMRDACWR_Pulse_Width = 1 << 12,
AO_Fast_CPU = 1 << 13,
AO_Number_Of_DAC_Packages = 1 << 14,
AO_Multiple_DACS_Per_Package = 1 << 15
} |
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enum | RTSI_Trig_B_Output_Bits { RTSI_Sub_Selection_1_Bit = 0x8000
} |
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enum | ao_update_output_selection { AO_Update_Output_High_Z = 0,
AO_Update_Output_Ground = 1,
AO_Update_Output_Enable_Low = 2,
AO_Update_Output_Enable_High = 3
} |
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enum | XXX_Status_Bits { PROMOUT = 0x1,
AI_FIFO_LOWER_NOT_EMPTY = 0x8
} |
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enum | AI_AO_Select_Bits { AI_DMA_Select_Shift = 0,
AI_DMA_Select_Mask = 0xf,
AO_DMA_Select_Shift = 4,
AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift
} |
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enum | Configuration_Memory_Low_Bits { AI_DITHER = 0x200,
AI_LAST_CHANNEL = 0x8000
} |
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enum | Configuration_Memory_High_Bits { AI_AC_COUPLE = 0x800,
AI_DIFFERENTIAL = 0x1000,
AI_COMMON = 0x2000,
AI_GROUND = 0x3000
} |
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enum | windowed_regs_67xx_61xx {
AO_Immediate_671x = 0x11,
AO_Timed_611x = 0x10,
AO_FIFO_Offset_Load_611x = 0x13,
AO_Later_Single_Point_Updates = 0x14,
AO_Waveform_Generation_611x = 0x15,
AO_Misc_611x = 0x16,
AO_Calibration_Channel_Select_67xx = 0x17,
AO_Configuration_2_67xx = 0x18,
CAL_ADC_Command_67xx = 0x19,
CAL_ADC_Status_67xx = 0x1a,
CAL_ADC_Data_67xx = 0x1b,
CAL_ADC_Config_Data_High_Word_67xx = 0x1c,
CAL_ADC_Config_Data_Low_Word_67xx = 0x1d
} |
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enum | AO_Misc_611x_Bits { CLEAR_WG = 1
} |
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enum | cs5529_configuration_bits {
CSCFG_CAL_CONTROL_MASK = 0x7,
CSCFG_SELF_CAL_OFFSET = 0x1,
CSCFG_SELF_CAL_GAIN = 0x2,
CSCFG_SELF_CAL_OFFSET_GAIN = 0x3,
CSCFG_SYSTEM_CAL_OFFSET = 0x5,
CSCFG_SYSTEM_CAL_GAIN = 0x6,
CSCFG_DONE = 1 << 3,
CSCFG_POWER_SAVE_SELECT = 1 << 4,
CSCFG_PORT_MODE = 1 << 5,
CSCFG_RESET_VALID = 1 << 6,
CSCFG_RESET = 1 << 7,
CSCFG_UNIPOLAR = 1 << 12,
CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13,
CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13,
CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13,
CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13,
CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13,
CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13,
CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13,
CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13,
CSCFG_WORD_RATE_MASK = 0x7 << 13,
CSCFG_LOW_POWER = 1 << 16
} |
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enum | cs5529_command_bits {
CSCMD_POWER_SAVE = 0x1,
CSCMD_REGISTER_SELECT_MASK = 0xe,
CSCMD_OFFSET_REGISTER = 0x0,
CSCMD_GAIN_REGISTER = 0x2,
CSCMD_CONFIG_REGISTER = 0x4,
CSCMD_READ = 0x10,
CSCMD_CONTINUOUS_CONVERSIONS = 0x20,
CSCMD_SINGLE_CONVERSION = 0x40,
CSCMD_COMMAND = 0x80
} |
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enum | cs5529_status_bits { CSS_ADC_BUSY = 0x1,
CSS_OSC_DETECT = 0x2,
CSS_OVERRANGE = 0x4
} |
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enum | {
ai_gain_16,
ai_gain_8,
ai_gain_14,
ai_gain_4,
ai_gain_611x,
ai_gain_622x,
ai_gain_628x,
ai_gain_6143
} |
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enum | caldac_enum {
caldac_none = 0,
mb88341,
dac8800,
dac8043,
ad8522,
ad8804,
ad8842,
ad8804_debug
} |
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enum | ni_reg_type {
ni_reg_normal = 0x0,
ni_reg_611x = 0x1,
ni_reg_6711 = 0x2,
ni_reg_6713 = 0x4,
ni_reg_67xx_mask = 0x6,
ni_reg_6xxx_mask = 0x7,
ni_reg_622x = 0x8,
ni_reg_625x = 0x10,
ni_reg_628x = 0x18,
ni_reg_m_series_mask = 0x18,
ni_reg_6143 = 0x20
} |
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enum | m_series_register_offsets {
M_Offset_CDIO_DMA_Select = 0x7,
M_Offset_SCXI_Status = 0x7,
M_Offset_AI_AO_Select = 0x9,
M_Offset_SCXI_Serial_Data_In = 0x9,
M_Offset_G0_G1_Select = 0xb,
M_Offset_Misc_Command = 0xf,
M_Offset_SCXI_Serial_Data_Out = 0x11,
M_Offset_SCXI_Control = 0x13,
M_Offset_SCXI_Output_Enable = 0x15,
M_Offset_AI_FIFO_Data = 0x1c,
M_Offset_Static_Digital_Output = 0x24,
M_Offset_Static_Digital_Input = 0x24,
M_Offset_DIO_Direction = 0x28,
M_Offset_Cal_PWM = 0x40,
M_Offset_AI_Config_FIFO_Data = 0x5e,
M_Offset_Interrupt_C_Enable = 0x88,
M_Offset_Interrupt_C_Status = 0x88,
M_Offset_Analog_Trigger_Control = 0x8c,
M_Offset_AO_Serial_Interrupt_Enable = 0xa0,
M_Offset_AO_Serial_Interrupt_Ack = 0xa1,
M_Offset_AO_Serial_Interrupt_Status = 0xa1,
M_Offset_AO_Calibration = 0xa3,
M_Offset_AO_FIFO_Data = 0xa4,
M_Offset_PFI_Filter = 0xb0,
M_Offset_RTSI_Filter = 0xb4,
M_Offset_SCXI_Legacy_Compatibility = 0xbc,
M_Offset_Interrupt_A_Ack = 0x104,
M_Offset_AI_Status_1 = 0x104,
M_Offset_Interrupt_B_Ack = 0x106,
M_Offset_AO_Status_1 = 0x106,
M_Offset_AI_Command_2 = 0x108,
M_Offset_G01_Status = 0x108,
M_Offset_AO_Command_2 = 0x10a,
M_Offset_AO_Status_2 = 0x10c,
M_Offset_G0_Command = 0x10c,
M_Offset_G1_Command = 0x10e,
M_Offset_G0_HW_Save = 0x110,
M_Offset_G0_HW_Save_High = 0x110,
M_Offset_AI_Command_1 = 0x110,
M_Offset_G0_HW_Save_Low = 0x112,
M_Offset_AO_Command_1 = 0x112,
M_Offset_G1_HW_Save = 0x114,
M_Offset_G1_HW_Save_High = 0x114,
M_Offset_G1_HW_Save_Low = 0x116,
M_Offset_AI_Mode_1 = 0x118,
M_Offset_G0_Save = 0x118,
M_Offset_G0_Save_High = 0x118,
M_Offset_AI_Mode_2 = 0x11a,
M_Offset_G0_Save_Low = 0x11a,
M_Offset_AI_SI_Load_A = 0x11c,
M_Offset_G1_Save = 0x11c,
M_Offset_G1_Save_High = 0x11c,
M_Offset_G1_Save_Low = 0x11e,
M_Offset_AI_SI_Load_B = 0x120,
M_Offset_AO_UI_Save = 0x120,
M_Offset_AI_SC_Load_A = 0x124,
M_Offset_AO_BC_Save = 0x124,
M_Offset_AI_SC_Load_B = 0x128,
M_Offset_AO_UC_Save = 0x128,
M_Offset_AI_SI2_Load_A = 0x12c,
M_Offset_AI_SI2_Load_B = 0x130,
M_Offset_G0_Mode = 0x134,
M_Offset_G1_Mode = 0x136,
M_Offset_Joint_Status_1 = 0x136,
M_Offset_G0_Load_A = 0x138,
M_Offset_Joint_Status_2 = 0x13a,
M_Offset_G0_Load_B = 0x13c,
M_Offset_G1_Load_A = 0x140,
M_Offset_G1_Load_B = 0x144,
M_Offset_G0_Input_Select = 0x148,
M_Offset_G1_Input_Select = 0x14a,
M_Offset_AO_Mode_1 = 0x14c,
M_Offset_AO_Mode_2 = 0x14e,
M_Offset_AO_UI_Load_A = 0x150,
M_Offset_AO_UI_Load_B = 0x154,
M_Offset_AO_BC_Load_A = 0x158,
M_Offset_AO_BC_Load_B = 0x15c,
M_Offset_AO_UC_Load_A = 0x160,
M_Offset_AO_UC_Load_B = 0x164,
M_Offset_Clock_and_FOUT = 0x170,
M_Offset_IO_Bidirection_Pin = 0x172,
M_Offset_RTSI_Trig_Direction = 0x174,
M_Offset_Interrupt_Control = 0x176,
M_Offset_AI_Output_Control = 0x178,
M_Offset_Analog_Trigger_Etc = 0x17a,
M_Offset_AI_START_STOP_Select = 0x17c,
M_Offset_AI_Trigger_Select = 0x17e,
M_Offset_AI_SI_Save = 0x180,
M_Offset_AI_DIV_Load_A = 0x180,
M_Offset_AI_SC_Save = 0x184,
M_Offset_AO_Start_Select = 0x184,
M_Offset_AO_Trigger_Select = 0x186,
M_Offset_AO_Mode_3 = 0x18c,
M_Offset_G0_Autoincrement = 0x188,
M_Offset_G1_Autoincrement = 0x18a,
M_Offset_Joint_Reset = 0x190,
M_Offset_Interrupt_A_Enable = 0x192,
M_Offset_Interrupt_B_Enable = 0x196,
M_Offset_AI_Personal = 0x19a,
M_Offset_AO_Personal = 0x19c,
M_Offset_RTSI_Trig_A_Output = 0x19e,
M_Offset_RTSI_Trig_B_Output = 0x1a0,
M_Offset_RTSI_Shared_MUX = 0x1a2,
M_Offset_AO_Output_Control = 0x1ac,
M_Offset_AI_Mode_3 = 0x1ae,
M_Offset_Configuration_Memory_Clear = 0x1a4,
M_Offset_AI_FIFO_Clear = 0x1a6,
M_Offset_AO_FIFO_Clear = 0x1a8,
M_Offset_G0_Counting_Mode = 0x1b0,
M_Offset_G1_Counting_Mode = 0x1b2,
M_Offset_G0_Second_Gate = 0x1b4,
M_Offset_G1_Second_Gate = 0x1b6,
M_Offset_G0_DMA_Config = 0x1b8,
M_Offset_G0_DMA_Status = 0x1b8,
M_Offset_G1_DMA_Config = 0x1ba,
M_Offset_G1_DMA_Status = 0x1ba,
M_Offset_G0_MSeries_ABZ = 0x1c0,
M_Offset_G1_MSeries_ABZ = 0x1c2,
M_Offset_Clock_and_Fout2 = 0x1c4,
M_Offset_PLL_Control = 0x1c6,
M_Offset_PLL_Status = 0x1c8,
M_Offset_PFI_Output_Select_1 = 0x1d0,
M_Offset_PFI_Output_Select_2 = 0x1d2,
M_Offset_PFI_Output_Select_3 = 0x1d4,
M_Offset_PFI_Output_Select_4 = 0x1d6,
M_Offset_PFI_Output_Select_5 = 0x1d8,
M_Offset_PFI_Output_Select_6 = 0x1da,
M_Offset_PFI_DI = 0x1dc,
M_Offset_PFI_DO = 0x1de,
M_Offset_AI_Config_FIFO_Bypass = 0x218,
M_Offset_SCXI_DIO_Enable = 0x21c,
M_Offset_CDI_FIFO_Data = 0x220,
M_Offset_CDO_FIFO_Data = 0x220,
M_Offset_CDIO_Status = 0x224,
M_Offset_CDIO_Command = 0x224,
M_Offset_CDI_Mode = 0x228,
M_Offset_CDO_Mode = 0x22c,
M_Offset_CDI_Mask_Enable = 0x230,
M_Offset_CDO_Mask_Enable = 0x234
} |
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enum | MSeries_AI_Config_FIFO_Data_Bits {
MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,
MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0,
MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6,
MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6,
MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6,
MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6,
MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6,
MSeries_AI_Config_Polarity_Bit = 0x1000,
MSeries_AI_Config_Dither_Bit = 0x2000,
MSeries_AI_Config_Last_Channel_Bit = 0x4000
} |
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enum | MSeries_Clock_and_Fout2_Bits {
MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb,
MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14,
MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b,
MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d,
MSeries_PLL_In_Source_Select_Mask = 0x1f,
MSeries_Timebase1_Select_Bit = 0x20,
MSeries_Timebase3_Select_Bit = 0x40,
MSeries_RTSI_10MHz_Bit = 0x80
} |
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enum | MSeries_PLL_Control_Bits {
MSeries_PLL_Enable_Bit = 0x1000,
MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,
MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000,
MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000,
MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000
} |
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enum | MSeries_PLL_Status { MSeries_PLL_Locked_Bit = 0x1
} |
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enum | MSeries_AI_Config_FIFO_Bypass_Bits {
MSeries_AI_Bypass_Channel_Mask = 0x7,
MSeries_AI_Bypass_Bank_Mask = 0x78,
MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380,
MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00,
MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000,
MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000,
MSeries_AI_Bypass_Gain_Mask = 0x1c0000,
MSeries_AI_Bypass_Dither_Bit = 0x200000,
MSeries_AI_Bypass_Polarity_Bit = 0x400000,
MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000
} |
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enum | MSeries_AO_Config_Bank_Bits {
MSeries_AO_DAC_Offset_Select_Mask = 0x7,
MSeries_AO_DAC_Offset_0V_Bits = 0x0,
MSeries_AO_DAC_Offset_5V_Bits = 0x1,
MSeries_AO_DAC_Reference_Mask = 0x38,
MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0,
MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8,
MSeries_AO_Update_Timed_Bit = 0x40,
MSeries_AO_Bipolar_Bit = 0x80
} |
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enum | MSeries_AO_Reference_Attenuation_Bits { MSeries_Attenuate_x5_Bit = 0x1
} |
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enum | MSeries_Gi_DMA_Config_Bits {
Gi_DMA_BankSW_Error_Bit = 0x10,
Gi_DMA_Reset_Bit = 0x8,
Gi_DMA_Int_Enable_Bit = 0x4,
Gi_DMA_Write_Bit = 0x2,
Gi_DMA_Enable_Bit = 0x1
} |
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enum | CDIO_DMA_Select_Bits { CDI_DMA_Select_Shift = 0,
CDI_DMA_Select_Mask = 0xf,
CDO_DMA_Select_Shift = 4,
CDO_DMA_Select_Mask = 0xf << CDO_DMA_Select_Shift
} |
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enum | CDIO_Status_Bits {
CDO_FIFO_Empty_Bit = 0x1,
CDO_FIFO_Full_Bit = 0x2,
CDO_FIFO_Request_Bit = 0x4,
CDO_Overrun_Bit = 0x8,
CDO_Underflow_Bit = 0x10,
CDI_FIFO_Empty_Bit = 0x10000,
CDI_FIFO_Full_Bit = 0x20000,
CDI_FIFO_Request_Bit = 0x40000,
CDI_Overrun_Bit = 0x80000,
CDI_Overflow_Bit = 0x100000
} |
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enum | CDIO_Command_Bits {
CDO_Disarm_Bit = 0x1,
CDO_Arm_Bit = 0x2,
CDI_Disarm_Bit = 0x4,
CDI_Arm_Bit = 0x8,
CDO_Reset_Bit = 0x10,
CDI_Reset_Bit = 0x20,
CDO_Error_Interrupt_Enable_Set_Bit = 0x40,
CDO_Error_Interrupt_Enable_Clear_Bit = 0x80,
CDI_Error_Interrupt_Enable_Set_Bit = 0x100,
CDI_Error_Interrupt_Enable_Clear_Bit = 0x200,
CDO_FIFO_Request_Interrupt_Enable_Set_Bit = 0x400,
CDO_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x800,
CDI_FIFO_Request_Interrupt_Enable_Set_Bit = 0x1000,
CDI_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x2000,
CDO_Error_Interrupt_Confirm_Bit = 0x4000,
CDI_Error_Interrupt_Confirm_Bit = 0x8000,
CDO_Empty_FIFO_Interrupt_Enable_Set_Bit = 0x10000,
CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit = 0x20000,
CDO_SW_Update_Bit = 0x80000,
CDI_SW_Update_Bit = 0x100000
} |
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enum | CDI_Mode_Bits {
CDI_Sample_Source_Select_Mask = 0x3f,
CDI_Halt_On_Error_Bit = 0x200,
CDI_Polarity_Bit = 0x400,
CDI_FIFO_Mode_Bit = 0x800,
CDI_Data_Lane_Mask = 0x3000,
CDI_Data_Lane_0_15_Bits = 0x0,
CDI_Data_Lane_16_31_Bits = 0x1000,
CDI_Data_Lane_0_7_Bits = 0x0,
CDI_Data_Lane_8_15_Bits = 0x1000,
CDI_Data_Lane_16_23_Bits = 0x2000,
CDI_Data_Lane_24_31_Bits = 0x3000
} |
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enum | CDO_Mode_Bits {
CDO_Sample_Source_Select_Mask = 0x3f,
CDO_Retransmit_Bit = 0x100,
CDO_Halt_On_Error_Bit = 0x200,
CDO_Polarity_Bit = 0x400,
CDO_FIFO_Mode_Bit = 0x800,
CDO_Data_Lane_Mask = 0x3000,
CDO_Data_Lane_0_15_Bits = 0x0,
CDO_Data_Lane_16_31_Bits = 0x1000,
CDO_Data_Lane_0_7_Bits = 0x0,
CDO_Data_Lane_8_15_Bits = 0x1000,
CDO_Data_Lane_16_23_Bits = 0x2000,
CDO_Data_Lane_24_31_Bits = 0x3000
} |
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enum | Interrupt_C_Enable_Bits { Interrupt_Group_C_Enable_Bit = 0x1
} |
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enum | Interrupt_C_Status_Bits { Interrupt_Group_C_Status_Bit = 0x1
} |
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