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ops-pmcmsp.c
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1 /*
2  * PMC-Sierra MSP board specific pci_ops
3  *
4  * Copyright 2001 MontaVista Software Inc.
5  * Copyright 2005-2007 PMC-Sierra, Inc
6  *
7  * Author: Jun Sun, [email protected] or [email protected]
8  *
9  * Much of the code is derived from the original DDB5074 port by
10  * Geert Uytterhoeven <[email protected]>
11  *
12  * This program is free software; you can redistribute it and/or modify it
13  * under the terms of the GNU General Public License as published by the
14  * Free Software Foundation; either version 2 of the License, or (at your
15  * option) any later version.
16  *
17  */
18 
19 #define PCI_COUNTERS 1
20 
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 
25 #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
26 #include <linux/proc_fs.h>
27 #include <linux/seq_file.h>
28 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
29 
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 
33 #include <asm/byteorder.h>
34 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
35 #include <asm/mipsmtregs.h>
36 #endif
37 
38 #include <msp_prom.h>
39 #include <msp_cic_int.h>
40 #include <msp_pci.h>
41 #include <msp_regs.h>
42 #include <msp_regops.h>
43 
44 #define PCI_ACCESS_READ 0
45 #define PCI_ACCESS_WRITE 1
46 
47 #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
48 static char proc_init;
49 extern struct proc_dir_entry *proc_bus_pci_dir;
50 unsigned int pci_int_count[32];
51 
52 static void pci_proc_init(void);
53 
54 /*****************************************************************************
55  *
56  * FUNCTION: read_msp_pci_counts
57  * _________________________________________________________________________
58  *
59  * DESCRIPTION: Prints the count of how many times each PCI
60  * interrupt has asserted. Can be invoked by the
61  * /proc filesystem.
62  *
63  * INPUTS: page - part of STDOUT calculation
64  * off - part of STDOUT calculation
65  * count - part of STDOUT calculation
66  * data - unused
67  *
68  * OUTPUTS: start - new start location
69  * eof - end of file pointer
70  *
71  * RETURNS: len - STDOUT length
72  *
73  ****************************************************************************/
74 static int read_msp_pci_counts(char *page, char **start, off_t off,
75  int count, int *eof, void *data)
76 {
77  int i;
78  int len = 0;
79  unsigned int intcount, total = 0;
80 
81  for (i = 0; i < 32; ++i) {
82  intcount = pci_int_count[i];
83  if (intcount != 0) {
84  len += sprintf(page + len, "[%d] = %u\n", i, intcount);
85  total += intcount;
86  }
87  }
88 
89  len += sprintf(page + len, "total = %u\n", total);
90  if (len <= off+count)
91  *eof = 1;
92 
93  *start = page + off;
94  len -= off;
95  if (len > count)
96  len = count;
97  if (len < 0)
98  len = 0;
99 
100  return len;
101 }
102 
103 /*****************************************************************************
104  *
105  * FUNCTION: gen_pci_cfg_wr
106  * _________________________________________________________________________
107  *
108  * DESCRIPTION: Generates a configuration write cycle for debug purposes.
109  * The IDSEL line asserted and location and data written are
110  * immaterial. Just want to be able to prove that a
111  * configuration write can be correctly generated on the
112  * PCI bus. Intent is that this function by invocable from
113  * the /proc filesystem.
114  *
115  * INPUTS: page - part of STDOUT calculation
116  * off - part of STDOUT calculation
117  * count - part of STDOUT calculation
118  * data - unused
119  *
120  * OUTPUTS: start - new start location
121  * eof - end of file pointer
122  *
123  * RETURNS: len - STDOUT length
124  *
125  ****************************************************************************/
126 static int gen_pci_cfg_wr(char *page, char **start, off_t off,
127  int count, int *eof, void *data)
128 {
129  unsigned char where = 0; /* Write to static Device/Vendor ID */
130  unsigned char bus_num = 0; /* Bus 0 */
131  unsigned char dev_fn = 0xF; /* Arbitrary device number */
132  u32 wr_data = 0xFF00AA00; /* Arbitrary data */
133  struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
134  int len = 0;
135  unsigned long value;
136  int intr;
137 
138  len += sprintf(page + len, "PMC MSP PCI: Beginning\n");
139 
140  if (proc_init == 0) {
141  pci_proc_init();
142  proc_init = ~0;
143  }
144 
145  len += sprintf(page + len, "PMC MSP PCI: Before Cfg Wr\n");
146 
147  /*
148  * Generate PCI Configuration Write Cycle
149  */
150 
151  /* Clear cause register bits */
153 
154  /* Setup address that is to appear on PCI bus */
156  (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
157  (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
158  (where & 0xFC);
159 
160  value = cpu_to_le32(wr_data);
161 
162  /* Launch the PCI configuration write cycle */
164 
165  /*
166  * Check if the PCI configuration cycle (rd or wr) succeeded, by
167  * checking the status bits for errors like master or target abort.
168  */
169  intr = preg->if_status;
170 
171  len += sprintf(page + len, "PMC MSP PCI: After Cfg Wr\n");
172 
173  /* Handle STDOUT calculations */
174  if (len <= off+count)
175  *eof = 1;
176  *start = page + off;
177  len -= off;
178  if (len > count)
179  len = count;
180  if (len < 0)
181  len = 0;
182 
183  return len;
184 }
185 
186 /*****************************************************************************
187  *
188  * FUNCTION: pci_proc_init
189  * _________________________________________________________________________
190  *
191  * DESCRIPTION: Create entries in the /proc filesystem for debug access.
192  *
193  * INPUTS: none
194  *
195  * OUTPUTS: none
196  *
197  * RETURNS: none
198  *
199  ****************************************************************************/
200 static void pci_proc_init(void)
201 {
202  create_proc_read_entry("pmc_msp_pci_rd_cnt", 0, NULL,
203  read_msp_pci_counts, NULL);
204  create_proc_read_entry("pmc_msp_pci_cfg_wr", 0, NULL,
205  gen_pci_cfg_wr, NULL);
206 }
207 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
208 
209 static DEFINE_SPINLOCK(bpci_lock);
210 
211 /*****************************************************************************
212  *
213  * STRUCT: pci_io_resource
214  * _________________________________________________________________________
215  *
216  * DESCRIPTION: Defines the address range that pciauto() will use to
217  * assign to the I/O BARs of PCI devices.
218  *
219  * Use the start and end addresses of the MSP7120 PCI Host
220  * Controller I/O space, in the form that they appear on the
221  * PCI bus AFTER MSP7120 has performed address translation.
222  *
223  * For I/O accesses, MSP7120 ignores OATRAN and maps I/O
224  * accesses into the bottom 0xFFF region of address space,
225  * so that is the range to put into the pci_io_resource
226  * struct.
227  *
228  * In MSP4200, the start address was 0x04 instead of the
229  * expected 0x00. Will just assume there was a good reason
230  * for this!
231  *
232  * NOTES: Linux, by default, will assign I/O space to the lowest
233  * region of address space. Since MSP7120 and Linux,
234  * by default, have no offset in between how they map, the
235  * io_offset element of pci_controller struct should be set
236  * to zero.
237  * ELEMENTS:
238  * name - String used for a meaningful name.
239  *
240  * start - Start address of MSP7120's I/O space, as MSP7120 presents
241  * the address on the PCI bus.
242  *
243  * end - End address of MSP7120's I/O space, as MSP7120 presents
244  * the address on the PCI bus.
245  *
246  * flags - Attributes indicating the type of resource. In this case,
247  * indicate I/O space.
248  *
249  ****************************************************************************/
250 static struct resource pci_io_resource = {
251  .name = "pci IO space",
252  .start = 0x04,
253  .end = 0x0FFF,
254  .flags = IORESOURCE_IO /* I/O space */
255 };
256 
257 /*****************************************************************************
258  *
259  * STRUCT: pci_mem_resource
260  * _________________________________________________________________________
261  *
262  * DESCRIPTION: Defines the address range that pciauto() will use to
263  * assign to the memory BARs of PCI devices.
264  *
265  * The .start and .end values are dependent upon how address
266  * translation is performed by the OATRAN regiser.
267  *
268  * The values to use for .start and .end are the values
269  * in the form they appear on the PCI bus AFTER MSP7120 has
270  * performed OATRAN address translation.
271  *
272  * ELEMENTS:
273  * name - String used for a meaningful name.
274  *
275  * start - Start address of MSP7120's memory space, as MSP7120 presents
276  * the address on the PCI bus.
277  *
278  * end - End address of MSP7120's memory space, as MSP7120 presents
279  * the address on the PCI bus.
280  *
281  * flags - Attributes indicating the type of resource. In this case,
282  * indicate memory space.
283  *
284  ****************************************************************************/
285 static struct resource pci_mem_resource = {
286  .name = "pci memory space",
287  .start = MSP_PCI_SPACE_BASE,
288  .end = MSP_PCI_SPACE_END,
289  .flags = IORESOURCE_MEM /* memory space */
290 };
291 
292 /*****************************************************************************
293  *
294  * FUNCTION: bpci_interrupt
295  * _________________________________________________________________________
296  *
297  * DESCRIPTION: PCI status interrupt handler. Updates the count of how
298  * many times each status bit has been set, then clears
299  * the status bits. If the appropriate macros are defined,
300  * these counts can be viewed via the /proc filesystem.
301  *
302  * INPUTS: irq - unused
303  * dev_id - unused
304  * pt_regs - unused
305  *
306  * OUTPUTS: none
307  *
308  * RETURNS: PCIBIOS_SUCCESSFUL - success
309  *
310  ****************************************************************************/
311 static irqreturn_t bpci_interrupt(int irq, void *dev_id)
312 {
313  struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
314  unsigned int stat = preg->if_status;
315 
316 #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
317  int i;
318  for (i = 0; i < 32; ++i) {
319  if ((1 << i) & stat)
320  ++pci_int_count[i];
321  }
322 #endif /* PROC_FS && PCI_COUNTERS */
323 
324  /* printk("PCI ISR: Status=%08X\n", stat); */
325 
326  /* write to clear all asserted interrupts */
327  preg->if_status = stat;
328 
329  return IRQ_HANDLED;
330 }
331 
332 /*****************************************************************************
333  *
334  * FUNCTION: msp_pcibios_config_access
335  * _________________________________________________________________________
336  *
337  * DESCRIPTION: Performs a PCI configuration access (rd or wr), then
338  * checks that the access succeeded by querying MSP7120's
339  * PCI status bits.
340  *
341  * INPUTS:
342  * access_type - kind of PCI configuration cycle to perform
343  * (read or write). Legal values are
344  * PCI_ACCESS_WRITE and PCI_ACCESS_READ.
345  *
346  * bus - pointer to the bus number of the device to
347  * be targeted for the configuration cycle.
348  * The only element of the pci_bus structure
349  * used is bus->number. This argument determines
350  * if the configuration access will be Type 0 or
351  * Type 1. Since MSP7120 assumes itself to be the
352  * PCI Host, any non-zero bus->number generates
353  * a Type 1 access.
354  *
355  * devfn - this is an 8-bit field. The lower three bits
356  * specify the function number of the device to
357  * be targeted for the configuration cycle, with
358  * all three-bit combinations being legal. The
359  * upper five bits specify the device number,
360  * with legal values being 10 to 31.
361  *
362  * where - address within the Configuration Header
363  * space to access.
364  *
365  * data - for write accesses, contains the data to
366  * write.
367  *
368  * OUTPUTS:
369  * data - for read accesses, contains the value read.
370  *
371  * RETURNS: PCIBIOS_SUCCESSFUL - success
372  * -1 - access failure
373  *
374  ****************************************************************************/
375 int msp_pcibios_config_access(unsigned char access_type,
376  struct pci_bus *bus,
377  unsigned int devfn,
378  unsigned char where,
379  u32 *data)
380 {
381  struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
382  unsigned char bus_num = bus->number;
383  unsigned char dev_fn = (unsigned char)devfn;
384  unsigned long flags;
385  unsigned long intr;
386  unsigned long value;
387  static char pciirqflag;
388  int ret;
389 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
390  unsigned int vpe_status;
391 #endif
392 
393 #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
394  if (proc_init == 0) {
395  pci_proc_init();
396  proc_init = ~0;
397  }
398 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
399 
400  /*
401  * Just the first time this function invokes, allocate
402  * an interrupt line for PCI host status interrupts. The
403  * allocation assigns an interrupt handler to the interrupt.
404  */
405  if (pciirqflag == 0) {
406  ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
407  bpci_interrupt,
408  IRQF_SHARED,
409  "PMC MSP PCI Host",
410  preg);
411  if (ret != 0)
412  return ret;
413  pciirqflag = ~0;
414  }
415 
416 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
417  local_irq_save(flags);
418  vpe_status = dvpe();
419 #else
420  spin_lock_irqsave(&bpci_lock, flags);
421 #endif
422 
423  /*
424  * Clear PCI cause register bits.
425  *
426  * In Polo, the PCI Host had a dedicated DMA called the
427  * Block Copy (not to be confused with the general purpose Block
428  * Copy Engine block). There appear to have been special interrupts
429  * for this Block Copy, called Block Copy 0 Fault (BC0F) and
430  * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
431  * dedicated Block Copy block, so these two interrupts are now
432  * marked reserved. In case the Block Copy is resurrected in a
433  * future design, maintain the code that treats these two interrupts
434  * specially.
435  *
436  * Write to clear all interrupts in the PCI status register, aside
437  * from BC0F and BC1F.
438  */
440 
441  /* Setup address that is to appear on PCI bus */
443  (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
444  (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
445  (where & 0xFC);
446 
447  /* IF access is a PCI configuration write */
448  if (access_type == PCI_ACCESS_WRITE) {
449  value = cpu_to_le32(*data);
451  } else {
452  /* ELSE access is a PCI configuration read */
454  *data = value;
455  }
456 
457  /*
458  * Check if the PCI configuration cycle (rd or wr) succeeded, by
459  * checking the status bits for errors like master or target abort.
460  */
461  intr = preg->if_status;
462 
463  /* Clear config access */
464  preg->config_addr = 0;
465 
466  /* IF error occurred */
467  if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) {
468  /* Clear status bits */
470 
471 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
472  evpe(vpe_status);
473  local_irq_restore(flags);
474 #else
475  spin_unlock_irqrestore(&bpci_lock, flags);
476 #endif
477 
478  return -1;
479  }
480 
481 #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
482  evpe(vpe_status);
483  local_irq_restore(flags);
484 #else
485  spin_unlock_irqrestore(&bpci_lock, flags);
486 #endif
487 
488  return PCIBIOS_SUCCESSFUL;
489 }
490 
491 /*****************************************************************************
492  *
493  * FUNCTION: msp_pcibios_read_config_byte
494  * _________________________________________________________________________
495  *
496  * DESCRIPTION: Read a byte from PCI configuration address spac
497  * Since the hardware can't address 8 bit chunks
498  * directly, read a 32-bit chunk, then mask off extraneous
499  * bits.
500  *
501  * INPUTS bus - structure containing attributes for the PCI bus
502  * that the read is destined for.
503  * devfn - device/function combination that the read is
504  * destined for.
505  * where - register within the Configuration Header space
506  * to access.
507  *
508  * OUTPUTS val - read data
509  *
510  * RETURNS: PCIBIOS_SUCCESSFUL - success
511  * -1 - read access failure
512  *
513  ****************************************************************************/
514 static int
515 msp_pcibios_read_config_byte(struct pci_bus *bus,
516  unsigned int devfn,
517  int where,
518  u32 *val)
519 {
520  u32 data = 0;
521 
522  /*
523  * If the config access did not complete normally (e.g., underwent
524  * master abort) do the PCI compliant thing, which is to supply an
525  * all ones value.
526  */
528  where, &data)) {
529  *val = 0xFFFFFFFF;
530  return -1;
531  }
532 
533  *val = (data >> ((where & 3) << 3)) & 0x0ff;
534 
535  return PCIBIOS_SUCCESSFUL;
536 }
537 
538 /*****************************************************************************
539  *
540  * FUNCTION: msp_pcibios_read_config_word
541  * _________________________________________________________________________
542  *
543  * DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
544  * Since the hardware can't address 16 bit chunks
545  * directly, read a 32-bit chunk, then mask off extraneous
546  * bits.
547  *
548  * INPUTS bus - structure containing attributes for the PCI bus
549  * that the read is destined for.
550  * devfn - device/function combination that the read is
551  * destined for.
552  * where - register within the Configuration Header space
553  * to access.
554  *
555  * OUTPUTS val - read data
556  *
557  * RETURNS: PCIBIOS_SUCCESSFUL - success
558  * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
559  * -1 - read access failure
560  *
561  ****************************************************************************/
562 static int
563 msp_pcibios_read_config_word(struct pci_bus *bus,
564  unsigned int devfn,
565  int where,
566  u32 *val)
567 {
568  u32 data = 0;
569 
570  /* if (where & 1) */ /* Commented out non-compliant code.
571  * Should allow word access to configuration
572  * registers, with only exception being when
573  * the word access would wrap around into
574  * the next dword.
575  */
576  if ((where & 3) == 3) {
577  *val = 0xFFFFFFFF;
579  }
580 
581  /*
582  * If the config access did not complete normally (e.g., underwent
583  * master abort) do the PCI compliant thing, which is to supply an
584  * all ones value.
585  */
587  where, &data)) {
588  *val = 0xFFFFFFFF;
589  return -1;
590  }
591 
592  *val = (data >> ((where & 3) << 3)) & 0x0ffff;
593 
594  return PCIBIOS_SUCCESSFUL;
595 }
596 
597 /*****************************************************************************
598  *
599  * FUNCTION: msp_pcibios_read_config_dword
600  * _________________________________________________________________________
601  *
602  * DESCRIPTION: Read a double word (32 bits) from PCI configuration
603  * address space.
604  *
605  * INPUTS bus - structure containing attributes for the PCI bus
606  * that the read is destined for.
607  * devfn - device/function combination that the read is
608  * destined for.
609  * where - register within the Configuration Header space
610  * to access.
611  *
612  * OUTPUTS val - read data
613  *
614  * RETURNS: PCIBIOS_SUCCESSFUL - success
615  * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
616  * -1 - read access failure
617  *
618  ****************************************************************************/
619 static int
620 msp_pcibios_read_config_dword(struct pci_bus *bus,
621  unsigned int devfn,
622  int where,
623  u32 *val)
624 {
625  u32 data = 0;
626 
627  /* Address must be dword aligned. */
628  if (where & 3) {
629  *val = 0xFFFFFFFF;
631  }
632 
633  /*
634  * If the config access did not complete normally (e.g., underwent
635  * master abort) do the PCI compliant thing, which is to supply an
636  * all ones value.
637  */
639  where, &data)) {
640  *val = 0xFFFFFFFF;
641  return -1;
642  }
643 
644  *val = data;
645 
646  return PCIBIOS_SUCCESSFUL;
647 }
648 
649 /*****************************************************************************
650  *
651  * FUNCTION: msp_pcibios_write_config_byte
652  * _________________________________________________________________________
653  *
654  * DESCRIPTION: Write a byte to PCI configuration address space.
655  * Since the hardware can't address 8 bit chunks
656  * directly, a read-modify-write is performed.
657  *
658  * INPUTS bus - structure containing attributes for the PCI bus
659  * that the write is destined for.
660  * devfn - device/function combination that the write is
661  * destined for.
662  * where - register within the Configuration Header space
663  * to access.
664  * val - value to write
665  *
666  * OUTPUTS none
667  *
668  * RETURNS: PCIBIOS_SUCCESSFUL - success
669  * -1 - write access failure
670  *
671  ****************************************************************************/
672 static int
673 msp_pcibios_write_config_byte(struct pci_bus *bus,
674  unsigned int devfn,
675  int where,
676  u8 val)
677 {
678  u32 data = 0;
679 
680  /* read config space */
682  where, &data))
683  return -1;
684 
685  /* modify the byte within the dword */
686  data = (data & ~(0xff << ((where & 3) << 3))) |
687  (val << ((where & 3) << 3));
688 
689  /* write back the full dword */
691  where, &data))
692  return -1;
693 
694  return PCIBIOS_SUCCESSFUL;
695 }
696 
697 /*****************************************************************************
698  *
699  * FUNCTION: msp_pcibios_write_config_word
700  * _________________________________________________________________________
701  *
702  * DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
703  * Since the hardware can't address 16 bit chunks
704  * directly, a read-modify-write is performed.
705  *
706  * INPUTS bus - structure containing attributes for the PCI bus
707  * that the write is destined for.
708  * devfn - device/function combination that the write is
709  * destined for.
710  * where - register within the Configuration Header space
711  * to access.
712  * val - value to write
713  *
714  * OUTPUTS none
715  *
716  * RETURNS: PCIBIOS_SUCCESSFUL - success
717  * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
718  * -1 - write access failure
719  *
720  ****************************************************************************/
721 static int
722 msp_pcibios_write_config_word(struct pci_bus *bus,
723  unsigned int devfn,
724  int where,
725  u16 val)
726 {
727  u32 data = 0;
728 
729  /* Fixed non-compliance: if (where & 1) */
730  if ((where & 3) == 3)
732 
733  /* read config space */
735  where, &data))
736  return -1;
737 
738  /* modify the word within the dword */
739  data = (data & ~(0xffff << ((where & 3) << 3))) |
740  (val << ((where & 3) << 3));
741 
742  /* write back the full dword */
744  where, &data))
745  return -1;
746 
747  return PCIBIOS_SUCCESSFUL;
748 }
749 
750 /*****************************************************************************
751  *
752  * FUNCTION: msp_pcibios_write_config_dword
753  * _________________________________________________________________________
754  *
755  * DESCRIPTION: Write a double word (32-bits) to PCI configuration address
756  * space.
757  *
758  * INPUTS bus - structure containing attributes for the PCI bus
759  * that the write is destined for.
760  * devfn - device/function combination that the write is
761  * destined for.
762  * where - register within the Configuration Header space
763  * to access.
764  * val - value to write
765  *
766  * OUTPUTS none
767  *
768  * RETURNS: PCIBIOS_SUCCESSFUL - success
769  * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
770  * -1 - write access failure
771  *
772  ****************************************************************************/
773 static int
774 msp_pcibios_write_config_dword(struct pci_bus *bus,
775  unsigned int devfn,
776  int where,
777  u32 val)
778 {
779  /* check that address is dword aligned */
780  if (where & 3)
782 
783  /* perform write */
785  where, &val))
786  return -1;
787 
788  return PCIBIOS_SUCCESSFUL;
789 }
790 
791 /*****************************************************************************
792  *
793  * FUNCTION: msp_pcibios_read_config
794  * _________________________________________________________________________
795  *
796  * DESCRIPTION: Interface the PCI configuration read request with
797  * the appropriate function, based on how many bytes
798  * the read request is.
799  *
800  * INPUTS bus - structure containing attributes for the PCI bus
801  * that the write is destined for.
802  * devfn - device/function combination that the write is
803  * destined for.
804  * where - register within the Configuration Header space
805  * to access.
806  * size - in units of bytes, should be 1, 2, or 4.
807  *
808  * OUTPUTS val - value read, with any extraneous bytes masked
809  * to zero.
810  *
811  * RETURNS: PCIBIOS_SUCCESSFUL - success
812  * -1 - failure
813  *
814  ****************************************************************************/
815 int
817  unsigned int devfn,
818  int where,
819  int size,
820  u32 *val)
821 {
822  if (size == 1) {
823  if (msp_pcibios_read_config_byte(bus, devfn, where, val)) {
824  return -1;
825  }
826  } else if (size == 2) {
827  if (msp_pcibios_read_config_word(bus, devfn, where, val)) {
828  return -1;
829  }
830  } else if (size == 4) {
831  if (msp_pcibios_read_config_dword(bus, devfn, where, val)) {
832  return -1;
833  }
834  } else {
835  *val = 0xFFFFFFFF;
836  return -1;
837  }
838 
839  return PCIBIOS_SUCCESSFUL;
840 }
841 
842 /*****************************************************************************
843  *
844  * FUNCTION: msp_pcibios_write_config
845  * _________________________________________________________________________
846  *
847  * DESCRIPTION: Interface the PCI configuration write request with
848  * the appropriate function, based on how many bytes
849  * the read request is.
850  *
851  * INPUTS bus - structure containing attributes for the PCI bus
852  * that the write is destined for.
853  * devfn - device/function combination that the write is
854  * destined for.
855  * where - register within the Configuration Header space
856  * to access.
857  * size - in units of bytes, should be 1, 2, or 4.
858  * val - value to write
859  *
860  * OUTPUTS: none
861  *
862  * RETURNS: PCIBIOS_SUCCESSFUL - success
863  * -1 - failure
864  *
865  ****************************************************************************/
866 int
868  unsigned int devfn,
869  int where,
870  int size,
871  u32 val)
872 {
873  if (size == 1) {
874  if (msp_pcibios_write_config_byte(bus, devfn,
875  where, (u8)(0xFF & val))) {
876  return -1;
877  }
878  } else if (size == 2) {
879  if (msp_pcibios_write_config_word(bus, devfn,
880  where, (u16)(0xFFFF & val))) {
881  return -1;
882  }
883  } else if (size == 4) {
884  if (msp_pcibios_write_config_dword(bus, devfn, where, val)) {
885  return -1;
886  }
887  } else {
888  return -1;
889  }
890 
891  return PCIBIOS_SUCCESSFUL;
892 }
893 
894 /*****************************************************************************
895  *
896  * STRUCTURE: msp_pci_ops
897  * _________________________________________________________________________
898  *
899  * DESCRIPTION: structure to abstract the hardware specific PCI
900  * configuration accesses.
901  *
902  * ELEMENTS:
903  * read - function for Linux to generate PCI Configuration reads.
904  * write - function for Linux to generate PCI Configuration writes.
905  *
906  ****************************************************************************/
908  .read = msp_pcibios_read_config,
909  .write = msp_pcibios_write_config
910 };
911 
912 /*****************************************************************************
913  *
914  * STRUCTURE: msp_pci_controller
915  * _________________________________________________________________________
916  *
917  * Describes the attributes of the MSP7120 PCI Host Controller
918  *
919  * ELEMENTS:
920  * pci_ops - abstracts the hardware specific PCI configuration
921  * accesses.
922  *
923  * mem_resource - address range pciauto() uses to assign to PCI device
924  * memory BARs.
925  *
926  * mem_offset - offset between how MSP7120 outbound PCI memory
927  * transaction addresses appear on the PCI bus and how Linux
928  * wants to configure memory BARs of the PCI devices.
929  * MSP7120 does nothing funky, so just set to zero.
930  *
931  * io_resource - address range pciauto() uses to assign to PCI device
932  * I/O BARs.
933  *
934  * io_offset - offset between how MSP7120 outbound PCI I/O
935  * transaction addresses appear on the PCI bus and how
936  * Linux defaults to configure I/O BARs of the PCI devices.
937  * MSP7120 maps outbound I/O accesses into the bottom
938  * bottom 4K of PCI address space (and ignores OATRAN).
939  * Since the Linux default is to configure I/O BARs to the
940  * bottom 4K, no special offset is needed. Just set to zero.
941  *
942  ****************************************************************************/
943 static struct pci_controller msp_pci_controller = {
944  .pci_ops = &msp_pci_ops,
945  .mem_resource = &pci_mem_resource,
946  .mem_offset = 0,
947  .io_map_base = MSP_PCI_IOSPACE_BASE,
948  .io_resource = &pci_io_resource,
949  .io_offset = 0
950 };
951 
952 /*****************************************************************************
953  *
954  * FUNCTION: msp_pci_init
955  * _________________________________________________________________________
956  *
957  * DESCRIPTION: Initialize the PCI Host Controller and register it with
958  * Linux so Linux can seize control of the PCI bus.
959  *
960  ****************************************************************************/
962 {
963  struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
964  u32 id;
965 
966  /* Extract Device ID */
967  id = read_reg32(PCI_JTAG_DEVID_REG, 0xFFFF) >> 12;
968 
969  /* Check if JTAG ID identifies MSP7120 */
970  if (!MSP_HAS_PCI(id)) {
971  printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id);
972  goto no_pci;
973  }
974 
975  /*
976  * Enable flushing of the PCI-SDRAM queue upon a read
977  * of the SDRAM's Memory Configuration Register.
978  */
979  *(unsigned long *)QFLUSH_REG_1 = 3;
980 
981  /* Configure PCI Host Controller. */
982  preg->if_status = ~0; /* Clear cause register bits */
983  preg->config_addr = 0; /* Clear config access */
984  preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */
985  preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */
986 
987  /* configure so inb(), outb(), and family are functional */
988  set_io_port_base(MSP_PCI_IOSPACE_BASE);
989 
990  /* Tell Linux the details of the MSP7120 PCI Host Controller */
991  register_pci_controller(&msp_pci_controller);
992 
993  return;
994 
995 no_pci:
996  /* Disable PCI channel */
997  printk(KERN_WARNING "PCI: no host PCI bus detected\n");
998 }