Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
ops-tx4927.c
Go to the documentation of this file.
1 /*
2  * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
3  *
4  * Based on linux/arch/mips/pci/ops-tx4938.c,
5  * linux/arch/mips/pci/fixup-rbtx4938.c,
6  * linux/arch/mips/txx9/rbtx4938/setup.c,
7  * and RBTX49xx patch from CELF patch archive.
8  *
9  * 2003-2005 (c) MontaVista Software, Inc.
10  * Copyright (C) 2004 by Ralf Baechle ([email protected])
11  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
12  *
13  * This program is free software; you can redistribute it and/or modify it
14  * under the terms of the GNU General Public License as published by the
15  * Free Software Foundation; either version 2 of the License, or (at your
16  * option) any later version.
17  */
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <asm/txx9/pci.h>
22 #include <asm/txx9/tx4927pcic.h>
23 
24 static struct {
25  struct pci_controller *channel;
26  struct tx4927_pcic_reg __iomem *pcicptr;
27 } pcicptrs[2]; /* TX4938 has 2 pcic */
28 
29 static void __init set_tx4927_pcicptr(struct pci_controller *channel,
30  struct tx4927_pcic_reg __iomem *pcicptr)
31 {
32  int i;
33 
34  for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
35  if (pcicptrs[i].channel == channel) {
36  pcicptrs[i].pcicptr = pcicptr;
37  return;
38  }
39  }
40  for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
41  if (!pcicptrs[i].channel) {
42  pcicptrs[i].channel = channel;
43  pcicptrs[i].pcicptr = pcicptr;
44  return;
45  }
46  }
47  BUG();
48 }
49 
50 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
51  struct pci_controller *channel)
52 {
53  int i;
54 
55  for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
56  if (pcicptrs[i].channel == channel)
57  return pcicptrs[i].pcicptr;
58  }
59  return NULL;
60 }
61 
62 static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
63  struct tx4927_pcic_reg __iomem *pcicptr)
64 {
65  if (bus->parent == NULL &&
66  devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
67  return -1;
68  __raw_writel(((bus->number & 0xff) << 0x10)
69  | ((devfn & 0xff) << 0x08) | (where & 0xfc)
70  | (bus->parent ? 1 : 0),
71  &pcicptr->g2pcfgadrs);
72  /* clear M_ABORT and Disable M_ABORT Int. */
73  __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
74  | (PCI_STATUS_REC_MASTER_ABORT << 16),
75  &pcicptr->pcistatus);
76  return 0;
77 }
78 
79 static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
80 {
81  int code = PCIBIOS_SUCCESSFUL;
82 
83  /* wait write cycle completion before checking error status */
84  while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
85  ;
86  if (__raw_readl(&pcicptr->pcistatus)
87  & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
88  __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
89  | (PCI_STATUS_REC_MASTER_ABORT << 16),
90  &pcicptr->pcistatus);
91  /* flush write buffer */
92  iob();
93  code = PCIBIOS_DEVICE_NOT_FOUND;
94  }
95  return code;
96 }
97 
98 static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
99 {
100 #ifdef __BIG_ENDIAN
101  offset ^= 3;
102 #endif
103  return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
104 }
105 static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
106 {
107 #ifdef __BIG_ENDIAN
108  offset ^= 2;
109 #endif
110  return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
111 }
112 static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
113 {
114  return __raw_readl(&pcicptr->g2pcfgdata);
115 }
116 static void icd_writeb(u8 val, int offset,
117  struct tx4927_pcic_reg __iomem *pcicptr)
118 {
119 #ifdef __BIG_ENDIAN
120  offset ^= 3;
121 #endif
122  __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
123 }
124 static void icd_writew(u16 val, int offset,
125  struct tx4927_pcic_reg __iomem *pcicptr)
126 {
127 #ifdef __BIG_ENDIAN
128  offset ^= 2;
129 #endif
130  __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
131 }
132 static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
133 {
134  __raw_writel(val, &pcicptr->g2pcfgdata);
135 }
136 
137 static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
138 {
139  struct pci_controller *channel = bus->sysdata;
140  return get_tx4927_pcicptr(channel);
141 }
142 
143 static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
144  int where, int size, u32 *val)
145 {
146  struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
147 
148  if (mkaddr(bus, devfn, where, pcicptr)) {
149  *val = 0xffffffff;
150  return -1;
151  }
152  switch (size) {
153  case 1:
154  *val = icd_readb(where & 3, pcicptr);
155  break;
156  case 2:
157  *val = icd_readw(where & 3, pcicptr);
158  break;
159  default:
160  *val = icd_readl(pcicptr);
161  }
162  return check_abort(pcicptr);
163 }
164 
165 static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
166  int where, int size, u32 val)
167 {
168  struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
169 
170  if (mkaddr(bus, devfn, where, pcicptr))
171  return -1;
172  switch (size) {
173  case 1:
174  icd_writeb(val, where & 3, pcicptr);
175  break;
176  case 2:
177  icd_writew(val, where & 3, pcicptr);
178  break;
179  default:
180  icd_writel(val, pcicptr);
181  }
182  return check_abort(pcicptr);
183 }
184 
185 static struct pci_ops tx4927_pci_ops = {
186  .read = tx4927_pci_config_read,
187  .write = tx4927_pci_config_write,
188 };
189 
190 static struct {
191  u8 trdyto;
192  u8 retryto;
193  u16 gbwc;
194 } tx4927_pci_opts __devinitdata = {
195  .trdyto = 0,
196  .retryto = 0,
197  .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
198 };
199 
200 char *__devinit tx4927_pcibios_setup(char *str)
201 {
202  unsigned long val;
203 
204  if (!strncmp(str, "trdyto=", 7)) {
205  if (strict_strtoul(str + 7, 0, &val) == 0)
206  tx4927_pci_opts.trdyto = val;
207  return NULL;
208  }
209  if (!strncmp(str, "retryto=", 8)) {
210  if (strict_strtoul(str + 8, 0, &val) == 0)
211  tx4927_pci_opts.retryto = val;
212  return NULL;
213  }
214  if (!strncmp(str, "gbwc=", 5)) {
215  if (strict_strtoul(str + 5, 0, &val) == 0)
216  tx4927_pci_opts.gbwc = val;
217  return NULL;
218  }
219  return str;
220 }
221 
222 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
223  struct pci_controller *channel, int extarb)
224 {
225  int i;
226  unsigned long flags;
227 
228  set_tx4927_pcicptr(channel, pcicptr);
229 
230  if (!channel->pci_ops)
231  printk(KERN_INFO
232  "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
233  __raw_readl(&pcicptr->pciid) >> 16,
234  __raw_readl(&pcicptr->pciid) & 0xffff,
235  __raw_readl(&pcicptr->pciccrev) & 0xff,
236  extarb ? "External" : "Internal");
237  channel->pci_ops = &tx4927_pci_ops;
238 
239  local_irq_save(flags);
240 
241  /* Disable All Initiator Space */
242  __raw_writel(__raw_readl(&pcicptr->pciccfg)
243  & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
244  | TX4927_PCIC_PCICCFG_G2PMEN(1)
245  | TX4927_PCIC_PCICCFG_G2PMEN(2)
246  | TX4927_PCIC_PCICCFG_G2PIOEN),
247  &pcicptr->pciccfg);
248 
249  /* GB->PCI mappings */
250  __raw_writel((channel->io_resource->end - channel->io_resource->start)
251  >> 4,
252  &pcicptr->g2piomask);
253  ____raw_writeq((channel->io_resource->start +
254  channel->io_map_base - IO_BASE) |
255 #ifdef __BIG_ENDIAN
256  TX4927_PCIC_G2PIOGBASE_ECHG
257 #else
258  TX4927_PCIC_G2PIOGBASE_BSDIS
259 #endif
260  , &pcicptr->g2piogbase);
261  ____raw_writeq(channel->io_resource->start - channel->io_offset,
262  &pcicptr->g2piopbase);
263  for (i = 0; i < 3; i++) {
264  __raw_writel(0, &pcicptr->g2pmmask[i]);
265  ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
266  ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
267  }
268  if (channel->mem_resource->end) {
269  __raw_writel((channel->mem_resource->end
270  - channel->mem_resource->start) >> 4,
271  &pcicptr->g2pmmask[0]);
272  ____raw_writeq(channel->mem_resource->start |
273 #ifdef __BIG_ENDIAN
274  TX4927_PCIC_G2PMnGBASE_ECHG
275 #else
276  TX4927_PCIC_G2PMnGBASE_BSDIS
277 #endif
278  , &pcicptr->g2pmgbase[0]);
279  ____raw_writeq(channel->mem_resource->start -
280  channel->mem_offset,
281  &pcicptr->g2pmpbase[0]);
282  }
283  /* PCI->GB mappings (I/O 256B) */
284  __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
285  ____raw_writeq(0, &pcicptr->p2giogbase);
286  /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
287  __raw_writel(0, &pcicptr->p2gm0plbase);
288  __raw_writel(0, &pcicptr->p2gm0pubase);
289  ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
290 #ifdef __BIG_ENDIAN
291  TX4927_PCIC_P2GMnGBASE_TECHG
292 #else
293  TX4927_PCIC_P2GMnGBASE_TBSDIS
294 #endif
295  , &pcicptr->p2gmgbase[0]);
296  /* PCI->GB mappings (MEM 16MB) */
297  __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
298  __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
299  ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
300  /* PCI->GB mappings (MEM 1MB) */
301  __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
302  ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
303 
304  /* Clear all (including IRBER) except for GBWC */
305  __raw_writel((tx4927_pci_opts.gbwc << 16)
306  & TX4927_PCIC_PCICCFG_GBWC_MASK,
307  &pcicptr->pciccfg);
308  /* Enable Initiator Memory Space */
309  if (channel->mem_resource->end)
310  __raw_writel(__raw_readl(&pcicptr->pciccfg)
311  | TX4927_PCIC_PCICCFG_G2PMEN(0),
312  &pcicptr->pciccfg);
313  /* Enable Initiator I/O Space */
314  if (channel->io_resource->end)
315  __raw_writel(__raw_readl(&pcicptr->pciccfg)
316  | TX4927_PCIC_PCICCFG_G2PIOEN,
317  &pcicptr->pciccfg);
318  /* Enable Initiator Config */
319  __raw_writel(__raw_readl(&pcicptr->pciccfg)
320  | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
321  &pcicptr->pciccfg);
322 
323  /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
324  __raw_writel(0, &pcicptr->pcicfg1);
325 
326  __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
327  | (tx4927_pci_opts.trdyto & 0xff)
328  | ((tx4927_pci_opts.retryto & 0xff) << 8),
329  &pcicptr->g2ptocnt);
330 
331  /* Clear All Local Bus Status */
332  __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
333  /* Enable All Local Bus Interrupts */
334  __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
335  /* Clear All Initiator Status */
336  __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
337  /* Enable All Initiator Interrupts */
338  __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
339  /* Clear All PCI Status Error */
340  __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
341  | (TX4927_PCIC_PCISTATUS_ALL << 16),
342  &pcicptr->pcistatus);
343  /* Enable All PCI Status Error Interrupts */
344  __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
345 
346  if (!extarb) {
347  /* Reset Bus Arbiter */
348  __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
349  __raw_writel(0, &pcicptr->pbabm);
350  /* Enable Bus Arbiter */
351  __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
352  }
353 
354  __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
355  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
356  &pcicptr->pcistatus);
357  local_irq_restore(flags);
358 
359  printk(KERN_DEBUG
360  "PCI: COMMAND=%04x,PCIMASK=%04x,"
361  "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
362  __raw_readl(&pcicptr->pcistatus) & 0xffff,
363  __raw_readl(&pcicptr->pcimask) & 0xffff,
364  __raw_readl(&pcicptr->g2ptocnt) & 0xff,
365  (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
366  (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
367 }
368 
369 static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
370 {
371  __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
372  __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
373  __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
374  static struct {
375  __u32 flag;
376  const char *str;
377  } pcistat_tbl[] = {
378  { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
379  { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
380  { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
381  { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
382  { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
383  { PCI_STATUS_PARITY, "MasterParityError" },
384  }, g2pstat_tbl[] = {
385  { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
386  { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
387  }, pcicstat_tbl[] = {
388  { TX4927_PCIC_PCICSTATUS_PME, "PME" },
389  { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
390  { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
391  { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
392  { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
393  { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
394  { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
395  { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
396  };
397  int i, cont;
398 
399  printk(KERN_ERR "");
400  if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
401  printk(KERN_CONT "pcistat:%04x(", pcistatus);
402  for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
403  if (pcistatus & pcistat_tbl[i].flag)
404  printk(KERN_CONT "%s%s",
405  cont++ ? " " : "", pcistat_tbl[i].str);
406  printk(KERN_CONT ") ");
407  }
408  if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
409  printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
410  for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
411  if (g2pstatus & g2pstat_tbl[i].flag)
412  printk(KERN_CONT "%s%s",
413  cont++ ? " " : "", g2pstat_tbl[i].str);
414  printk(KERN_CONT ") ");
415  }
416  if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
417  printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
418  for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
419  if (pcicstatus & pcicstat_tbl[i].flag)
420  printk(KERN_CONT "%s%s",
421  cont++ ? " " : "", pcicstat_tbl[i].str);
422  printk(KERN_CONT ")");
423  }
424  printk(KERN_CONT "\n");
425 }
426 
427 void tx4927_report_pcic_status(void)
428 {
429  int i;
430 
431  for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
432  if (pcicptrs[i].pcicptr)
433  tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
434  }
435 }
436 
437 static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
438 {
439  int i;
440  __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
441 
442  printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
443  for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
444  if (i % 32 == 0) {
445  printk(KERN_CONT "\n");
446  printk(KERN_INFO "%04x:", i);
447  }
448  /* skip registers with side-effects */
449  if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
450  || i == offsetof(struct tx4927_pcic_reg, g2pspc)
451  || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
452  || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
453  printk(KERN_CONT " XXXXXXXX");
454  continue;
455  }
456  printk(KERN_CONT " %08x", __raw_readl(preg));
457  }
458  printk(KERN_CONT "\n");
459 }
460 
461 void tx4927_dump_pcic_settings(void)
462 {
463  int i;
464 
465  for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
466  if (pcicptrs[i].pcicptr)
467  tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
468  }
469 }
470 
471 irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
472 {
473  struct pt_regs *regs = get_irq_regs();
474  struct tx4927_pcic_reg __iomem *pcicptr =
475  (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
476 
477  if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
478  printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
479  (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
480  tx4927_report_pcic_status1(pcicptr);
481  }
482  if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
483  /* clear all pci errors */
484  __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
485  | (TX4927_PCIC_PCISTATUS_ALL << 16),
486  &pcicptr->pcistatus);
487  __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
488  __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
489  __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
490  return IRQ_HANDLED;
491  }
492  console_verbose();
493  tx4927_dump_pcic_settings1(pcicptr);
494  panic("PCI error.");
495 }
496 
497 #ifdef CONFIG_TOSHIBA_FPCIB0
498 static void __devinit tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
499 {
500  struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
501 
502  if (!pcicptr)
503  return;
504  if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
505  /* Reset Bus Arbiter */
506  __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
507  /*
508  * swap reqBP and reqXP (raise priority of SLC90E66).
509  * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
510  * PCI Backplane board.
511  */
512  __raw_writel(0x72543610, &pcicptr->pbareqport);
513  __raw_writel(0, &pcicptr->pbabm);
514  /* Use Fixed ParkMaster (required by SLC90E66) */
515  __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
516  /* Enable Bus Arbiter */
517  __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
518  TX4927_PCIC_PBACFG_PBAEN,
519  &pcicptr->pbacfg);
520  printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
521  __raw_readl(&pcicptr->pbareqport));
522  }
523 }
524 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
526  tx4927_quirk_slc90e66_bridge);
527 #endif
Generated on Thu Jan 10 2013 13:12:00 for Linux Kernel by   doxygen 1.8.2