19 #include <linux/export.h>
23 #include <asm/div64.h>
43 wiphy_debug(priv->
hw->wiphy,
"/ --- tx queue dump (%d entries) ---\n",
47 skb_queue_walk(&priv->
tx_queue, skb) {
48 info = IEEE80211_SKB_CB(skb);
50 hdr = (
void *) skb->
data;
54 "| [%02d] => [skb:%p skb_len:0x%04x "
55 "hdr:{flags:%02x len:%04x req_id:%04x type:%02x} "
56 "mem:{start:%04x end:%04x, free:%d}]\n",
63 largest_hole =
max(largest_hole,
free);
66 largest_hole =
max(largest_hole,
free);
68 "\\ --- [free: %d], largest free block: %d ---\n",
70 spin_unlock_irqrestore(&priv->
tx_queue.lock, flags);
94 info = IEEE80211_SKB_CB(skb);
105 spin_unlock_irqrestore(&priv->
tx_queue.lock, flags);
109 skb_queue_walk(&priv->
tx_queue, entry) {
111 info = IEEE80211_SKB_CB(entry);
115 if (!target_skb && hole_size >=
len) {
116 target_skb = entry->
prev;
126 if (!skb_queue_empty(&priv->
tx_queue)) {
127 info = IEEE80211_SKB_CB(target_skb);
132 spin_unlock_irqrestore(&priv->
tx_queue.lock, flags);
137 info = IEEE80211_SKB_CB(skb);
146 __skb_queue_after(&priv->
tx_queue, target_skb, skb);
147 spin_unlock_irqrestore(&priv->
tx_queue.lock, flags);
151 static void p54_tx_pending(
struct p54_common *priv)
160 ret = p54_assign_address(priv, skb);
164 priv->
tx(priv->
hw, skb);
167 static void p54_wake_queues(
struct p54_common *priv)
175 p54_tx_pending(priv);
178 for (i = 0; i < priv->
hw->queues; i++) {
186 static int p54_tx_qos_accounting_alloc(
struct p54_common *priv,
216 static void p54_tx_qos_accounting_free(
struct p54_common *priv,
234 p54_wake_queues(priv);
244 p54_tx_qos_accounting_free(priv, skb);
256 skb_queue_walk(&priv->
tx_queue, entry) {
260 __skb_unlink(entry, &priv->
tx_queue);
261 spin_unlock_irqrestore(&priv->
tx_queue.lock, flags);
262 p54_tx_qos_accounting_free(priv, entry);
266 spin_unlock_irqrestore(&priv->
tx_queue.lock, flags);
273 p54_tx_pending(priv);
276 static int p54_rssi_to_dbm(
struct p54_common *priv,
int rssi)
278 if (priv->
rxhw != 5) {
279 return ((rssi * priv->
cur_rssi->mul) / 64 +
285 return rssi / 2 - 110;
311 if (!ether_addr_equal(hdr->
addr3, priv->
bssid))
321 new_psm = ieee80211_check_tim(tim_ie, tim_len, priv->
aid);
355 if (hdr->
rate & 0x10)
358 rx_status->rate_idx = (rate < 4) ? 0 : rate - 4;
367 if (tsf32 < priv->tsf_low32)
375 header_len += hdr->
align[0];
380 p54_pspoll_workaround(priv, skb);
398 unsigned int pad = 0, frame_len;
401 entry = p54_find_and_unlink_skb(priv, hdr->
req_id);
405 frame_len = entry->
len;
406 info = IEEE80211_SKB_CB(entry);
429 status.ack_signal) != 20);
432 pad = entry_data->
align[0];
436 for (idx = 0; idx < 4; idx++) {
437 if (count >= info->
status.rates[idx].count) {
439 }
else if (count > 0) {
453 info->
status.ack_signal = p54_rssi_to_dbm(priv,
465 iv[1] = (iv[0] | 0x20) & 0x7f;
479 skb_pull(entry,
sizeof(*hdr) + pad +
sizeof(*entry_data));
483 static void p54_rx_eeprom_readback(
struct p54_common *priv,
493 if (priv->
fw_var >= 0x509) {
502 tmp = p54_find_and_unlink_skb(priv, hdr->
req_id);
513 unsigned int i, rssi,
tx, cca, dtime, dtotal, dcca, dtx, drssi,
unit;
520 if (tsf32 < priv->tsf_low32)
551 dtotal = dcca + drssi + dtx;
561 unit = dtime / dtotal;
596 tmp = p54_find_and_unlink_skb(priv, hdr->
req_id);
612 wiphy_info(priv->
hw->wiphy,
"radar (freq:%d MHz)\n", freq);
631 wiphy_info(priv->
hw->wiphy,
"received event:%x freq:%d\n",
643 p54_rx_frame_sent(priv, skb);
646 p54_rx_trap(priv, skb);
651 p54_rx_stats(priv, skb);
654 p54_rx_eeprom_readback(priv, skb);
658 "not handling 0x%02x type control frame\n",
672 return p54_rx_control(priv, skb);
682 bool *burst_possible)
687 *burst_possible =
true;
689 *burst_possible =
false;
702 switch (priv->
mode) {
782 u16 hdr_flags = 0, aid = 0;
786 u8 calculated_tries[4];
787 u8 nrates = 0, nremaining = 8;
788 bool burst_allowed =
false;
790 p54_tx_80211_header(priv, skb, info, control->
sta, &queue, &extra_len,
791 &hdr_flags, &aid, &burst_allowed);
793 if (p54_tx_qos_accounting_alloc(priv, skb, queue)) {
798 padding = (
unsigned long)(skb->
data - (
sizeof(*hdr) +
sizeof(*txhdr))) & 3;
827 cts_rate = info->
control.rts_cts_rate_idx;
833 if (info->
control.rates[i].idx < 0)
839 for (i = 0; i < nrates; i++) {
845 calculated_tries[
i] =
min_t(
int, ((15 >> nrates) | 1) + 1,
847 nremaining -= calculated_tries[
i];
851 for (i = nrates - 1; nremaining > 0 && i >= 0; i--) {
852 int tmp = info->
control.rates[
i].count - calculated_tries[
i];
858 tmp =
min_t(
int, tmp, nremaining);
859 calculated_tries[
i] +=
tmp;
864 for (i = 0; i < nrates && ridx < 8; i++) {
871 info->
control.rates[
i].count = calculated_tries[
i];
873 rc_flags = info->
control.rates[
i].flags;
879 burst_allowed =
false;
883 burst_allowed =
false;
885 for (j = 0; j < calculated_tries[
i] && ridx < 8; j++) {
909 len += info->
control.hw_key->icv_len;
911 info->
control.hw_key->icv_len);
921 if (priv->
rxhw == 5) {
922 txhdr->
longbow.cts_rate = cts_rate;
926 txhdr->
normal.cts_rate = cts_rate;