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pci_schizo.c
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1 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
2  *
3  * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller ([email protected])
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/export.h>
12 #include <linux/interrupt.h>
13 #include <linux/of_device.h>
14 
15 #include <asm/iommu.h>
16 #include <asm/irq.h>
17 #include <asm/pstate.h>
18 #include <asm/prom.h>
19 #include <asm/upa.h>
20 
21 #include "pci_impl.h"
22 #include "iommu_common.h"
23 
24 #define DRIVER_NAME "schizo"
25 #define PFX DRIVER_NAME ": "
26 
27 /* This is a convention that at least Excalibur and Merlin
28  * follow. I suppose the SCHIZO used in Starcat and friends
29  * will do similar.
30  *
31  * The only way I could see this changing is if the newlink
32  * block requires more space in Schizo's address space than
33  * they predicted, thus requiring an address space reorg when
34  * the newer Schizo is taped out.
35  */
36 
37 /* Streaming buffer control register. */
38 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
39 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
40 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
41 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
42 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
43 
44 /* IOMMU control register. */
45 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
46 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
47 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
48 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
49 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
50 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
51 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
52 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
53 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
54 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
55 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
56 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
59 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
60 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
61 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
62 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
63 
64 /* Schizo config space address format is nearly identical to
65  * that of PSYCHO:
66  *
67  * 32 24 23 16 15 11 10 8 7 2 1 0
68  * ---------------------------------------------------------
69  * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
70  * ---------------------------------------------------------
71  */
72 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
73 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
74  (((unsigned long)(BUS) << 16) | \
75  ((unsigned long)(DEVFN) << 8) | \
76  ((unsigned long)(REG)))
77 
78 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
79  unsigned char bus,
80  unsigned int devfn,
81  int where)
82 {
83  if (!pbm)
84  return NULL;
85  bus -= pbm->pci_first_busno;
86  return (void *)
87  (SCHIZO_CONFIG_BASE(pbm) |
88  SCHIZO_CONFIG_ENCODE(bus, devfn, where));
89 }
90 
91 /* SCHIZO error handling support. */
92 enum schizo_error_type {
93  UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
94 };
95 
96 static DEFINE_SPINLOCK(stc_buf_lock);
97 static unsigned long stc_error_buf[128];
98 static unsigned long stc_tag_buf[16];
99 static unsigned long stc_line_buf[16];
100 
101 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
102 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
103 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
104 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
105 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
106 
107 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
108 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
109 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
110 
111 #define SCHIZO_STCERR_WRITE 0x2UL
112 #define SCHIZO_STCERR_READ 0x1UL
113 
114 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
115 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
116 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
117 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
118 
119 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
120 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
121 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
122 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
123 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
124 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
125 
126 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
127  enum schizo_error_type type)
128 {
129  struct strbuf *strbuf = &pbm->stc;
130  unsigned long regbase = pbm->pbm_regs;
131  unsigned long err_base, tag_base, line_base;
132  u64 control;
133  int i;
134 
135  err_base = regbase + SCHIZO_STC_ERR;
136  tag_base = regbase + SCHIZO_STC_TAG;
137  line_base = regbase + SCHIZO_STC_LINE;
138 
139  spin_lock(&stc_buf_lock);
140 
141  /* This is __REALLY__ dangerous. When we put the
142  * streaming buffer into diagnostic mode to probe
143  * it's tags and error status, we _must_ clear all
144  * of the line tag valid bits before re-enabling
145  * the streaming buffer. If any dirty data lives
146  * in the STC when we do this, we will end up
147  * invalidating it before it has a chance to reach
148  * main memory.
149  */
150  control = upa_readq(strbuf->strbuf_control);
151  upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
152  strbuf->strbuf_control);
153  for (i = 0; i < 128; i++) {
154  unsigned long val;
155 
156  val = upa_readq(err_base + (i * 8UL));
157  upa_writeq(0UL, err_base + (i * 8UL));
158  stc_error_buf[i] = val;
159  }
160  for (i = 0; i < 16; i++) {
161  stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
162  stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
163  upa_writeq(0UL, tag_base + (i * 8UL));
164  upa_writeq(0UL, line_base + (i * 8UL));
165  }
166 
167  /* OK, state is logged, exit diagnostic mode. */
168  upa_writeq(control, strbuf->strbuf_control);
169 
170  for (i = 0; i < 16; i++) {
171  int j, saw_error, first, last;
172 
173  saw_error = 0;
174  first = i * 8;
175  last = first + 8;
176  for (j = first; j < last; j++) {
177  unsigned long errval = stc_error_buf[j];
178  if (errval != 0) {
179  saw_error++;
180  printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
181  pbm->name,
182  j,
183  (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
184  (errval & SCHIZO_STCERR_READ) ? 1 : 0);
185  }
186  }
187  if (saw_error != 0) {
188  unsigned long tagval = stc_tag_buf[i];
189  unsigned long lineval = stc_line_buf[i];
190  printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
191  pbm->name,
192  i,
193  ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
194  (tagval & SCHIZO_STCTAG_VPN),
195  ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
196  ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
197 
198  /* XXX Should spit out per-bank error information... -DaveM */
199  printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
200  "V(%d)FOFN(%d)]\n",
201  pbm->name,
202  i,
203  ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
204  ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
205  ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
206  ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
207  ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
208  ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
209  }
210  }
211 
212  spin_unlock(&stc_buf_lock);
213 }
214 
215 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
216  * controller level errors.
217  */
218 
219 #define SCHIZO_IOMMU_TAG 0xa580UL
220 #define SCHIZO_IOMMU_DATA 0xa600UL
221 
222 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
223 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
224 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
225 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
226 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
227 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
228 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
229 
230 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
231 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
232 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
233 
234 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
235  enum schizo_error_type type)
236 {
237  struct iommu *iommu = pbm->iommu;
238  unsigned long iommu_tag[16];
239  unsigned long iommu_data[16];
240  unsigned long flags;
241  u64 control;
242  int i;
243 
244  spin_lock_irqsave(&iommu->lock, flags);
245  control = upa_readq(iommu->iommu_control);
246  if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
247  unsigned long base;
248  char *type_string;
249 
250  /* Clear the error encountered bit. */
251  control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
252  upa_writeq(control, iommu->iommu_control);
253 
254  switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
255  case 0:
256  type_string = "Protection Error";
257  break;
258  case 1:
259  type_string = "Invalid Error";
260  break;
261  case 2:
262  type_string = "TimeOut Error";
263  break;
264  case 3:
265  default:
266  type_string = "ECC Error";
267  break;
268  }
269  printk("%s: IOMMU Error, type[%s]\n",
270  pbm->name, type_string);
271 
272  /* Put the IOMMU into diagnostic mode and probe
273  * it's TLB for entries with error status.
274  *
275  * It is very possible for another DVMA to occur
276  * while we do this probe, and corrupt the system
277  * further. But we are so screwed at this point
278  * that we are likely to crash hard anyways, so
279  * get as much diagnostic information to the
280  * console as we can.
281  */
282  upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
283  iommu->iommu_control);
284 
285  base = pbm->pbm_regs;
286 
287  for (i = 0; i < 16; i++) {
288  iommu_tag[i] =
289  upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
290  iommu_data[i] =
291  upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
292 
293  /* Now clear out the entry. */
294  upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
295  upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
296  }
297 
298  /* Leave diagnostic mode. */
299  upa_writeq(control, iommu->iommu_control);
300 
301  for (i = 0; i < 16; i++) {
302  unsigned long tag, data;
303 
304  tag = iommu_tag[i];
305  if (!(tag & SCHIZO_IOMMU_TAG_ERR))
306  continue;
307 
308  data = iommu_data[i];
309  switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
310  case 0:
311  type_string = "Protection Error";
312  break;
313  case 1:
314  type_string = "Invalid Error";
315  break;
316  case 2:
317  type_string = "TimeOut Error";
318  break;
319  case 3:
320  default:
321  type_string = "ECC Error";
322  break;
323  }
324  printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
325  "sz(%dK) vpg(%08lx)]\n",
326  pbm->name, i, type_string,
327  (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
328  ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
329  ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
330  ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
331  (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
332  printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
333  pbm->name, i,
334  ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
335  ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
336  (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
337  }
338  }
339  if (pbm->stc.strbuf_enabled)
340  __schizo_check_stc_error_pbm(pbm, type);
341  spin_unlock_irqrestore(&iommu->lock, flags);
342 }
343 
344 static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
345  enum schizo_error_type type)
346 {
347  schizo_check_iommu_error_pbm(pbm, type);
348  if (pbm->sibling)
349  schizo_check_iommu_error_pbm(pbm->sibling, type);
350 }
351 
352 /* Uncorrectable ECC error status gathering. */
353 #define SCHIZO_UE_AFSR 0x10030UL
354 #define SCHIZO_UE_AFAR 0x10038UL
355 
356 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
357 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
358 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
359 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
360 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
361 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
362 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
363 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
364 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
365 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
366 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
367 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
368 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
369 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
370 
371 static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
372 {
373  struct pci_pbm_info *pbm = dev_id;
374  unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
375  unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
376  unsigned long afsr, afar, error_bits;
377  int reported, limit;
378 
379  /* Latch uncorrectable error status. */
380  afar = upa_readq(afar_reg);
381 
382  /* If either of the error pending bits are set in the
383  * AFSR, the error status is being actively updated by
384  * the hardware and we must re-read to get a clean value.
385  */
386  limit = 1000;
387  do {
388  afsr = upa_readq(afsr_reg);
389  } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
390 
391  /* Clear the primary/secondary error status bits. */
392  error_bits = afsr &
393  (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
394  SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
395  if (!error_bits)
396  return IRQ_NONE;
397  upa_writeq(error_bits, afsr_reg);
398 
399  /* Log the error. */
400  printk("%s: Uncorrectable Error, primary error type[%s]\n",
401  pbm->name,
402  (((error_bits & SCHIZO_UEAFSR_PPIO) ?
403  "PIO" :
404  ((error_bits & SCHIZO_UEAFSR_PDRD) ?
405  "DMA Read" :
406  ((error_bits & SCHIZO_UEAFSR_PDWR) ?
407  "DMA Write" : "???")))));
408  printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
409  pbm->name,
410  (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
411  (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
412  (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
413  printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
414  pbm->name,
415  (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
416  (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
417  (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
418  (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
419  (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
420  printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
421  printk("%s: UE Secondary errors [", pbm->name);
422  reported = 0;
423  if (afsr & SCHIZO_UEAFSR_SPIO) {
424  reported++;
425  printk("(PIO)");
426  }
427  if (afsr & SCHIZO_UEAFSR_SDMA) {
428  reported++;
429  printk("(DMA)");
430  }
431  if (!reported)
432  printk("(none)");
433  printk("]\n");
434 
435  /* Interrogate IOMMU for error status. */
436  schizo_check_iommu_error(pbm, UE_ERR);
437 
438  return IRQ_HANDLED;
439 }
440 
441 #define SCHIZO_CE_AFSR 0x10040UL
442 #define SCHIZO_CE_AFAR 0x10048UL
443 
444 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
445 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
446 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
447 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
448 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
449 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
450 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
451 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
452 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
453 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
454 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
455 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
456 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
457 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
458 
459 static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
460 {
461  struct pci_pbm_info *pbm = dev_id;
462  unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
463  unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
464  unsigned long afsr, afar, error_bits;
465  int reported, limit;
466 
467  /* Latch error status. */
468  afar = upa_readq(afar_reg);
469 
470  /* If either of the error pending bits are set in the
471  * AFSR, the error status is being actively updated by
472  * the hardware and we must re-read to get a clean value.
473  */
474  limit = 1000;
475  do {
476  afsr = upa_readq(afsr_reg);
477  } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
478 
479  /* Clear primary/secondary error status bits. */
480  error_bits = afsr &
481  (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
482  SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
483  if (!error_bits)
484  return IRQ_NONE;
485  upa_writeq(error_bits, afsr_reg);
486 
487  /* Log the error. */
488  printk("%s: Correctable Error, primary error type[%s]\n",
489  pbm->name,
490  (((error_bits & SCHIZO_CEAFSR_PPIO) ?
491  "PIO" :
492  ((error_bits & SCHIZO_CEAFSR_PDRD) ?
493  "DMA Read" :
494  ((error_bits & SCHIZO_CEAFSR_PDWR) ?
495  "DMA Write" : "???")))));
496 
497  /* XXX Use syndrome and afar to print out module string just like
498  * XXX UDB CE trap handler does... -DaveM
499  */
500  printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
501  pbm->name,
502  (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
503  (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
504  (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
505  printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
506  pbm->name,
507  (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
508  (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
509  (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
510  (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
511  (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
512  printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
513  printk("%s: CE Secondary errors [", pbm->name);
514  reported = 0;
515  if (afsr & SCHIZO_CEAFSR_SPIO) {
516  reported++;
517  printk("(PIO)");
518  }
519  if (afsr & SCHIZO_CEAFSR_SDMA) {
520  reported++;
521  printk("(DMA)");
522  }
523  if (!reported)
524  printk("(none)");
525  printk("]\n");
526 
527  return IRQ_HANDLED;
528 }
529 
530 #define SCHIZO_PCI_AFSR 0x2010UL
531 #define SCHIZO_PCI_AFAR 0x2018UL
532 
533 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
534 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
535 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
536 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
537 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
538 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
539 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
540 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
541 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
542 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
543 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
544 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
545 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
546 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
547 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
548 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
549 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
550 
551 #define SCHIZO_PCI_CTRL (0x2000UL)
552 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
553 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
554 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
555 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
556 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
557 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
558 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
559 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
560 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
561 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
562 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
563 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
564 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
565 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
566 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
567 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
568 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
569 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
570 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
571 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
572 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
573 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
574 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
575 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
576 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
577 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
578 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
579 
580 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
581 {
582  unsigned long csr_reg, csr, csr_error_bits;
583  irqreturn_t ret = IRQ_NONE;
584  u16 stat;
585 
586  csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
587  csr = upa_readq(csr_reg);
588  csr_error_bits =
589  csr & (SCHIZO_PCICTRL_BUS_UNUS |
590  SCHIZO_PCICTRL_TTO_ERR |
591  SCHIZO_PCICTRL_RTRY_ERR |
592  SCHIZO_PCICTRL_DTO_ERR |
593  SCHIZO_PCICTRL_SBH_ERR |
594  SCHIZO_PCICTRL_SERR);
595  if (csr_error_bits) {
596  /* Clear the errors. */
597  upa_writeq(csr, csr_reg);
598 
599  /* Log 'em. */
600  if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
601  printk("%s: Bus unusable error asserted.\n",
602  pbm->name);
603  if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
604  printk("%s: PCI TRDY# timeout error asserted.\n",
605  pbm->name);
606  if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
607  printk("%s: PCI excessive retry error asserted.\n",
608  pbm->name);
609  if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
610  printk("%s: PCI discard timeout error asserted.\n",
611  pbm->name);
612  if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
613  printk("%s: PCI streaming byte hole error asserted.\n",
614  pbm->name);
615  if (csr_error_bits & SCHIZO_PCICTRL_SERR)
616  printk("%s: PCI SERR signal asserted.\n",
617  pbm->name);
618  ret = IRQ_HANDLED;
619  }
620  pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
621  if (stat & (PCI_STATUS_PARITY |
622  PCI_STATUS_SIG_TARGET_ABORT |
623  PCI_STATUS_REC_TARGET_ABORT |
624  PCI_STATUS_REC_MASTER_ABORT |
625  PCI_STATUS_SIG_SYSTEM_ERROR)) {
626  printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
627  pbm->name, stat);
628  pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
629  ret = IRQ_HANDLED;
630  }
631  return ret;
632 }
633 
634 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
635 {
636  struct pci_pbm_info *pbm = dev_id;
637  unsigned long afsr_reg, afar_reg, base;
638  unsigned long afsr, afar, error_bits;
639  int reported;
640 
641  base = pbm->pbm_regs;
642 
643  afsr_reg = base + SCHIZO_PCI_AFSR;
644  afar_reg = base + SCHIZO_PCI_AFAR;
645 
646  /* Latch error status. */
647  afar = upa_readq(afar_reg);
648  afsr = upa_readq(afsr_reg);
649 
650  /* Clear primary/secondary error status bits. */
651  error_bits = afsr &
652  (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
653  SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
654  SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
655  SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
656  SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
657  SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
658  if (!error_bits)
659  return schizo_pcierr_intr_other(pbm);
660  upa_writeq(error_bits, afsr_reg);
661 
662  /* Log the error. */
663  printk("%s: PCI Error, primary error type[%s]\n",
664  pbm->name,
665  (((error_bits & SCHIZO_PCIAFSR_PMA) ?
666  "Master Abort" :
667  ((error_bits & SCHIZO_PCIAFSR_PTA) ?
668  "Target Abort" :
669  ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
670  "Excessive Retries" :
671  ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
672  "Parity Error" :
673  ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
674  "Timeout" :
675  ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
676  "Bus Unusable" : "???"))))))));
677  printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
678  pbm->name,
679  (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
680  (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
681  ((afsr & SCHIZO_PCIAFSR_CFG) ?
682  "Config" :
683  ((afsr & SCHIZO_PCIAFSR_MEM) ?
684  "Memory" :
685  ((afsr & SCHIZO_PCIAFSR_IO) ?
686  "I/O" : "???"))));
687  printk("%s: PCI AFAR [%016lx]\n",
688  pbm->name, afar);
689  printk("%s: PCI Secondary errors [",
690  pbm->name);
691  reported = 0;
692  if (afsr & SCHIZO_PCIAFSR_SMA) {
693  reported++;
694  printk("(Master Abort)");
695  }
696  if (afsr & SCHIZO_PCIAFSR_STA) {
697  reported++;
698  printk("(Target Abort)");
699  }
700  if (afsr & SCHIZO_PCIAFSR_SRTRY) {
701  reported++;
702  printk("(Excessive Retries)");
703  }
704  if (afsr & SCHIZO_PCIAFSR_SPERR) {
705  reported++;
706  printk("(Parity Error)");
707  }
708  if (afsr & SCHIZO_PCIAFSR_STTO) {
709  reported++;
710  printk("(Timeout)");
711  }
712  if (afsr & SCHIZO_PCIAFSR_SUNUS) {
713  reported++;
714  printk("(Bus Unusable)");
715  }
716  if (!reported)
717  printk("(none)");
718  printk("]\n");
719 
720  /* For the error types shown, scan PBM's PCI bus for devices
721  * which have logged that error type.
722  */
723 
724  /* If we see a Target Abort, this could be the result of an
725  * IOMMU translation error of some sort. It is extremely
726  * useful to log this information as usually it indicates
727  * a bug in the IOMMU support code or a PCI device driver.
728  */
729  if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
730  schizo_check_iommu_error(pbm, PCI_ERR);
731  pci_scan_for_target_abort(pbm, pbm->pci_bus);
732  }
733  if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
734  pci_scan_for_master_abort(pbm, pbm->pci_bus);
735 
736  /* For excessive retries, PSYCHO/PBM will abort the device
737  * and there is no way to specifically check for excessive
738  * retries in the config space status registers. So what
739  * we hope is that we'll catch it via the master/target
740  * abort events.
741  */
742 
743  if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
744  pci_scan_for_parity_error(pbm, pbm->pci_bus);
745 
746  return IRQ_HANDLED;
747 }
748 
749 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
750 
751 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
752 
753 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
754 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
755 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
756 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
757 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
758 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
759 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
760 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
761 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
762 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
763 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
764 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
765 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
766 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
767 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
768 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
769 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
770 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
771 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
772 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
773 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
774 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
775 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
776 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
777 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
778 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
779 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
780 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
781 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
782 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
783 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
784 
785 /* We only expect UNMAP errors here. The rest of the Safari errors
786  * are marked fatal and thus cause a system reset.
787  */
788 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
789 {
790  struct pci_pbm_info *pbm = dev_id;
791  u64 errlog;
792 
793  errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
794  upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
795  pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
796 
797  if (!(errlog & BUS_ERROR_UNMAP)) {
798  printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n",
799  pbm->name, errlog);
800 
801  return IRQ_HANDLED;
802  }
803 
804  printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
805  pbm->name);
806  schizo_check_iommu_error(pbm, SAFARI_ERR);
807 
808  return IRQ_HANDLED;
809 }
810 
811 /* Nearly identical to PSYCHO equivalents... */
812 #define SCHIZO_ECC_CTRL 0x10020UL
813 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
814 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
815 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
816 
817 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
818 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
819 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
820 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
821 
822 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
823 {
824  ino &= IMAP_INO;
825 
826  if (pbm->ino_bitmap & (1UL << ino))
827  return 1;
828 
829  return 0;
830 }
831 
832 /* How the Tomatillo IRQs are routed around is pure guesswork here.
833  *
834  * All the Tomatillo devices I see in prtconf dumps seem to have only
835  * a single PCI bus unit attached to it. It would seem they are separate
836  * devices because their PortID (ie. JBUS ID) values are all different
837  * and thus the registers are mapped to totally different locations.
838  *
839  * However, two Tomatillo's look "similar" in that the only difference
840  * in their PortID is the lowest bit.
841  *
842  * So if we were to ignore this lower bit, it certainly looks like two
843  * PCI bus units of the same Tomatillo. I still have not really
844  * figured this out...
845  */
846 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
847 {
848  struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
849  u64 tmp, err_mask, err_no_mask;
850  int err;
851 
852  /* Tomatillo IRQ property layout is:
853  * 0: PCIERR
854  * 1: UE ERR
855  * 2: CE ERR
856  * 3: SERR
857  * 4: POWER FAIL?
858  */
859 
860  if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
861  err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
862  "TOMATILLO_UE", pbm);
863  if (err)
864  printk(KERN_WARNING "%s: Could not register UE, "
865  "err=%d\n", pbm->name, err);
866  }
867  if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
868  err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
869  "TOMATILLO_CE", pbm);
870  if (err)
871  printk(KERN_WARNING "%s: Could not register CE, "
872  "err=%d\n", pbm->name, err);
873  }
874  err = 0;
875  if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
876  err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
877  "TOMATILLO_PCIERR", pbm);
878  } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
879  err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
880  "TOMATILLO_PCIERR", pbm);
881  }
882  if (err)
883  printk(KERN_WARNING "%s: Could not register PCIERR, "
884  "err=%d\n", pbm->name, err);
885 
886  if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
887  err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
888  "TOMATILLO_SERR", pbm);
889  if (err)
890  printk(KERN_WARNING "%s: Could not register SERR, "
891  "err=%d\n", pbm->name, err);
892  }
893 
894  /* Enable UE and CE interrupts for controller. */
895  upa_writeq((SCHIZO_ECCCTRL_EE |
896  SCHIZO_ECCCTRL_UE |
897  SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
898 
899  /* Enable PCI Error interrupts and clear error
900  * bits.
901  */
902  err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
903  SCHIZO_PCICTRL_TTO_ERR |
904  SCHIZO_PCICTRL_RTRY_ERR |
905  SCHIZO_PCICTRL_SERR |
906  SCHIZO_PCICTRL_EEN);
907 
908  err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
909 
910  tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
911  tmp |= err_mask;
912  tmp &= ~err_no_mask;
913  upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
914 
915  err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
916  SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
917  SCHIZO_PCIAFSR_PTTO |
918  SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
919  SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
920  SCHIZO_PCIAFSR_STTO);
921 
922  upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
923 
924  err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
925  BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
926  BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
927  BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
928  BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
929  BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
930  BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
931  BUS_ERROR_APERR | BUS_ERROR_UNMAP |
932  BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
933 
934  upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
935  pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
936 
937  upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
938  pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
939 }
940 
941 static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
942 {
943  struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
944  u64 tmp, err_mask, err_no_mask;
945  int err;
946 
947  /* Schizo IRQ property layout is:
948  * 0: PCIERR
949  * 1: UE ERR
950  * 2: CE ERR
951  * 3: SERR
952  * 4: POWER FAIL?
953  */
954 
955  if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
956  err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
957  "SCHIZO_UE", pbm);
958  if (err)
959  printk(KERN_WARNING "%s: Could not register UE, "
960  "err=%d\n", pbm->name, err);
961  }
962  if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
963  err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
964  "SCHIZO_CE", pbm);
965  if (err)
966  printk(KERN_WARNING "%s: Could not register CE, "
967  "err=%d\n", pbm->name, err);
968  }
969  err = 0;
970  if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
971  err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
972  "SCHIZO_PCIERR", pbm);
973  } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
974  err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
975  "SCHIZO_PCIERR", pbm);
976  }
977  if (err)
978  printk(KERN_WARNING "%s: Could not register PCIERR, "
979  "err=%d\n", pbm->name, err);
980 
981  if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
982  err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
983  "SCHIZO_SERR", pbm);
984  if (err)
985  printk(KERN_WARNING "%s: Could not register SERR, "
986  "err=%d\n", pbm->name, err);
987  }
988 
989  /* Enable UE and CE interrupts for controller. */
990  upa_writeq((SCHIZO_ECCCTRL_EE |
991  SCHIZO_ECCCTRL_UE |
992  SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
993 
994  err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
995  SCHIZO_PCICTRL_ESLCK |
996  SCHIZO_PCICTRL_TTO_ERR |
997  SCHIZO_PCICTRL_RTRY_ERR |
998  SCHIZO_PCICTRL_SBH_ERR |
999  SCHIZO_PCICTRL_SERR |
1000  SCHIZO_PCICTRL_EEN);
1001 
1002  err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1003  SCHIZO_PCICTRL_SBH_INT);
1004 
1005  /* Enable PCI Error interrupts and clear error
1006  * bits for each PBM.
1007  */
1008  tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1009  tmp |= err_mask;
1010  tmp &= ~err_no_mask;
1011  upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1012 
1013  upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1014  SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1015  SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1016  SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1017  SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1018  SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
1019  pbm->pbm_regs + SCHIZO_PCI_AFSR);
1020 
1021  /* Make all Safari error conditions fatal except unmapped
1022  * errors which we make generate interrupts.
1023  */
1024  err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1025  BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1026  BUS_ERROR_BADMC |
1027  BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1028  BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1029  BUS_ERROR_CIQTO |
1030  BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1031  BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1032  BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1033  BUS_ERROR_ILL);
1034 #if 1
1035  /* XXX Something wrong with some Excalibur systems
1036  * XXX Sun is shipping. The behavior on a 2-cpu
1037  * XXX machine is that both CPU1 parity error bits
1038  * XXX are set and are immediately set again when
1039  * XXX their error status bits are cleared. Just
1040  * XXX ignore them for now. -DaveM
1041  */
1042  err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1043  BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1044 #endif
1045 
1046  upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
1047  pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
1048 }
1049 
1050 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1051 {
1052  u8 *addr;
1053 
1054  /* Set cache-line size to 64 bytes, this is actually
1055  * a nop but I do it for completeness.
1056  */
1057  addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1058  0, PCI_CACHE_LINE_SIZE);
1059  pci_config_write8(addr, 64 / sizeof(u32));
1060 
1061  /* Set PBM latency timer to 64 PCI clocks. */
1062  addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1063  0, PCI_LATENCY_TIMER);
1064  pci_config_write8(addr, 64);
1065 }
1066 
1067 static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm,
1068  struct device *parent)
1069 {
1070  pbm_config_busmastering(pbm);
1071  pbm->is_66mhz_capable =
1072  (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL)
1073  != NULL);
1074 
1075  pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1076 
1077  if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1078  tomatillo_register_error_handlers(pbm);
1079  else
1080  schizo_register_error_handlers(pbm);
1081 }
1082 
1083 #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1084 #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1085 #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1086 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1087 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1088 
1089 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1090 {
1091  unsigned long base = pbm->pbm_regs;
1092  u64 control;
1093 
1094  if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1095  /* TOMATILLO lacks streaming cache. */
1096  return;
1097  }
1098 
1099  /* SCHIZO has context flushing. */
1100  pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1101  pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1102  pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1103  pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1104  pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1105 
1106  pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1107  ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1108  + 63UL)
1109  & ~63UL);
1110  pbm->stc.strbuf_flushflag_pa = (unsigned long)
1111  __pa(pbm->stc.strbuf_flushflag);
1112 
1113  /* Turn off LRU locking and diag mode, enable the
1114  * streaming buffer and leave the rerun-disable
1115  * setting however OBP set it.
1116  */
1117  control = upa_readq(pbm->stc.strbuf_control);
1118  control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1119  SCHIZO_STRBUF_CTRL_LENAB |
1120  SCHIZO_STRBUF_CTRL_DENAB);
1121  control |= SCHIZO_STRBUF_CTRL_ENAB;
1122  upa_writeq(control, pbm->stc.strbuf_control);
1123 
1124  pbm->stc.strbuf_enabled = 1;
1125 }
1126 
1127 #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1128 #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1129 #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1130 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1131 
1132 static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1133 {
1134  static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
1135  unsigned long i, tagbase, database;
1136  struct iommu *iommu = pbm->iommu;
1137  int tsbsize, err;
1138  const u32 *vdma;
1139  u32 dma_mask;
1140  u64 control;
1141 
1142  vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
1143  if (!vdma)
1144  vdma = vdma_default;
1145 
1146  dma_mask = vdma[0];
1147  switch (vdma[1]) {
1148  case 0x20000000:
1149  dma_mask |= 0x1fffffff;
1150  tsbsize = 64;
1151  break;
1152 
1153  case 0x40000000:
1154  dma_mask |= 0x3fffffff;
1155  tsbsize = 128;
1156  break;
1157 
1158  case 0x80000000:
1159  dma_mask |= 0x7fffffff;
1160  tsbsize = 128;
1161  break;
1162 
1163  default:
1164  printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1165  return -EINVAL;
1166  }
1167 
1168  /* Register addresses, SCHIZO has iommu ctx flushing. */
1169  iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1170  iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1171  iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1172  iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
1173  iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1174 
1175  /* We use the main control/status register of SCHIZO as the write
1176  * completion register.
1177  */
1178  iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1179 
1180  /*
1181  * Invalidate TLB Entries.
1182  */
1183  control = upa_readq(iommu->iommu_control);
1184  control |= SCHIZO_IOMMU_CTRL_DENAB;
1185  upa_writeq(control, iommu->iommu_control);
1186 
1187  tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1188 
1189  for (i = 0; i < 16; i++) {
1190  upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
1191  upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
1192  }
1193 
1194  /* Leave diag mode enabled for full-flushing done
1195  * in pci_iommu.c
1196  */
1197  err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1198  pbm->numa_node);
1199  if (err) {
1200  printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
1201  return err;
1202  }
1203 
1204  upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
1205 
1206  control = upa_readq(iommu->iommu_control);
1207  control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1208  switch (tsbsize) {
1209  case 64:
1210  control |= SCHIZO_IOMMU_TSBSZ_64K;
1211  break;
1212  case 128:
1213  control |= SCHIZO_IOMMU_TSBSZ_128K;
1214  break;
1215  }
1216 
1217  control |= SCHIZO_IOMMU_CTRL_ENAB;
1218  upa_writeq(control, iommu->iommu_control);
1219 
1220  return 0;
1221 }
1222 
1223 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1224 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1225 
1226 #define SCHIZO_PCI_DIAG (0x2020UL)
1227 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1228 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1229 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1230 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1231 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1232 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1233 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1234 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1235 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1236 
1237 #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1238 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1239 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1240 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1241 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1242 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1243 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1244 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1245 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1246 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1247 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1248 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1249 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1250 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1251 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1252 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1253 
1254 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1255 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1256 
1257 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1258 {
1259  u64 tmp;
1260 
1261  upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
1262 
1263  tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1264 
1265  /* Enable arbiter for all PCI slots. */
1266  tmp |= 0xff;
1267 
1268  if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1269  pbm->chip_version >= 0x2)
1270  tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1271 
1272  if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL))
1273  tmp |= SCHIZO_PCICTRL_PARK;
1274  else
1275  tmp &= ~SCHIZO_PCICTRL_PARK;
1276 
1277  if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1278  pbm->chip_version <= 0x1)
1279  tmp |= SCHIZO_PCICTRL_DTO_INT;
1280  else
1281  tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1282 
1283  if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1284  tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1285  SCHIZO_PCICTRL_RDO_PREF |
1286  SCHIZO_PCICTRL_RDL_PREF);
1287 
1288  upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1289 
1290  tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1291  tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1292  SCHIZO_PCIDIAG_D_RETRY |
1293  SCHIZO_PCIDIAG_D_INTSYNC);
1294  upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
1295 
1296  if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1297  /* Clear prefetch lengths to workaround a bug in
1298  * Jalapeno...
1299  */
1300  tmp = (TOMATILLO_IOC_PART_WPENAB |
1301  (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1302  TOMATILLO_IOC_RDMULT_CPENAB |
1303  TOMATILLO_IOC_RDONE_CPENAB |
1304  TOMATILLO_IOC_RDLINE_CPENAB);
1305 
1306  upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
1307  }
1308 }
1309 
1310 static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm,
1311  struct platform_device *op, u32 portid,
1312  int chip_type)
1313 {
1314  const struct linux_prom64_registers *regs;
1315  struct device_node *dp = op->dev.of_node;
1316  const char *chipset_name;
1317  int err;
1318 
1319  switch (chip_type) {
1320  case PBM_CHIP_TYPE_TOMATILLO:
1321  chipset_name = "TOMATILLO";
1322  break;
1323 
1324  case PBM_CHIP_TYPE_SCHIZO_PLUS:
1325  chipset_name = "SCHIZO+";
1326  break;
1327 
1328  case PBM_CHIP_TYPE_SCHIZO:
1329  default:
1330  chipset_name = "SCHIZO";
1331  break;
1332  }
1333 
1334  /* For SCHIZO, three OBP regs:
1335  * 1) PBM controller regs
1336  * 2) Schizo front-end controller regs (same for both PBMs)
1337  * 3) PBM PCI config space
1338  *
1339  * For TOMATILLO, four OBP regs:
1340  * 1) PBM controller regs
1341  * 2) Tomatillo front-end controller regs
1342  * 3) PBM PCI config space
1343  * 4) Ichip regs
1344  */
1345  regs = of_get_property(dp, "reg", NULL);
1346 
1347  pbm->next = pci_pbm_root;
1348  pci_pbm_root = pbm;
1349 
1350  pbm->numa_node = -1;
1351 
1352  pbm->pci_ops = &sun4u_pci_ops;
1353  pbm->config_space_reg_bits = 8;
1354 
1355  pbm->index = pci_num_pbms++;
1356 
1357  pbm->portid = portid;
1358  pbm->op = op;
1359 
1360  pbm->chip_type = chip_type;
1361  pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1362  pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
1363 
1364  pbm->pbm_regs = regs[0].phys_addr;
1365  pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1366 
1367  if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1368  pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
1369 
1370  pbm->name = dp->full_name;
1371 
1372  printk("%s: %s PCI Bus Module ver[%x:%x]\n",
1373  pbm->name, chipset_name,
1374  pbm->chip_version, pbm->chip_revision);
1375 
1376  schizo_pbm_hw_init(pbm);
1377 
1378  pci_determine_mem_io_space(pbm);
1379 
1380  pci_get_pbm_props(pbm);
1381 
1382  err = schizo_pbm_iommu_init(pbm);
1383  if (err)
1384  return err;
1385 
1386  schizo_pbm_strbuf_init(pbm);
1387 
1388  schizo_scan_bus(pbm, &op->dev);
1389 
1390  return 0;
1391 }
1392 
1393 static inline int portid_compare(u32 x, u32 y, int chip_type)
1394 {
1395  if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1396  if (x == (y ^ 1))
1397  return 1;
1398  return 0;
1399  }
1400  return (x == y);
1401 }
1402 
1403 static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid,
1404  int chip_type)
1405 {
1406  struct pci_pbm_info *pbm;
1407 
1408  for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1409  if (portid_compare(pbm->portid, portid, chip_type))
1410  return pbm;
1411  }
1412  return NULL;
1413 }
1414 
1415 static int __devinit __schizo_init(struct platform_device *op, unsigned long chip_type)
1416 {
1417  struct device_node *dp = op->dev.of_node;
1418  struct pci_pbm_info *pbm;
1419  struct iommu *iommu;
1420  u32 portid;
1421  int err;
1422 
1423  portid = of_getintprop_default(dp, "portid", 0xff);
1424 
1425  err = -ENOMEM;
1426  pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1427  if (!pbm) {
1428  printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
1429  goto out_err;
1430  }
1431 
1432  pbm->sibling = schizo_find_sibling(portid, chip_type);
1433 
1434  iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1435  if (!iommu) {
1436  printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
1437  goto out_free_pbm;
1438  }
1439 
1440  pbm->iommu = iommu;
1441 
1442  if (schizo_pbm_init(pbm, op, portid, chip_type))
1443  goto out_free_iommu;
1444 
1445  if (pbm->sibling)
1446  pbm->sibling->sibling = pbm;
1447 
1448  dev_set_drvdata(&op->dev, pbm);
1449 
1450  return 0;
1451 
1452 out_free_iommu:
1453  kfree(pbm->iommu);
1454 
1455 out_free_pbm:
1456  kfree(pbm);
1457 
1458 out_err:
1459  return err;
1460 }
1461 
1462 static const struct of_device_id schizo_match[];
1463 static int __devinit schizo_probe(struct platform_device *op)
1464 {
1465  const struct of_device_id *match;
1466 
1467  match = of_match_device(schizo_match, &op->dev);
1468  if (!match)
1469  return -EINVAL;
1470  return __schizo_init(op, (unsigned long)match->data);
1471 }
1472 
1473 /* The ordering of this table is very important. Some Tomatillo
1474  * nodes announce that they are compatible with both pci108e,a801
1475  * and pci108e,8001. So list the chips in reverse chronological
1476  * order.
1477  */
1478 static const struct of_device_id schizo_match[] = {
1479  {
1480  .name = "pci",
1481  .compatible = "pci108e,a801",
1482  .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1483  },
1484  {
1485  .name = "pci",
1486  .compatible = "pci108e,8002",
1487  .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1488  },
1489  {
1490  .name = "pci",
1491  .compatible = "pci108e,8001",
1492  .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1493  },
1494  {},
1495 };
1496 
1497 static struct platform_driver schizo_driver = {
1498  .driver = {
1499  .name = DRIVER_NAME,
1500  .owner = THIS_MODULE,
1501  .of_match_table = schizo_match,
1502  },
1503  .probe = schizo_probe,
1504 };
1505 
1506 static int __init schizo_init(void)
1507 {
1508  return platform_driver_register(&schizo_driver);
1509 }
1510 
1511 subsys_initcall(schizo_init);
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