| enum | {
MV_PRIMARY_BAR = 0,
MV_IO_BAR = 2,
MV_MISC_BAR = 3,
MV_MAJOR_REG_AREA_SZ = 0x10000,
MV_MINOR_REG_AREA_SZ = 0x2000,
COAL_CLOCKS_PER_USEC = 150,
MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1),
MAX_COAL_IO_COUNT = 255,
MV_PCI_REG_BASE = 0,
COAL_REG_BASE = 0x18000,
IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
ALL_PORTS_COAL_IRQ = (1 << 4),
IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
SATAHC0_REG_BASE = 0x20000,
FLASH_CTL = 0x1046c,
GPIO_PORT_CTL = 0x104f0,
RESET_CFG = 0x180d8,
MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ,
MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
MV_MAX_Q_DEPTH = 32,
MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
MV_MAX_SG_CT = 256,
MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
MV_PORT_HC_SHIFT = 2,
MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT),
MV_PORT_MASK = (MV_PORTS_PER_HC - 1),
MV_FLAG_DUAL_HC = (1 << 30),
MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
MV_GEN_II_FLAGS,
MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
CRQB_FLAG_READ = (1 << 0),
CRQB_TAG_SHIFT = 1,
CRQB_IOID_SHIFT = 6,
CRQB_PMP_SHIFT = 12,
CRQB_HOSTQ_SHIFT = 17,
CRQB_CMD_ADDR_SHIFT = 8,
CRQB_CMD_CS = (0x2 << 11),
CRQB_CMD_LAST = (1 << 15),
CRPB_FLAG_STATUS_SHIFT = 8,
CRPB_IOID_SHIFT_6 = 5,
CRPB_IOID_SHIFT_7 = 7,
EPRD_FLAG_END_OF_TBL = (1 << 31),
MV_PCI_COMMAND = 0xc00,
MV_PCI_COMMAND_MWRCOM = (1 << 4),
MV_PCI_COMMAND_MRDTRIG = (1 << 7),
PCI_MAIN_CMD_STS = 0xd30,
STOP_PCI_MASTER = (1 << 2),
PCI_MASTER_EMPTY = (1 << 3),
GLOB_SFT_RST = (1 << 4),
MV_PCI_MODE = 0xd00,
MV_PCI_MODE_MASK = 0x30,
MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
MV_PCI_DISC_TIMER = 0xd04,
MV_PCI_MSI_TRIGGER = 0xc38,
MV_PCI_SERR_MASK = 0xc28,
MV_PCI_XBAR_TMOUT = 0x1d04,
MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
MV_PCI_ERR_ATTRIBUTE = 0x1d48,
MV_PCI_ERR_COMMAND = 0x1d50,
PCI_IRQ_CAUSE = 0x1d58,
PCI_IRQ_MASK = 0x1d5c,
PCI_UNMASK_ALL_IRQS = 0x7fffff,
PCIE_IRQ_CAUSE = 0x1900,
PCIE_IRQ_MASK = 0x1910,
PCIE_UNMASK_ALL_IRQS = 0x40a,
PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
PCI_HC_MAIN_IRQ_MASK = 0x1d64,
SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
SOC_HC_MAIN_IRQ_MASK = 0x20024,
ERR_IRQ = (1 << 0),
DONE_IRQ = (1 << 1),
HC0_IRQ_PEND = 0x1ff,
HC_SHIFT = 9,
DONE_IRQ_0_3 = 0x000000aa,
DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT),
PCI_ERR = (1 << 18),
TRAN_COAL_LO_DONE = (1 << 19),
TRAN_COAL_HI_DONE = (1 << 20),
PORTS_0_3_COAL_DONE = (1 << 8),
PORTS_4_7_COAL_DONE = (1 << 17),
ALL_PORTS_COAL_DONE = (1 << 21),
GPIO_INT = (1 << 22),
SELF_INT = (1 << 23),
TWSI_INT = (1 << 24),
HC_MAIN_RSVD = (0x7f << 25),
HC_MAIN_RSVD_5 = (0x1fff << 19),
HC_MAIN_RSVD_SOC = (0x3fffffb << 6),
HC_CFG = 0x00,
HC_IRQ_CAUSE = 0x14,
DMA_IRQ = (1 << 0),
HC_COAL_IRQ = (1 << 4),
DEV_IRQ = (1 << 8),
HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
SOC_LED_CTRL = 0x2c,
SOC_LED_CTRL_BLINK = (1 << 0),
SOC_LED_CTRL_ACT_PRESENCE = (1 << 2),
SHD_BLK = 0x100,
SHD_CTL_AST = 0x20,
SATA_STATUS = 0x300,
SATA_ACTIVE = 0x350,
FIS_IRQ_CAUSE = 0x364,
FIS_IRQ_CAUSE_AN = (1 << 9),
LTMODE = 0x30c,
LTMODE_BIT8 = (1 << 8),
PHY_MODE2 = 0x330,
PHY_MODE3 = 0x310,
PHY_MODE4 = 0x314,
PHY_MODE4_CFG_MASK = 0x00000003,
PHY_MODE4_CFG_VALUE = 0x00000001,
PHY_MODE4_RSVD_ZEROS = 0x5de3fffa,
PHY_MODE4_RSVD_ONES = 0x00000005,
SATA_IFCTL = 0x344,
SATA_TESTCTL = 0x348,
SATA_IFSTAT = 0x34c,
VENDOR_UNIQUE_FIS = 0x35c,
FISCFG = 0x360,
FISCFG_WAIT_DEV_ERR = (1 << 8),
FISCFG_SINGLE_SYNC = (1 << 16),
PHY_MODE9_GEN2 = 0x398,
PHY_MODE9_GEN1 = 0x39c,
PHYCFG_OFS = 0x3a0,
MV5_PHY_MODE = 0x74,
MV5_LTMODE = 0x30,
MV5_PHY_CTL = 0x0C,
SATA_IFCFG = 0x050,
MV_M2_PREAMP_MASK = 0x7e0,
EDMA_CFG = 0,
EDMA_CFG_Q_DEPTH = 0x1f,
EDMA_CFG_NCQ = (1 << 5),
EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14),
EDMA_CFG_RD_BRST_EXT = (1 << 11),
EDMA_CFG_WR_BUFF_LEN = (1 << 13),
EDMA_CFG_EDMA_FBS = (1 << 16),
EDMA_CFG_FBS = (1 << 26),
EDMA_ERR_IRQ_CAUSE = 0x8,
EDMA_ERR_IRQ_MASK = 0xc,
EDMA_ERR_D_PAR = (1 << 0),
EDMA_ERR_PRD_PAR = (1 << 1),
EDMA_ERR_DEV = (1 << 2),
EDMA_ERR_DEV_DCON = (1 << 3),
EDMA_ERR_DEV_CON = (1 << 4),
EDMA_ERR_SERR = (1 << 5),
EDMA_ERR_SELF_DIS = (1 << 7),
EDMA_ERR_SELF_DIS_5 = (1 << 8),
EDMA_ERR_BIST_ASYNC = (1 << 8),
EDMA_ERR_TRANS_IRQ_7 = (1 << 8),
EDMA_ERR_CRQB_PAR = (1 << 9),
EDMA_ERR_CRPB_PAR = (1 << 10),
EDMA_ERR_INTRL_PAR = (1 << 11),
EDMA_ERR_IORDY = (1 << 12),
EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13),
EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14),
EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16),
EDMA_ERR_LNK_DATA_RX = (0xf << 17),
EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21),
EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22),
EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23),
EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24),
EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25),
EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
EDMA_ERR_TRANS_PROTO = (1 << 31),
EDMA_ERR_OVERRUN_5 = (1 << 5),
EDMA_ERR_UNDERRUN_5 = (1 << 6),
EDMA_ERR_IRQ_TRANSIENT,
EDMA_EH_FREEZE,
EDMA_EH_FREEZE_5,
EDMA_REQ_Q_BASE_HI = 0x10,
EDMA_REQ_Q_IN_PTR = 0x14,
EDMA_REQ_Q_OUT_PTR = 0x18,
EDMA_REQ_Q_PTR_SHIFT = 5,
EDMA_RSP_Q_BASE_HI = 0x1c,
EDMA_RSP_Q_IN_PTR = 0x20,
EDMA_RSP_Q_OUT_PTR = 0x24,
EDMA_RSP_Q_PTR_SHIFT = 3,
EDMA_CMD = 0x28,
EDMA_EN = (1 << 0),
EDMA_DS = (1 << 1),
EDMA_RESET = (1 << 2),
EDMA_STATUS = 0x30,
EDMA_STATUS_CACHE_EMPTY = (1 << 6),
EDMA_STATUS_IDLE = (1 << 7),
EDMA_IORDY_TMOUT = 0x34,
EDMA_ARB_CFG = 0x38,
EDMA_HALTCOND = 0x60,
EDMA_UNKNOWN_RSVD = 0x6C,
BMDMA_CMD = 0x224,
BMDMA_STATUS = 0x228,
BMDMA_PRD_LOW = 0x22c,
BMDMA_PRD_HIGH = 0x230,
MV_HP_FLAG_MSI = (1 << 0),
MV_HP_ERRATA_50XXB0 = (1 << 1),
MV_HP_ERRATA_50XXB2 = (1 << 2),
MV_HP_ERRATA_60X1B2 = (1 << 3),
MV_HP_ERRATA_60X1C0 = (1 << 4),
MV_HP_GEN_I = (1 << 6),
MV_HP_GEN_II = (1 << 7),
MV_HP_GEN_IIE = (1 << 8),
MV_HP_PCIE = (1 << 9),
MV_HP_CUT_THROUGH = (1 << 10),
MV_HP_FLAG_SOC = (1 << 11),
MV_HP_QUIRK_LED_BLINK_EN = (1 << 12),
MV_PP_FLAG_EDMA_EN = (1 << 0),
MV_PP_FLAG_NCQ_EN = (1 << 1),
MV_PP_FLAG_FBS_EN = (1 << 2),
MV_PP_FLAG_DELAYED_EH = (1 << 3),
MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4)
} |
1.8.2