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pinctrl-tegra20.c
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1 /*
2  * Pinctrl data for the NVIDIA Tegra20 pinmux
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5  *
6  * Derived from code:
7  * Copyright (C) 2010 Google, Inc.
8  * Copyright (C) 2010 NVIDIA Corporation
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms and conditions of the GNU General Public License,
12  * version 2, as published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17  * more details.
18  */
19 
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 
26 #include "pinctrl-tegra.h"
27 
28 /*
29  * Most pins affected by the pinmux can also be GPIOs. Define these first.
30  * These must match how the GPIO driver names/numbers its pins.
31  */
32 #define _GPIO(offset) (offset)
33 
34 #define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
35 #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
36 #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
37 #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
38 #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
39 #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
40 #define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
41 #define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
42 #define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
43 #define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
44 #define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
45 #define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
46 #define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
47 #define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
48 #define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
49 #define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
50 #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
51 #define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
52 #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
53 #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
54 #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
55 #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
56 #define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
57 #define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
58 #define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
59 #define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
60 #define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
61 #define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
62 #define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
63 #define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
64 #define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
65 #define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
66 #define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
67 #define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
68 #define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
69 #define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
70 #define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
71 #define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
72 #define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
73 #define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
74 #define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
75 #define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
76 #define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
77 #define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
78 #define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
79 #define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
80 #define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
81 #define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
82 #define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
83 #define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
84 #define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
85 #define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
86 #define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
87 #define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
88 #define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
89 #define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
90 #define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
91 #define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
92 #define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
93 #define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
94 #define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
95 #define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
96 #define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
97 #define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
98 #define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
99 #define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
100 #define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
101 #define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
102 #define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
103 #define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
104 #define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
105 #define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
106 #define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
107 #define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
108 #define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
109 #define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
110 #define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
111 #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
112 #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
113 #define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
114 #define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
115 #define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
116 #define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
117 #define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
118 #define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
119 #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
120 #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
121 #define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
122 #define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
123 #define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
124 #define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
125 #define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
126 #define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
127 #define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
128 #define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
129 #define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
130 #define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
131 #define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
132 #define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
133 #define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
134 #define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
135 #define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
136 #define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
137 #define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
138 #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
139 #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
140 #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
141 #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
142 #define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
143 #define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
144 #define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
145 #define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
146 #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
147 #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
148 #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
149 #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
150 #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
151 #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
152 #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
153 #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
154 #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
155 #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
156 #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
157 #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
158 #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
159 #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
160 #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
161 #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
162 #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
163 #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
164 #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
165 #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
166 #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
167 #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
168 #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
169 #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
170 #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
171 #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
172 #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
173 #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
174 #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
175 #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
176 #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
177 #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
178 #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
179 #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
180 #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
181 #define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
182 #define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
183 #define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
184 #define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
185 #define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
186 #define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
187 #define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
188 #define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
189 #define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
190 #define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
191 #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
192 #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
193 #define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
194 #define TEGRA_PIN_PU0 _GPIO(160)
195 #define TEGRA_PIN_PU1 _GPIO(161)
196 #define TEGRA_PIN_PU2 _GPIO(162)
197 #define TEGRA_PIN_PU3 _GPIO(163)
198 #define TEGRA_PIN_PU4 _GPIO(164)
199 #define TEGRA_PIN_PU5 _GPIO(165)
200 #define TEGRA_PIN_PU6 _GPIO(166)
201 #define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
202 #define TEGRA_PIN_PV0 _GPIO(168)
203 #define TEGRA_PIN_PV1 _GPIO(169)
204 #define TEGRA_PIN_PV2 _GPIO(170)
205 #define TEGRA_PIN_PV3 _GPIO(171)
206 #define TEGRA_PIN_PV4 _GPIO(172)
207 #define TEGRA_PIN_PV5 _GPIO(173)
208 #define TEGRA_PIN_PV6 _GPIO(174)
209 #define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
210 #define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
211 #define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
212 #define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
213 #define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
214 #define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
215 #define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
216 #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
217 #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
218 #define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
219 #define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
220 #define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
221 #define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
222 #define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
223 #define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
224 #define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
225 #define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
226 #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
227 #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
228 #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
229 #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
230 #define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
231 #define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
232 #define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
233 #define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
234 #define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
235 #define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
236 #define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
237 #define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
238 #define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
239 #define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
240 #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
241 #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
242 #define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
243 #define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
244 #define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
245 #define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
246 #define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
247 #define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
248 #define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
249 #define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
250 #define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
251 #define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
252 #define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
253 #define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
254 #define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
255 #define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
256 #define TEGRA_PIN_PBB6 _GPIO(222)
257 #define TEGRA_PIN_PBB7 _GPIO(223)
258 
259 /* All non-GPIO pins follow */
260 #define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
261 #define _PIN(offset) (NUM_GPIOS + (offset))
262 
263 #define TEGRA_PIN_CRT_HSYNC _PIN(30)
264 #define TEGRA_PIN_CRT_VSYNC _PIN(31)
265 #define TEGRA_PIN_DDC_SCL _PIN(32)
266 #define TEGRA_PIN_DDC_SDA _PIN(33)
267 #define TEGRA_PIN_OWC _PIN(34)
268 #define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
269 #define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
270 #define TEGRA_PIN_PWR_INT_N _PIN(37)
271 #define TEGRA_PIN_CLK_32_K_IN _PIN(38)
272 #define TEGRA_PIN_DDR_COMP_PD _PIN(39)
273 #define TEGRA_PIN_DDR_COMP_PU _PIN(40)
274 #define TEGRA_PIN_DDR_A0 _PIN(41)
275 #define TEGRA_PIN_DDR_A1 _PIN(42)
276 #define TEGRA_PIN_DDR_A2 _PIN(43)
277 #define TEGRA_PIN_DDR_A3 _PIN(44)
278 #define TEGRA_PIN_DDR_A4 _PIN(45)
279 #define TEGRA_PIN_DDR_A5 _PIN(46)
280 #define TEGRA_PIN_DDR_A6 _PIN(47)
281 #define TEGRA_PIN_DDR_A7 _PIN(48)
282 #define TEGRA_PIN_DDR_A8 _PIN(49)
283 #define TEGRA_PIN_DDR_A9 _PIN(50)
284 #define TEGRA_PIN_DDR_A10 _PIN(51)
285 #define TEGRA_PIN_DDR_A11 _PIN(52)
286 #define TEGRA_PIN_DDR_A12 _PIN(53)
287 #define TEGRA_PIN_DDR_A13 _PIN(54)
288 #define TEGRA_PIN_DDR_A14 _PIN(55)
289 #define TEGRA_PIN_DDR_CAS_N _PIN(56)
290 #define TEGRA_PIN_DDR_BA0 _PIN(57)
291 #define TEGRA_PIN_DDR_BA1 _PIN(58)
292 #define TEGRA_PIN_DDR_BA2 _PIN(59)
293 #define TEGRA_PIN_DDR_DQS0P _PIN(60)
294 #define TEGRA_PIN_DDR_DQS0N _PIN(61)
295 #define TEGRA_PIN_DDR_DQS1P _PIN(62)
296 #define TEGRA_PIN_DDR_DQS1N _PIN(63)
297 #define TEGRA_PIN_DDR_DQS2P _PIN(64)
298 #define TEGRA_PIN_DDR_DQS2N _PIN(65)
299 #define TEGRA_PIN_DDR_DQS3P _PIN(66)
300 #define TEGRA_PIN_DDR_DQS3N _PIN(67)
301 #define TEGRA_PIN_DDR_CKE0 _PIN(68)
302 #define TEGRA_PIN_DDR_CKE1 _PIN(69)
303 #define TEGRA_PIN_DDR_CLK _PIN(70)
304 #define TEGRA_PIN_DDR_CLK_N _PIN(71)
305 #define TEGRA_PIN_DDR_DM0 _PIN(72)
306 #define TEGRA_PIN_DDR_DM1 _PIN(73)
307 #define TEGRA_PIN_DDR_DM2 _PIN(74)
308 #define TEGRA_PIN_DDR_DM3 _PIN(75)
309 #define TEGRA_PIN_DDR_ODT _PIN(76)
310 #define TEGRA_PIN_DDR_QUSE0 _PIN(77)
311 #define TEGRA_PIN_DDR_QUSE1 _PIN(78)
312 #define TEGRA_PIN_DDR_QUSE2 _PIN(79)
313 #define TEGRA_PIN_DDR_QUSE3 _PIN(80)
314 #define TEGRA_PIN_DDR_RAS_N _PIN(81)
315 #define TEGRA_PIN_DDR_WE_N _PIN(82)
316 #define TEGRA_PIN_DDR_DQ0 _PIN(83)
317 #define TEGRA_PIN_DDR_DQ1 _PIN(84)
318 #define TEGRA_PIN_DDR_DQ2 _PIN(85)
319 #define TEGRA_PIN_DDR_DQ3 _PIN(86)
320 #define TEGRA_PIN_DDR_DQ4 _PIN(87)
321 #define TEGRA_PIN_DDR_DQ5 _PIN(88)
322 #define TEGRA_PIN_DDR_DQ6 _PIN(89)
323 #define TEGRA_PIN_DDR_DQ7 _PIN(90)
324 #define TEGRA_PIN_DDR_DQ8 _PIN(91)
325 #define TEGRA_PIN_DDR_DQ9 _PIN(92)
326 #define TEGRA_PIN_DDR_DQ10 _PIN(93)
327 #define TEGRA_PIN_DDR_DQ11 _PIN(94)
328 #define TEGRA_PIN_DDR_DQ12 _PIN(95)
329 #define TEGRA_PIN_DDR_DQ13 _PIN(96)
330 #define TEGRA_PIN_DDR_DQ14 _PIN(97)
331 #define TEGRA_PIN_DDR_DQ15 _PIN(98)
332 #define TEGRA_PIN_DDR_DQ16 _PIN(99)
333 #define TEGRA_PIN_DDR_DQ17 _PIN(100)
334 #define TEGRA_PIN_DDR_DQ18 _PIN(101)
335 #define TEGRA_PIN_DDR_DQ19 _PIN(102)
336 #define TEGRA_PIN_DDR_DQ20 _PIN(103)
337 #define TEGRA_PIN_DDR_DQ21 _PIN(104)
338 #define TEGRA_PIN_DDR_DQ22 _PIN(105)
339 #define TEGRA_PIN_DDR_DQ23 _PIN(106)
340 #define TEGRA_PIN_DDR_DQ24 _PIN(107)
341 #define TEGRA_PIN_DDR_DQ25 _PIN(108)
342 #define TEGRA_PIN_DDR_DQ26 _PIN(109)
343 #define TEGRA_PIN_DDR_DQ27 _PIN(110)
344 #define TEGRA_PIN_DDR_DQ28 _PIN(111)
345 #define TEGRA_PIN_DDR_DQ29 _PIN(112)
346 #define TEGRA_PIN_DDR_DQ30 _PIN(113)
347 #define TEGRA_PIN_DDR_DQ31 _PIN(114)
348 #define TEGRA_PIN_DDR_CS0_N _PIN(115)
349 #define TEGRA_PIN_DDR_CS1_N _PIN(116)
350 #define TEGRA_PIN_SYS_RESET _PIN(117)
351 #define TEGRA_PIN_JTAG_TRST_N _PIN(118)
352 #define TEGRA_PIN_JTAG_TDO _PIN(119)
353 #define TEGRA_PIN_JTAG_TMS _PIN(120)
354 #define TEGRA_PIN_JTAG_TCK _PIN(121)
355 #define TEGRA_PIN_JTAG_TDI _PIN(122)
356 #define TEGRA_PIN_TEST_MODE_EN _PIN(123)
357 
358 static const struct pinctrl_pin_desc tegra20_pins[] = {
359  PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
360  PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
361  PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
362  PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
363  PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
364  PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
365  PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
366  PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
367  PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
368  PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
369  PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
370  PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
371  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
372  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
373  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
374  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
375  PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
376  PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
377  PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
378  PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
379  PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
380  PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
381  PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
382  PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
383  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
384  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
385  PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
386  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
387  PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
388  PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
389  PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
390  PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
391  PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
392  PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
393  PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
394  PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
395  PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
396  PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
397  PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
398  PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
399  PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
400  PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
401  PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
402  PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
403  PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
404  PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
405  PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
406  PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
407  PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
408  PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
409  PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
410  PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
411  PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
412  PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
413  PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
414  PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
415  PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
416  PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
417  PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
418  PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
419  PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
420  PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
421  PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
422  PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
423  PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
424  PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
425  PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
426  PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
427  PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
428  PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
429  PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
430  PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
431  PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
432  PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
433  PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
434  PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
435  PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
436  PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
437  PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
438  PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
439  PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
440  PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
441  PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
442  PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
443  PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
444  PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
445  PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
446  PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
447  PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
448  PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
449  PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
450  PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
451  PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
452  PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
453  PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
454  PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
455  PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
456  PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
457  PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
458  PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
459  PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
460  PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
461  PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
462  PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
463  PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
464  PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
465  PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
466  PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
467  PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
468  PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
469  PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
470  PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
471  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
472  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
473  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
474  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
475  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
476  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
477  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
478  PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
479  PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
480  PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
481  PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
482  PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
483  PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
484  PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
485  PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
486  PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
487  PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
488  PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
489  PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
490  PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
491  PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
492  PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
493  PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
494  PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
495  PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
496  PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
497  PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
498  PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
499  PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
500  PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
501  PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
502  PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
503  PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
504  PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
505  PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
506  PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
507  PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
508  PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
509  PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
510  PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
511  PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
512  PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
513  PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
514  PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
515  PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
516  PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
517  PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
518  PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
519  /* PU0..6: GPIO only */
520  PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
521  PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
522  PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
523  PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
524  PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
525  PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
526  PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
527  PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
528  /* PV0..1: GPIO only */
529  PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
530  PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
531  /* PV2..3: Balls are named after GPIO not function */
532  PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
533  PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
534  /* PV4..6: GPIO only */
535  PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
536  PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
537  PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
538  PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
539  PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
540  PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
541  PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
542  PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
543  PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
544  PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
545  PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
546  PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
547  PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
548  PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
549  PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
550  PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
551  PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
552  PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
553  PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
554  PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
555  PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
556  PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
557  PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
558  PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
559  PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
560  PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
561  PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
562  PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
563  PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
564  PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
565  PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
566  PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
567  PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
568  PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
569  PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
570  PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
571  PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
572  PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
573  PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
574  PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
575  PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
576  PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
577  PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
578  PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
579  PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
580  PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
581  PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
582  PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
583  PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
584  PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
585  PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
586  PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
587  PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
588  PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
589  PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
590  PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
591  PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
592  PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
593  PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
594  PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
595  PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
596  PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
597  PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
598  PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
599  PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
600  PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
601  PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
602  PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
603  PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
604  PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
605  PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
606  PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
607  PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
608  PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
609  PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
610  PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
611  PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
612  PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
613  PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
614  PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
615  PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
616  PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
617  PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
618  PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
619  PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
620  PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
621  PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
622  PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
623  PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
624  PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
625  PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
626  PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
627  PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
628  PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
629  PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
630  PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
631  PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
632  PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
633  PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
634  PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
635  PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
636  PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
637  PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
638  PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
639  PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
640  PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
641  PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
642  PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
643  PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
644  PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
645  PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
646  PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
647  PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
648  PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
649  PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
650  PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
651  PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
652  PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
653  PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
654  PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
655  PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
656  PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
657  PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
658  PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
659  PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
660  PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
661  PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
662  PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
663  PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
664  PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
665  PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
666  PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
667  PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
668  PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
669  PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
670  PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
671  PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
672  PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
673  PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
674  PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
675  PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
676  PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
677  PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
678  PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
679  PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
680  PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
681 };
682 
683 static const unsigned ata_pins[] = {
684  TEGRA_PIN_GMI_CS6_N_PI3,
685  TEGRA_PIN_GMI_CS7_N_PI6,
686  TEGRA_PIN_GMI_RST_N_PI4,
687 };
688 
689 static const unsigned atb_pins[] = {
690  TEGRA_PIN_GMI_CS5_N_PI2,
691  TEGRA_PIN_GMI_DPD_PT7,
692 };
693 
694 static const unsigned atc_pins[] = {
695  TEGRA_PIN_GMI_IORDY_PI5,
696  TEGRA_PIN_GMI_WAIT_PI7,
697  TEGRA_PIN_GMI_ADV_N_PK0,
698  TEGRA_PIN_GMI_CLK_PK1,
699  TEGRA_PIN_GMI_CS2_N_PK3,
700  TEGRA_PIN_GMI_CS3_N_PK4,
701  TEGRA_PIN_GMI_CS4_N_PK2,
702  TEGRA_PIN_GMI_AD0_PG0,
703  TEGRA_PIN_GMI_AD1_PG1,
704  TEGRA_PIN_GMI_AD2_PG2,
705  TEGRA_PIN_GMI_AD3_PG3,
706  TEGRA_PIN_GMI_AD4_PG4,
707  TEGRA_PIN_GMI_AD5_PG5,
708  TEGRA_PIN_GMI_AD6_PG6,
709  TEGRA_PIN_GMI_AD7_PG7,
710  TEGRA_PIN_GMI_HIOW_N_PI0,
711  TEGRA_PIN_GMI_HIOR_N_PI1,
712 };
713 
714 static const unsigned atd_pins[] = {
715  TEGRA_PIN_GMI_AD8_PH0,
716  TEGRA_PIN_GMI_AD9_PH1,
717  TEGRA_PIN_GMI_AD10_PH2,
718  TEGRA_PIN_GMI_AD11_PH3,
719 };
720 
721 static const unsigned ate_pins[] = {
722  TEGRA_PIN_GMI_AD12_PH4,
723  TEGRA_PIN_GMI_AD13_PH5,
724  TEGRA_PIN_GMI_AD14_PH6,
725  TEGRA_PIN_GMI_AD15_PH7,
726 };
727 
728 static const unsigned cdev1_pins[] = {
729  TEGRA_PIN_DAP_MCLK1_PW4,
730 };
731 
732 static const unsigned cdev2_pins[] = {
733  TEGRA_PIN_DAP_MCLK2_PW5,
734 };
735 
736 static const unsigned crtp_pins[] = {
737  TEGRA_PIN_CRT_HSYNC,
738  TEGRA_PIN_CRT_VSYNC,
739 };
740 
741 static const unsigned csus_pins[] = {
742  TEGRA_PIN_VI_MCLK_PT1,
743 };
744 
745 static const unsigned dap1_pins[] = {
746  TEGRA_PIN_DAP1_FS_PN0,
747  TEGRA_PIN_DAP1_DIN_PN1,
748  TEGRA_PIN_DAP1_DOUT_PN2,
749  TEGRA_PIN_DAP1_SCLK_PN3,
750 };
751 
752 static const unsigned dap2_pins[] = {
753  TEGRA_PIN_DAP2_FS_PA2,
754  TEGRA_PIN_DAP2_SCLK_PA3,
755  TEGRA_PIN_DAP2_DIN_PA4,
756  TEGRA_PIN_DAP2_DOUT_PA5,
757 };
758 
759 static const unsigned dap3_pins[] = {
760  TEGRA_PIN_DAP3_FS_PP0,
761  TEGRA_PIN_DAP3_DIN_PP1,
762  TEGRA_PIN_DAP3_DOUT_PP2,
763  TEGRA_PIN_DAP3_SCLK_PP3,
764 };
765 
766 static const unsigned dap4_pins[] = {
767  TEGRA_PIN_DAP4_FS_PP4,
768  TEGRA_PIN_DAP4_DIN_PP5,
769  TEGRA_PIN_DAP4_DOUT_PP6,
770  TEGRA_PIN_DAP4_SCLK_PP7,
771 };
772 
773 static const unsigned ddc_pins[] = {
774  TEGRA_PIN_DDC_SCL,
775  TEGRA_PIN_DDC_SDA,
776 };
777 
778 static const unsigned dta_pins[] = {
779  TEGRA_PIN_VI_D0_PT4,
780  TEGRA_PIN_VI_D1_PD5,
781 };
782 
783 static const unsigned dtb_pins[] = {
784  TEGRA_PIN_VI_D10_PT2,
785  TEGRA_PIN_VI_D11_PT3,
786 };
787 
788 static const unsigned dtc_pins[] = {
789  TEGRA_PIN_VI_HSYNC_PD7,
790  TEGRA_PIN_VI_VSYNC_PD6,
791 };
792 
793 static const unsigned dtd_pins[] = {
794  TEGRA_PIN_VI_PCLK_PT0,
795  TEGRA_PIN_VI_D2_PL0,
796  TEGRA_PIN_VI_D3_PL1,
797  TEGRA_PIN_VI_D4_PL2,
798  TEGRA_PIN_VI_D5_PL3,
799  TEGRA_PIN_VI_D6_PL4,
800  TEGRA_PIN_VI_D7_PL5,
801  TEGRA_PIN_VI_D8_PL6,
802  TEGRA_PIN_VI_D9_PL7,
803 };
804 
805 static const unsigned dte_pins[] = {
806  TEGRA_PIN_VI_GP0_PBB1,
807  TEGRA_PIN_VI_GP3_PBB4,
808  TEGRA_PIN_VI_GP4_PBB5,
809  TEGRA_PIN_VI_GP5_PD2,
810  TEGRA_PIN_VI_GP6_PA0,
811 };
812 
813 static const unsigned dtf_pins[] = {
814  TEGRA_PIN_CAM_I2C_SCL_PBB2,
815  TEGRA_PIN_CAM_I2C_SDA_PBB3,
816 };
817 
818 static const unsigned gma_pins[] = {
819  TEGRA_PIN_GMI_AD20_PAA0,
820  TEGRA_PIN_GMI_AD21_PAA1,
821  TEGRA_PIN_GMI_AD22_PAA2,
822  TEGRA_PIN_GMI_AD23_PAA3,
823 };
824 
825 static const unsigned gmb_pins[] = {
826  TEGRA_PIN_GMI_WP_N_PC7,
827 };
828 
829 static const unsigned gmc_pins[] = {
830  TEGRA_PIN_GMI_AD16_PJ7,
831  TEGRA_PIN_GMI_AD17_PB0,
832  TEGRA_PIN_GMI_AD18_PB1,
833  TEGRA_PIN_GMI_AD19_PK7,
834 };
835 
836 static const unsigned gmd_pins[] = {
837  TEGRA_PIN_GMI_CS0_N_PJ0,
838  TEGRA_PIN_GMI_CS1_N_PJ2,
839 };
840 
841 static const unsigned gme_pins[] = {
842  TEGRA_PIN_GMI_AD24_PAA4,
843  TEGRA_PIN_GMI_AD25_PAA5,
844  TEGRA_PIN_GMI_AD26_PAA6,
845  TEGRA_PIN_GMI_AD27_PAA7,
846 };
847 
848 static const unsigned gpu_pins[] = {
849  TEGRA_PIN_PU0,
850  TEGRA_PIN_PU1,
851  TEGRA_PIN_PU2,
852  TEGRA_PIN_PU3,
853  TEGRA_PIN_PU4,
854  TEGRA_PIN_PU5,
855  TEGRA_PIN_PU6,
856 };
857 
858 static const unsigned gpu7_pins[] = {
859  TEGRA_PIN_JTAG_RTCK_PU7,
860 };
861 
862 static const unsigned gpv_pins[] = {
863  TEGRA_PIN_PV4,
864  TEGRA_PIN_PV5,
865  TEGRA_PIN_PV6,
866 };
867 
868 static const unsigned hdint_pins[] = {
869  TEGRA_PIN_HDMI_INT_N_PN7,
870 };
871 
872 static const unsigned i2cp_pins[] = {
873  TEGRA_PIN_PWR_I2C_SCL_PZ6,
874  TEGRA_PIN_PWR_I2C_SDA_PZ7,
875 };
876 
877 static const unsigned irrx_pins[] = {
878  TEGRA_PIN_UART2_RTS_N_PJ6,
879 };
880 
881 static const unsigned irtx_pins[] = {
882  TEGRA_PIN_UART2_CTS_N_PJ5,
883 };
884 
885 static const unsigned kbca_pins[] = {
886  TEGRA_PIN_KB_ROW0_PR0,
887  TEGRA_PIN_KB_ROW1_PR1,
888  TEGRA_PIN_KB_ROW2_PR2,
889 };
890 
891 static const unsigned kbcb_pins[] = {
892  TEGRA_PIN_KB_ROW7_PR7,
893  TEGRA_PIN_KB_ROW8_PS0,
894  TEGRA_PIN_KB_ROW9_PS1,
895  TEGRA_PIN_KB_ROW10_PS2,
896  TEGRA_PIN_KB_ROW11_PS3,
897  TEGRA_PIN_KB_ROW12_PS4,
898  TEGRA_PIN_KB_ROW13_PS5,
899  TEGRA_PIN_KB_ROW14_PS6,
900  TEGRA_PIN_KB_ROW15_PS7,
901 };
902 
903 static const unsigned kbcc_pins[] = {
904  TEGRA_PIN_KB_COL0_PQ0,
905  TEGRA_PIN_KB_COL1_PQ1,
906 };
907 
908 static const unsigned kbcd_pins[] = {
909  TEGRA_PIN_KB_ROW3_PR3,
910  TEGRA_PIN_KB_ROW4_PR4,
911  TEGRA_PIN_KB_ROW5_PR5,
912  TEGRA_PIN_KB_ROW6_PR6,
913 };
914 
915 static const unsigned kbce_pins[] = {
916  TEGRA_PIN_KB_COL7_PQ7,
917 };
918 
919 static const unsigned kbcf_pins[] = {
920  TEGRA_PIN_KB_COL2_PQ2,
921  TEGRA_PIN_KB_COL3_PQ3,
922  TEGRA_PIN_KB_COL4_PQ4,
923  TEGRA_PIN_KB_COL5_PQ5,
924  TEGRA_PIN_KB_COL6_PQ6,
925 };
926 
927 static const unsigned lcsn_pins[] = {
928  TEGRA_PIN_LCD_CS0_N_PN4,
929 };
930 
931 static const unsigned ld0_pins[] = {
932  TEGRA_PIN_LCD_D0_PE0,
933 };
934 
935 static const unsigned ld1_pins[] = {
936  TEGRA_PIN_LCD_D1_PE1,
937 };
938 
939 static const unsigned ld2_pins[] = {
940  TEGRA_PIN_LCD_D2_PE2,
941 };
942 
943 static const unsigned ld3_pins[] = {
944  TEGRA_PIN_LCD_D3_PE3,
945 };
946 
947 static const unsigned ld4_pins[] = {
948  TEGRA_PIN_LCD_D4_PE4,
949 };
950 
951 static const unsigned ld5_pins[] = {
952  TEGRA_PIN_LCD_D5_PE5,
953 };
954 
955 static const unsigned ld6_pins[] = {
956  TEGRA_PIN_LCD_D6_PE6,
957 };
958 
959 static const unsigned ld7_pins[] = {
960  TEGRA_PIN_LCD_D7_PE7,
961 };
962 
963 static const unsigned ld8_pins[] = {
964  TEGRA_PIN_LCD_D8_PF0,
965 };
966 
967 static const unsigned ld9_pins[] = {
968  TEGRA_PIN_LCD_D9_PF1,
969 };
970 
971 static const unsigned ld10_pins[] = {
972  TEGRA_PIN_LCD_D10_PF2,
973 };
974 
975 static const unsigned ld11_pins[] = {
976  TEGRA_PIN_LCD_D11_PF3,
977 };
978 
979 static const unsigned ld12_pins[] = {
980  TEGRA_PIN_LCD_D12_PF4,
981 };
982 
983 static const unsigned ld13_pins[] = {
984  TEGRA_PIN_LCD_D13_PF5,
985 };
986 
987 static const unsigned ld14_pins[] = {
988  TEGRA_PIN_LCD_D14_PF6,
989 };
990 
991 static const unsigned ld15_pins[] = {
992  TEGRA_PIN_LCD_D15_PF7,
993 };
994 
995 static const unsigned ld16_pins[] = {
996  TEGRA_PIN_LCD_D16_PM0,
997 };
998 
999 static const unsigned ld17_pins[] = {
1000  TEGRA_PIN_LCD_D17_PM1,
1001 };
1002 
1003 static const unsigned ldc_pins[] = {
1004  TEGRA_PIN_LCD_DC0_PN6,
1005 };
1006 
1007 static const unsigned ldi_pins[] = {
1008  TEGRA_PIN_LCD_D22_PM6,
1009 };
1010 
1011 static const unsigned lhp0_pins[] = {
1012  TEGRA_PIN_LCD_D21_PM5,
1013 };
1014 
1015 static const unsigned lhp1_pins[] = {
1016  TEGRA_PIN_LCD_D18_PM2,
1017 };
1018 
1019 static const unsigned lhp2_pins[] = {
1020  TEGRA_PIN_LCD_D19_PM3,
1021 };
1022 
1023 static const unsigned lhs_pins[] = {
1024  TEGRA_PIN_LCD_HSYNC_PJ3,
1025 };
1026 
1027 static const unsigned lm0_pins[] = {
1028  TEGRA_PIN_LCD_CS1_N_PW0,
1029 };
1030 
1031 static const unsigned lm1_pins[] = {
1032  TEGRA_PIN_LCD_M1_PW1,
1033 };
1034 
1035 static const unsigned lpp_pins[] = {
1036  TEGRA_PIN_LCD_D23_PM7,
1037 };
1038 
1039 static const unsigned lpw0_pins[] = {
1040  TEGRA_PIN_LCD_PWR0_PB2,
1041 };
1042 
1043 static const unsigned lpw1_pins[] = {
1044  TEGRA_PIN_LCD_PWR1_PC1,
1045 };
1046 
1047 static const unsigned lpw2_pins[] = {
1048  TEGRA_PIN_LCD_PWR2_PC6,
1049 };
1050 
1051 static const unsigned lsc0_pins[] = {
1052  TEGRA_PIN_LCD_PCLK_PB3,
1053 };
1054 
1055 static const unsigned lsc1_pins[] = {
1056  TEGRA_PIN_LCD_WR_N_PZ3,
1057 };
1058 
1059 static const unsigned lsck_pins[] = {
1060  TEGRA_PIN_LCD_SCK_PZ4,
1061 };
1062 
1063 static const unsigned lsda_pins[] = {
1064  TEGRA_PIN_LCD_SDOUT_PN5,
1065 };
1066 
1067 static const unsigned lsdi_pins[] = {
1068  TEGRA_PIN_LCD_SDIN_PZ2,
1069 };
1070 
1071 static const unsigned lspi_pins[] = {
1072  TEGRA_PIN_LCD_DE_PJ1,
1073 };
1074 
1075 static const unsigned lvp0_pins[] = {
1076  TEGRA_PIN_LCD_DC1_PV7,
1077 };
1078 
1079 static const unsigned lvp1_pins[] = {
1080  TEGRA_PIN_LCD_D20_PM4,
1081 };
1082 
1083 static const unsigned lvs_pins[] = {
1084  TEGRA_PIN_LCD_VSYNC_PJ4,
1085 };
1086 
1087 static const unsigned ls_pins[] = {
1088  TEGRA_PIN_LCD_PWR0_PB2,
1089  TEGRA_PIN_LCD_PWR1_PC1,
1090  TEGRA_PIN_LCD_PWR2_PC6,
1091  TEGRA_PIN_LCD_SDIN_PZ2,
1092  TEGRA_PIN_LCD_SDOUT_PN5,
1093  TEGRA_PIN_LCD_WR_N_PZ3,
1094  TEGRA_PIN_LCD_CS0_N_PN4,
1095  TEGRA_PIN_LCD_DC0_PN6,
1096  TEGRA_PIN_LCD_SCK_PZ4,
1097 };
1098 
1099 static const unsigned lc_pins[] = {
1100  TEGRA_PIN_LCD_PCLK_PB3,
1101  TEGRA_PIN_LCD_DE_PJ1,
1102  TEGRA_PIN_LCD_HSYNC_PJ3,
1103  TEGRA_PIN_LCD_VSYNC_PJ4,
1104  TEGRA_PIN_LCD_CS1_N_PW0,
1105  TEGRA_PIN_LCD_M1_PW1,
1106  TEGRA_PIN_LCD_DC1_PV7,
1107  TEGRA_PIN_HDMI_INT_N_PN7,
1108 };
1109 
1110 static const unsigned ld17_0_pins[] = {
1111  TEGRA_PIN_LCD_D0_PE0,
1112  TEGRA_PIN_LCD_D1_PE1,
1113  TEGRA_PIN_LCD_D2_PE2,
1114  TEGRA_PIN_LCD_D3_PE3,
1115  TEGRA_PIN_LCD_D4_PE4,
1116  TEGRA_PIN_LCD_D5_PE5,
1117  TEGRA_PIN_LCD_D6_PE6,
1118  TEGRA_PIN_LCD_D7_PE7,
1119  TEGRA_PIN_LCD_D8_PF0,
1120  TEGRA_PIN_LCD_D9_PF1,
1121  TEGRA_PIN_LCD_D10_PF2,
1122  TEGRA_PIN_LCD_D11_PF3,
1123  TEGRA_PIN_LCD_D12_PF4,
1124  TEGRA_PIN_LCD_D13_PF5,
1125  TEGRA_PIN_LCD_D14_PF6,
1126  TEGRA_PIN_LCD_D15_PF7,
1127  TEGRA_PIN_LCD_D16_PM0,
1128  TEGRA_PIN_LCD_D17_PM1,
1129 };
1130 
1131 static const unsigned ld19_18_pins[] = {
1132  TEGRA_PIN_LCD_D18_PM2,
1133  TEGRA_PIN_LCD_D19_PM3,
1134 };
1135 
1136 static const unsigned ld21_20_pins[] = {
1137  TEGRA_PIN_LCD_D20_PM4,
1138  TEGRA_PIN_LCD_D21_PM5,
1139 };
1140 
1141 static const unsigned ld23_22_pins[] = {
1142  TEGRA_PIN_LCD_D22_PM6,
1143  TEGRA_PIN_LCD_D23_PM7,
1144 };
1145 
1146 static const unsigned owc_pins[] = {
1147  TEGRA_PIN_OWC,
1148 };
1149 
1150 static const unsigned pmc_pins[] = {
1151  TEGRA_PIN_LED_BLINK_PBB0,
1152  TEGRA_PIN_SYS_CLK_REQ_PZ5,
1153  TEGRA_PIN_CORE_PWR_REQ,
1154  TEGRA_PIN_CPU_PWR_REQ,
1155  TEGRA_PIN_PWR_INT_N,
1156 };
1157 
1158 static const unsigned pta_pins[] = {
1159  TEGRA_PIN_GEN2_I2C_SCL_PT5,
1160  TEGRA_PIN_GEN2_I2C_SDA_PT6,
1161 };
1162 
1163 static const unsigned rm_pins[] = {
1164  TEGRA_PIN_GEN1_I2C_SCL_PC4,
1165  TEGRA_PIN_GEN1_I2C_SDA_PC5,
1166 };
1167 
1168 static const unsigned sdb_pins[] = {
1169  TEGRA_PIN_SDIO3_CMD_PA7,
1170 };
1171 
1172 static const unsigned sdc_pins[] = {
1173  TEGRA_PIN_SDIO3_DAT0_PB7,
1174  TEGRA_PIN_SDIO3_DAT1_PB6,
1175  TEGRA_PIN_SDIO3_DAT2_PB5,
1176  TEGRA_PIN_SDIO3_DAT3_PB4,
1177 };
1178 
1179 static const unsigned sdd_pins[] = {
1180  TEGRA_PIN_SDIO3_CLK_PA6,
1181 };
1182 
1183 static const unsigned sdio1_pins[] = {
1184  TEGRA_PIN_SDIO1_CLK_PZ0,
1185  TEGRA_PIN_SDIO1_CMD_PZ1,
1186  TEGRA_PIN_SDIO1_DAT0_PY7,
1187  TEGRA_PIN_SDIO1_DAT1_PY6,
1188  TEGRA_PIN_SDIO1_DAT2_PY5,
1189  TEGRA_PIN_SDIO1_DAT3_PY4,
1190 };
1191 
1192 static const unsigned slxa_pins[] = {
1193  TEGRA_PIN_SDIO3_DAT4_PD1,
1194 };
1195 
1196 static const unsigned slxc_pins[] = {
1197  TEGRA_PIN_SDIO3_DAT6_PD3,
1198 };
1199 
1200 static const unsigned slxd_pins[] = {
1201  TEGRA_PIN_SDIO3_DAT7_PD4,
1202 };
1203 
1204 static const unsigned slxk_pins[] = {
1205  TEGRA_PIN_SDIO3_DAT5_PD0,
1206 };
1207 
1208 static const unsigned spdi_pins[] = {
1209  TEGRA_PIN_SPDIF_IN_PK6,
1210 };
1211 
1212 static const unsigned spdo_pins[] = {
1213  TEGRA_PIN_SPDIF_OUT_PK5,
1214 };
1215 
1216 static const unsigned spia_pins[] = {
1217  TEGRA_PIN_SPI2_MOSI_PX0,
1218 };
1219 
1220 static const unsigned spib_pins[] = {
1221  TEGRA_PIN_SPI2_MISO_PX1,
1222 };
1223 
1224 static const unsigned spic_pins[] = {
1225  TEGRA_PIN_SPI2_CS0_N_PX3,
1226  TEGRA_PIN_SPI2_SCK_PX2,
1227 };
1228 
1229 static const unsigned spid_pins[] = {
1230  TEGRA_PIN_SPI1_MOSI_PX4,
1231 };
1232 
1233 static const unsigned spie_pins[] = {
1234  TEGRA_PIN_SPI1_CS0_N_PX6,
1235  TEGRA_PIN_SPI1_SCK_PX5,
1236 };
1237 
1238 static const unsigned spif_pins[] = {
1239  TEGRA_PIN_SPI1_MISO_PX7,
1240 };
1241 
1242 static const unsigned spig_pins[] = {
1243  TEGRA_PIN_SPI2_CS1_N_PW2,
1244 };
1245 
1246 static const unsigned spih_pins[] = {
1247  TEGRA_PIN_SPI2_CS2_N_PW3,
1248 };
1249 
1250 static const unsigned uaa_pins[] = {
1251  TEGRA_PIN_ULPI_DATA0_PO1,
1252  TEGRA_PIN_ULPI_DATA1_PO2,
1253  TEGRA_PIN_ULPI_DATA2_PO3,
1254  TEGRA_PIN_ULPI_DATA3_PO4,
1255 };
1256 
1257 static const unsigned uab_pins[] = {
1258  TEGRA_PIN_ULPI_DATA4_PO5,
1259  TEGRA_PIN_ULPI_DATA5_PO6,
1260  TEGRA_PIN_ULPI_DATA6_PO7,
1261  TEGRA_PIN_ULPI_DATA7_PO0,
1262 };
1263 
1264 static const unsigned uac_pins[] = {
1265  TEGRA_PIN_PV0,
1266  TEGRA_PIN_PV1,
1267  TEGRA_PIN_PV2,
1268  TEGRA_PIN_PV3,
1269 };
1270 
1271 static const unsigned ck32_pins[] = {
1272  TEGRA_PIN_CLK_32_K_IN,
1273 };
1274 
1275 static const unsigned uad_pins[] = {
1276  TEGRA_PIN_UART2_RXD_PC3,
1277  TEGRA_PIN_UART2_TXD_PC2,
1278 };
1279 
1280 static const unsigned uca_pins[] = {
1281  TEGRA_PIN_UART3_RXD_PW7,
1282  TEGRA_PIN_UART3_TXD_PW6,
1283 };
1284 
1285 static const unsigned ucb_pins[] = {
1286  TEGRA_PIN_UART3_CTS_N_PA1,
1287  TEGRA_PIN_UART3_RTS_N_PC0,
1288 };
1289 
1290 static const unsigned uda_pins[] = {
1291  TEGRA_PIN_ULPI_CLK_PY0,
1292  TEGRA_PIN_ULPI_DIR_PY1,
1293  TEGRA_PIN_ULPI_NXT_PY2,
1294  TEGRA_PIN_ULPI_STP_PY3,
1295 };
1296 
1297 static const unsigned ddrc_pins[] = {
1298  TEGRA_PIN_DDR_COMP_PD,
1299  TEGRA_PIN_DDR_COMP_PU,
1300 };
1301 
1302 static const unsigned pmca_pins[] = {
1303  TEGRA_PIN_LED_BLINK_PBB0,
1304 };
1305 
1306 static const unsigned pmcb_pins[] = {
1307  TEGRA_PIN_SYS_CLK_REQ_PZ5,
1308 };
1309 
1310 static const unsigned pmcc_pins[] = {
1311  TEGRA_PIN_CORE_PWR_REQ,
1312 };
1313 
1314 static const unsigned pmcd_pins[] = {
1315  TEGRA_PIN_CPU_PWR_REQ,
1316 };
1317 
1318 static const unsigned pmce_pins[] = {
1319  TEGRA_PIN_PWR_INT_N,
1320 };
1321 
1322 static const unsigned xm2c_pins[] = {
1323  TEGRA_PIN_DDR_A0,
1324  TEGRA_PIN_DDR_A1,
1325  TEGRA_PIN_DDR_A2,
1326  TEGRA_PIN_DDR_A3,
1327  TEGRA_PIN_DDR_A4,
1328  TEGRA_PIN_DDR_A5,
1329  TEGRA_PIN_DDR_A6,
1330  TEGRA_PIN_DDR_A7,
1331  TEGRA_PIN_DDR_A8,
1332  TEGRA_PIN_DDR_A9,
1333  TEGRA_PIN_DDR_A10,
1334  TEGRA_PIN_DDR_A11,
1335  TEGRA_PIN_DDR_A12,
1336  TEGRA_PIN_DDR_A13,
1337  TEGRA_PIN_DDR_A14,
1338  TEGRA_PIN_DDR_CAS_N,
1339  TEGRA_PIN_DDR_BA0,
1340  TEGRA_PIN_DDR_BA1,
1341  TEGRA_PIN_DDR_BA2,
1342  TEGRA_PIN_DDR_DQS0P,
1343  TEGRA_PIN_DDR_DQS0N,
1344  TEGRA_PIN_DDR_DQS1P,
1345  TEGRA_PIN_DDR_DQS1N,
1346  TEGRA_PIN_DDR_DQS2P,
1347  TEGRA_PIN_DDR_DQS2N,
1348  TEGRA_PIN_DDR_DQS3P,
1349  TEGRA_PIN_DDR_DQS3N,
1350  TEGRA_PIN_DDR_CS0_N,
1351  TEGRA_PIN_DDR_CS1_N,
1352  TEGRA_PIN_DDR_CKE0,
1353  TEGRA_PIN_DDR_CKE1,
1354  TEGRA_PIN_DDR_CLK,
1355  TEGRA_PIN_DDR_CLK_N,
1356  TEGRA_PIN_DDR_DM0,
1357  TEGRA_PIN_DDR_DM1,
1358  TEGRA_PIN_DDR_DM2,
1359  TEGRA_PIN_DDR_DM3,
1360  TEGRA_PIN_DDR_ODT,
1361  TEGRA_PIN_DDR_RAS_N,
1362  TEGRA_PIN_DDR_WE_N,
1363  TEGRA_PIN_DDR_QUSE0,
1364  TEGRA_PIN_DDR_QUSE1,
1365  TEGRA_PIN_DDR_QUSE2,
1366  TEGRA_PIN_DDR_QUSE3,
1367 };
1368 
1369 static const unsigned xm2d_pins[] = {
1370  TEGRA_PIN_DDR_DQ0,
1371  TEGRA_PIN_DDR_DQ1,
1372  TEGRA_PIN_DDR_DQ2,
1373  TEGRA_PIN_DDR_DQ3,
1374  TEGRA_PIN_DDR_DQ4,
1375  TEGRA_PIN_DDR_DQ5,
1376  TEGRA_PIN_DDR_DQ6,
1377  TEGRA_PIN_DDR_DQ7,
1378  TEGRA_PIN_DDR_DQ8,
1379  TEGRA_PIN_DDR_DQ9,
1380  TEGRA_PIN_DDR_DQ10,
1381  TEGRA_PIN_DDR_DQ11,
1382  TEGRA_PIN_DDR_DQ12,
1383  TEGRA_PIN_DDR_DQ13,
1384  TEGRA_PIN_DDR_DQ14,
1385  TEGRA_PIN_DDR_DQ15,
1386  TEGRA_PIN_DDR_DQ16,
1387  TEGRA_PIN_DDR_DQ17,
1388  TEGRA_PIN_DDR_DQ18,
1389  TEGRA_PIN_DDR_DQ19,
1390  TEGRA_PIN_DDR_DQ20,
1391  TEGRA_PIN_DDR_DQ21,
1392  TEGRA_PIN_DDR_DQ22,
1393  TEGRA_PIN_DDR_DQ23,
1394  TEGRA_PIN_DDR_DQ24,
1395  TEGRA_PIN_DDR_DQ25,
1396  TEGRA_PIN_DDR_DQ26,
1397  TEGRA_PIN_DDR_DQ27,
1398  TEGRA_PIN_DDR_DQ28,
1399  TEGRA_PIN_DDR_DQ29,
1400  TEGRA_PIN_DDR_DQ30,
1401  TEGRA_PIN_DDR_DQ31,
1402 };
1403 
1404 static const unsigned drive_ao1_pins[] = {
1405  TEGRA_PIN_SYS_RESET,
1406  TEGRA_PIN_PWR_I2C_SCL_PZ6,
1407  TEGRA_PIN_PWR_I2C_SDA_PZ7,
1408  TEGRA_PIN_KB_ROW0_PR0,
1409  TEGRA_PIN_KB_ROW1_PR1,
1410  TEGRA_PIN_KB_ROW2_PR2,
1411  TEGRA_PIN_KB_ROW3_PR3,
1412  TEGRA_PIN_KB_ROW4_PR4,
1413  TEGRA_PIN_KB_ROW5_PR5,
1414  TEGRA_PIN_KB_ROW6_PR6,
1415  TEGRA_PIN_KB_ROW7_PR7,
1416 };
1417 
1418 static const unsigned drive_ao2_pins[] = {
1419  TEGRA_PIN_KB_ROW8_PS0,
1420  TEGRA_PIN_KB_ROW9_PS1,
1421  TEGRA_PIN_KB_ROW10_PS2,
1422  TEGRA_PIN_KB_ROW11_PS3,
1423  TEGRA_PIN_KB_ROW12_PS4,
1424  TEGRA_PIN_KB_ROW13_PS5,
1425  TEGRA_PIN_KB_ROW14_PS6,
1426  TEGRA_PIN_KB_ROW15_PS7,
1427  TEGRA_PIN_KB_COL0_PQ0,
1428  TEGRA_PIN_KB_COL1_PQ1,
1429  TEGRA_PIN_KB_COL2_PQ2,
1430  TEGRA_PIN_KB_COL3_PQ3,
1431  TEGRA_PIN_KB_COL4_PQ4,
1432  TEGRA_PIN_KB_COL5_PQ5,
1433  TEGRA_PIN_KB_COL6_PQ6,
1434  TEGRA_PIN_KB_COL7_PQ7,
1435  TEGRA_PIN_LED_BLINK_PBB0,
1436  TEGRA_PIN_SYS_CLK_REQ_PZ5,
1437  TEGRA_PIN_CORE_PWR_REQ,
1438  TEGRA_PIN_CPU_PWR_REQ,
1439  TEGRA_PIN_PWR_INT_N,
1440  TEGRA_PIN_CLK_32_K_IN,
1441 };
1442 
1443 static const unsigned drive_at1_pins[] = {
1444  TEGRA_PIN_GMI_IORDY_PI5,
1445  TEGRA_PIN_GMI_AD8_PH0,
1446  TEGRA_PIN_GMI_AD9_PH1,
1447  TEGRA_PIN_GMI_AD10_PH2,
1448  TEGRA_PIN_GMI_AD11_PH3,
1449  TEGRA_PIN_GMI_AD12_PH4,
1450  TEGRA_PIN_GMI_AD13_PH5,
1451  TEGRA_PIN_GMI_AD14_PH6,
1452  TEGRA_PIN_GMI_AD15_PH7,
1453  TEGRA_PIN_GMI_CS7_N_PI6,
1454  TEGRA_PIN_GMI_DPD_PT7,
1455  TEGRA_PIN_GEN2_I2C_SCL_PT5,
1456  TEGRA_PIN_GEN2_I2C_SDA_PT6,
1457 };
1458 
1459 static const unsigned drive_at2_pins[] = {
1460  TEGRA_PIN_GMI_WAIT_PI7,
1461  TEGRA_PIN_GMI_ADV_N_PK0,
1462  TEGRA_PIN_GMI_CLK_PK1,
1463  TEGRA_PIN_GMI_CS6_N_PI3,
1464  TEGRA_PIN_GMI_CS5_N_PI2,
1465  TEGRA_PIN_GMI_CS4_N_PK2,
1466  TEGRA_PIN_GMI_CS3_N_PK4,
1467  TEGRA_PIN_GMI_CS2_N_PK3,
1468  TEGRA_PIN_GMI_AD0_PG0,
1469  TEGRA_PIN_GMI_AD1_PG1,
1470  TEGRA_PIN_GMI_AD2_PG2,
1471  TEGRA_PIN_GMI_AD3_PG3,
1472  TEGRA_PIN_GMI_AD4_PG4,
1473  TEGRA_PIN_GMI_AD5_PG5,
1474  TEGRA_PIN_GMI_AD6_PG6,
1475  TEGRA_PIN_GMI_AD7_PG7,
1476  TEGRA_PIN_GMI_HIOW_N_PI0,
1477  TEGRA_PIN_GMI_HIOR_N_PI1,
1478  TEGRA_PIN_GMI_RST_N_PI4,
1479 };
1480 
1481 static const unsigned drive_cdev1_pins[] = {
1482  TEGRA_PIN_DAP_MCLK1_PW4,
1483 };
1484 
1485 static const unsigned drive_cdev2_pins[] = {
1486  TEGRA_PIN_DAP_MCLK2_PW5,
1487 };
1488 
1489 static const unsigned drive_csus_pins[] = {
1490  TEGRA_PIN_VI_MCLK_PT1,
1491 };
1492 
1493 static const unsigned drive_dap1_pins[] = {
1494  TEGRA_PIN_DAP1_FS_PN0,
1495  TEGRA_PIN_DAP1_DIN_PN1,
1496  TEGRA_PIN_DAP1_DOUT_PN2,
1497  TEGRA_PIN_DAP1_SCLK_PN3,
1498  TEGRA_PIN_SPDIF_OUT_PK5,
1499  TEGRA_PIN_SPDIF_IN_PK6,
1500 };
1501 
1502 static const unsigned drive_dap2_pins[] = {
1503  TEGRA_PIN_DAP2_FS_PA2,
1504  TEGRA_PIN_DAP2_SCLK_PA3,
1505  TEGRA_PIN_DAP2_DIN_PA4,
1506  TEGRA_PIN_DAP2_DOUT_PA5,
1507 };
1508 
1509 static const unsigned drive_dap3_pins[] = {
1510  TEGRA_PIN_DAP3_FS_PP0,
1511  TEGRA_PIN_DAP3_DIN_PP1,
1512  TEGRA_PIN_DAP3_DOUT_PP2,
1513  TEGRA_PIN_DAP3_SCLK_PP3,
1514 };
1515 
1516 static const unsigned drive_dap4_pins[] = {
1517  TEGRA_PIN_DAP4_FS_PP4,
1518  TEGRA_PIN_DAP4_DIN_PP5,
1519  TEGRA_PIN_DAP4_DOUT_PP6,
1520  TEGRA_PIN_DAP4_SCLK_PP7,
1521 };
1522 
1523 static const unsigned drive_dbg_pins[] = {
1524  TEGRA_PIN_PU0,
1525  TEGRA_PIN_PU1,
1526  TEGRA_PIN_PU2,
1527  TEGRA_PIN_PU3,
1528  TEGRA_PIN_PU4,
1529  TEGRA_PIN_PU5,
1530  TEGRA_PIN_PU6,
1531  TEGRA_PIN_JTAG_RTCK_PU7,
1532  TEGRA_PIN_GEN1_I2C_SDA_PC5,
1533  TEGRA_PIN_GEN1_I2C_SCL_PC4,
1534  TEGRA_PIN_JTAG_TRST_N,
1535  TEGRA_PIN_JTAG_TDO,
1536  TEGRA_PIN_JTAG_TMS,
1537  TEGRA_PIN_JTAG_TCK,
1538  TEGRA_PIN_JTAG_TDI,
1539  TEGRA_PIN_TEST_MODE_EN,
1540 };
1541 
1542 static const unsigned drive_lcd1_pins[] = {
1543  TEGRA_PIN_LCD_PWR1_PC1,
1544  TEGRA_PIN_LCD_PWR2_PC6,
1545  TEGRA_PIN_LCD_SDIN_PZ2,
1546  TEGRA_PIN_LCD_SDOUT_PN5,
1547  TEGRA_PIN_LCD_WR_N_PZ3,
1548  TEGRA_PIN_LCD_CS0_N_PN4,
1549  TEGRA_PIN_LCD_DC0_PN6,
1550  TEGRA_PIN_LCD_SCK_PZ4,
1551 };
1552 
1553 static const unsigned drive_lcd2_pins[] = {
1554  TEGRA_PIN_LCD_PWR0_PB2,
1555  TEGRA_PIN_LCD_PCLK_PB3,
1556  TEGRA_PIN_LCD_DE_PJ1,
1557  TEGRA_PIN_LCD_HSYNC_PJ3,
1558  TEGRA_PIN_LCD_VSYNC_PJ4,
1559  TEGRA_PIN_LCD_D0_PE0,
1560  TEGRA_PIN_LCD_D1_PE1,
1561  TEGRA_PIN_LCD_D2_PE2,
1562  TEGRA_PIN_LCD_D3_PE3,
1563  TEGRA_PIN_LCD_D4_PE4,
1564  TEGRA_PIN_LCD_D5_PE5,
1565  TEGRA_PIN_LCD_D6_PE6,
1566  TEGRA_PIN_LCD_D7_PE7,
1567  TEGRA_PIN_LCD_D8_PF0,
1568  TEGRA_PIN_LCD_D9_PF1,
1569  TEGRA_PIN_LCD_D10_PF2,
1570  TEGRA_PIN_LCD_D11_PF3,
1571  TEGRA_PIN_LCD_D12_PF4,
1572  TEGRA_PIN_LCD_D13_PF5,
1573  TEGRA_PIN_LCD_D14_PF6,
1574  TEGRA_PIN_LCD_D15_PF7,
1575  TEGRA_PIN_LCD_D16_PM0,
1576  TEGRA_PIN_LCD_D17_PM1,
1577  TEGRA_PIN_LCD_D18_PM2,
1578  TEGRA_PIN_LCD_D19_PM3,
1579  TEGRA_PIN_LCD_D20_PM4,
1580  TEGRA_PIN_LCD_D21_PM5,
1581  TEGRA_PIN_LCD_D22_PM6,
1582  TEGRA_PIN_LCD_D23_PM7,
1583  TEGRA_PIN_LCD_CS1_N_PW0,
1584  TEGRA_PIN_LCD_M1_PW1,
1585  TEGRA_PIN_LCD_DC1_PV7,
1586  TEGRA_PIN_HDMI_INT_N_PN7,
1587 };
1588 
1589 static const unsigned drive_sdmmc2_pins[] = {
1590  TEGRA_PIN_SDIO3_DAT4_PD1,
1591  TEGRA_PIN_SDIO3_DAT5_PD0,
1592  TEGRA_PIN_SDIO3_DAT6_PD3,
1593  TEGRA_PIN_SDIO3_DAT7_PD4,
1594 };
1595 
1596 static const unsigned drive_sdmmc3_pins[] = {
1597  TEGRA_PIN_SDIO3_CLK_PA6,
1598  TEGRA_PIN_SDIO3_CMD_PA7,
1599  TEGRA_PIN_SDIO3_DAT0_PB7,
1600  TEGRA_PIN_SDIO3_DAT1_PB6,
1601  TEGRA_PIN_SDIO3_DAT2_PB5,
1602  TEGRA_PIN_SDIO3_DAT3_PB4,
1603  TEGRA_PIN_PV4,
1604  TEGRA_PIN_PV5,
1605  TEGRA_PIN_PV6,
1606 };
1607 
1608 static const unsigned drive_spi_pins[] = {
1609  TEGRA_PIN_SPI2_MOSI_PX0,
1610  TEGRA_PIN_SPI2_MISO_PX1,
1611  TEGRA_PIN_SPI2_SCK_PX2,
1612  TEGRA_PIN_SPI2_CS0_N_PX3,
1613  TEGRA_PIN_SPI1_MOSI_PX4,
1614  TEGRA_PIN_SPI1_SCK_PX5,
1615  TEGRA_PIN_SPI1_CS0_N_PX6,
1616  TEGRA_PIN_SPI1_MISO_PX7,
1617  TEGRA_PIN_SPI2_CS1_N_PW2,
1618  TEGRA_PIN_SPI2_CS2_N_PW3,
1619 };
1620 
1621 static const unsigned drive_uaa_pins[] = {
1622  TEGRA_PIN_ULPI_DATA0_PO1,
1623  TEGRA_PIN_ULPI_DATA1_PO2,
1624  TEGRA_PIN_ULPI_DATA2_PO3,
1625  TEGRA_PIN_ULPI_DATA3_PO4,
1626 };
1627 
1628 static const unsigned drive_uab_pins[] = {
1629  TEGRA_PIN_ULPI_DATA4_PO5,
1630  TEGRA_PIN_ULPI_DATA5_PO6,
1631  TEGRA_PIN_ULPI_DATA6_PO7,
1632  TEGRA_PIN_ULPI_DATA7_PO0,
1633  TEGRA_PIN_PV0,
1634  TEGRA_PIN_PV1,
1635  TEGRA_PIN_PV2,
1636  TEGRA_PIN_PV3,
1637 };
1638 
1639 static const unsigned drive_uart2_pins[] = {
1640  TEGRA_PIN_UART2_TXD_PC2,
1641  TEGRA_PIN_UART2_RXD_PC3,
1642  TEGRA_PIN_UART2_RTS_N_PJ6,
1643  TEGRA_PIN_UART2_CTS_N_PJ5,
1644 };
1645 
1646 static const unsigned drive_uart3_pins[] = {
1647  TEGRA_PIN_UART3_TXD_PW6,
1648  TEGRA_PIN_UART3_RXD_PW7,
1649  TEGRA_PIN_UART3_RTS_N_PC0,
1650  TEGRA_PIN_UART3_CTS_N_PA1,
1651 };
1652 
1653 static const unsigned drive_vi1_pins[] = {
1654  TEGRA_PIN_VI_D0_PT4,
1655  TEGRA_PIN_VI_D1_PD5,
1656  TEGRA_PIN_VI_D2_PL0,
1657  TEGRA_PIN_VI_D3_PL1,
1658  TEGRA_PIN_VI_D4_PL2,
1659  TEGRA_PIN_VI_D5_PL3,
1660  TEGRA_PIN_VI_D6_PL4,
1661  TEGRA_PIN_VI_D7_PL5,
1662  TEGRA_PIN_VI_D8_PL6,
1663  TEGRA_PIN_VI_D9_PL7,
1664  TEGRA_PIN_VI_D10_PT2,
1665  TEGRA_PIN_VI_D11_PT3,
1666  TEGRA_PIN_VI_PCLK_PT0,
1667  TEGRA_PIN_VI_VSYNC_PD6,
1668  TEGRA_PIN_VI_HSYNC_PD7,
1669 };
1670 
1671 static const unsigned drive_vi2_pins[] = {
1672  TEGRA_PIN_VI_GP0_PBB1,
1673  TEGRA_PIN_CAM_I2C_SCL_PBB2,
1674  TEGRA_PIN_CAM_I2C_SDA_PBB3,
1675  TEGRA_PIN_VI_GP3_PBB4,
1676  TEGRA_PIN_VI_GP4_PBB5,
1677  TEGRA_PIN_VI_GP5_PD2,
1678  TEGRA_PIN_VI_GP6_PA0,
1679 };
1680 
1681 static const unsigned drive_xm2a_pins[] = {
1682  TEGRA_PIN_DDR_A0,
1683  TEGRA_PIN_DDR_A1,
1684  TEGRA_PIN_DDR_A2,
1685  TEGRA_PIN_DDR_A3,
1686  TEGRA_PIN_DDR_A4,
1687  TEGRA_PIN_DDR_A5,
1688  TEGRA_PIN_DDR_A6,
1689  TEGRA_PIN_DDR_A7,
1690  TEGRA_PIN_DDR_A8,
1691  TEGRA_PIN_DDR_A9,
1692  TEGRA_PIN_DDR_A10,
1693  TEGRA_PIN_DDR_A11,
1694  TEGRA_PIN_DDR_A12,
1695  TEGRA_PIN_DDR_A13,
1696  TEGRA_PIN_DDR_A14,
1697  TEGRA_PIN_DDR_BA0,
1698  TEGRA_PIN_DDR_BA1,
1699  TEGRA_PIN_DDR_BA2,
1700  TEGRA_PIN_DDR_CS0_N,
1701  TEGRA_PIN_DDR_CS1_N,
1702  TEGRA_PIN_DDR_ODT,
1703  TEGRA_PIN_DDR_RAS_N,
1704  TEGRA_PIN_DDR_CAS_N,
1705  TEGRA_PIN_DDR_WE_N,
1706  TEGRA_PIN_DDR_CKE0,
1707  TEGRA_PIN_DDR_CKE1,
1708 };
1709 
1710 static const unsigned drive_xm2c_pins[] = {
1711  TEGRA_PIN_DDR_DQS0P,
1712  TEGRA_PIN_DDR_DQS0N,
1713  TEGRA_PIN_DDR_DQS1P,
1714  TEGRA_PIN_DDR_DQS1N,
1715  TEGRA_PIN_DDR_DQS2P,
1716  TEGRA_PIN_DDR_DQS2N,
1717  TEGRA_PIN_DDR_DQS3P,
1718  TEGRA_PIN_DDR_DQS3N,
1719  TEGRA_PIN_DDR_QUSE0,
1720  TEGRA_PIN_DDR_QUSE1,
1721  TEGRA_PIN_DDR_QUSE2,
1722  TEGRA_PIN_DDR_QUSE3,
1723 };
1724 
1725 static const unsigned drive_xm2d_pins[] = {
1726  TEGRA_PIN_DDR_DQ0,
1727  TEGRA_PIN_DDR_DQ1,
1728  TEGRA_PIN_DDR_DQ2,
1729  TEGRA_PIN_DDR_DQ3,
1730  TEGRA_PIN_DDR_DQ4,
1731  TEGRA_PIN_DDR_DQ5,
1732  TEGRA_PIN_DDR_DQ6,
1733  TEGRA_PIN_DDR_DQ7,
1734  TEGRA_PIN_DDR_DQ8,
1735  TEGRA_PIN_DDR_DQ9,
1736  TEGRA_PIN_DDR_DQ10,
1737  TEGRA_PIN_DDR_DQ11,
1738  TEGRA_PIN_DDR_DQ12,
1739  TEGRA_PIN_DDR_DQ13,
1740  TEGRA_PIN_DDR_DQ14,
1741  TEGRA_PIN_DDR_DQ15,
1742  TEGRA_PIN_DDR_DQ16,
1743  TEGRA_PIN_DDR_DQ17,
1744  TEGRA_PIN_DDR_DQ18,
1745  TEGRA_PIN_DDR_DQ19,
1746  TEGRA_PIN_DDR_DQ20,
1747  TEGRA_PIN_DDR_DQ21,
1748  TEGRA_PIN_DDR_DQ22,
1749  TEGRA_PIN_DDR_DQ23,
1750  TEGRA_PIN_DDR_DQ24,
1751  TEGRA_PIN_DDR_DQ25,
1752  TEGRA_PIN_DDR_DQ26,
1753  TEGRA_PIN_DDR_DQ27,
1754  TEGRA_PIN_DDR_DQ28,
1755  TEGRA_PIN_DDR_DQ29,
1756  TEGRA_PIN_DDR_DQ30,
1757  TEGRA_PIN_DDR_DQ31,
1758  TEGRA_PIN_DDR_DM0,
1759  TEGRA_PIN_DDR_DM1,
1760  TEGRA_PIN_DDR_DM2,
1761  TEGRA_PIN_DDR_DM3,
1762 };
1763 
1764 static const unsigned drive_xm2clk_pins[] = {
1765  TEGRA_PIN_DDR_CLK,
1766  TEGRA_PIN_DDR_CLK_N,
1767 };
1768 
1769 static const unsigned drive_sdio1_pins[] = {
1770  TEGRA_PIN_SDIO1_CLK_PZ0,
1771  TEGRA_PIN_SDIO1_CMD_PZ1,
1772  TEGRA_PIN_SDIO1_DAT0_PY7,
1773  TEGRA_PIN_SDIO1_DAT1_PY6,
1774  TEGRA_PIN_SDIO1_DAT2_PY5,
1775  TEGRA_PIN_SDIO1_DAT3_PY4,
1776 };
1777 
1778 static const unsigned drive_crt_pins[] = {
1779  TEGRA_PIN_CRT_HSYNC,
1780  TEGRA_PIN_CRT_VSYNC,
1781 };
1782 
1783 static const unsigned drive_ddc_pins[] = {
1784  TEGRA_PIN_DDC_SCL,
1785  TEGRA_PIN_DDC_SDA,
1786 };
1787 
1788 static const unsigned drive_gma_pins[] = {
1789  TEGRA_PIN_GMI_AD20_PAA0,
1790  TEGRA_PIN_GMI_AD21_PAA1,
1791  TEGRA_PIN_GMI_AD22_PAA2,
1792  TEGRA_PIN_GMI_AD23_PAA3,
1793 };
1794 
1795 static const unsigned drive_gmb_pins[] = {
1796  TEGRA_PIN_GMI_WP_N_PC7,
1797 };
1798 
1799 static const unsigned drive_gmc_pins[] = {
1800  TEGRA_PIN_GMI_AD16_PJ7,
1801  TEGRA_PIN_GMI_AD17_PB0,
1802  TEGRA_PIN_GMI_AD18_PB1,
1803  TEGRA_PIN_GMI_AD19_PK7,
1804 };
1805 
1806 static const unsigned drive_gmd_pins[] = {
1807  TEGRA_PIN_GMI_CS0_N_PJ0,
1808  TEGRA_PIN_GMI_CS1_N_PJ2,
1809 };
1810 
1811 static const unsigned drive_gme_pins[] = {
1812  TEGRA_PIN_GMI_AD24_PAA4,
1813  TEGRA_PIN_GMI_AD25_PAA5,
1814  TEGRA_PIN_GMI_AD26_PAA6,
1815  TEGRA_PIN_GMI_AD27_PAA7,
1816 };
1817 
1818 static const unsigned drive_owr_pins[] = {
1819  TEGRA_PIN_OWC,
1820 };
1821 
1822 static const unsigned drive_uda_pins[] = {
1823  TEGRA_PIN_ULPI_CLK_PY0,
1824  TEGRA_PIN_ULPI_DIR_PY1,
1825  TEGRA_PIN_ULPI_NXT_PY2,
1826  TEGRA_PIN_ULPI_STP_PY3,
1827 };
1828 
1829 enum tegra_mux {
1830  TEGRA_MUX_AHB_CLK,
1831  TEGRA_MUX_APB_CLK,
1832  TEGRA_MUX_AUDIO_SYNC,
1833  TEGRA_MUX_CRT,
1834  TEGRA_MUX_DAP1,
1835  TEGRA_MUX_DAP2,
1836  TEGRA_MUX_DAP3,
1837  TEGRA_MUX_DAP4,
1838  TEGRA_MUX_DAP5,
1839  TEGRA_MUX_DISPLAYA,
1840  TEGRA_MUX_DISPLAYB,
1841  TEGRA_MUX_EMC_TEST0_DLL,
1842  TEGRA_MUX_EMC_TEST1_DLL,
1843  TEGRA_MUX_GMI,
1844  TEGRA_MUX_GMI_INT,
1845  TEGRA_MUX_HDMI,
1846  TEGRA_MUX_I2CP,
1847  TEGRA_MUX_I2C1,
1848  TEGRA_MUX_I2C2,
1849  TEGRA_MUX_I2C3,
1850  TEGRA_MUX_IDE,
1851  TEGRA_MUX_IRDA,
1852  TEGRA_MUX_KBC,
1853  TEGRA_MUX_MIO,
1854  TEGRA_MUX_MIPI_HS,
1855  TEGRA_MUX_NAND,
1856  TEGRA_MUX_OSC,
1857  TEGRA_MUX_OWR,
1858  TEGRA_MUX_PCIE,
1859  TEGRA_MUX_PLLA_OUT,
1860  TEGRA_MUX_PLLC_OUT1,
1861  TEGRA_MUX_PLLM_OUT1,
1862  TEGRA_MUX_PLLP_OUT2,
1863  TEGRA_MUX_PLLP_OUT3,
1864  TEGRA_MUX_PLLP_OUT4,
1865  TEGRA_MUX_PWM,
1866  TEGRA_MUX_PWR_INTR,
1867  TEGRA_MUX_PWR_ON,
1868  TEGRA_MUX_RSVD1,
1869  TEGRA_MUX_RSVD2,
1870  TEGRA_MUX_RSVD3,
1871  TEGRA_MUX_RSVD4,
1872  TEGRA_MUX_RTCK,
1873  TEGRA_MUX_SDIO1,
1874  TEGRA_MUX_SDIO2,
1875  TEGRA_MUX_SDIO3,
1876  TEGRA_MUX_SDIO4,
1877  TEGRA_MUX_SFLASH,
1878  TEGRA_MUX_SPDIF,
1879  TEGRA_MUX_SPI1,
1880  TEGRA_MUX_SPI2,
1881  TEGRA_MUX_SPI2_ALT,
1882  TEGRA_MUX_SPI3,
1883  TEGRA_MUX_SPI4,
1884  TEGRA_MUX_TRACE,
1885  TEGRA_MUX_TWC,
1886  TEGRA_MUX_UARTA,
1887  TEGRA_MUX_UARTB,
1888  TEGRA_MUX_UARTC,
1889  TEGRA_MUX_UARTD,
1890  TEGRA_MUX_UARTE,
1891  TEGRA_MUX_ULPI,
1892  TEGRA_MUX_VI,
1893  TEGRA_MUX_VI_SENSOR_CLK,
1894  TEGRA_MUX_XIO,
1895 };
1896 
1897 static const char * const ahb_clk_groups[] = {
1898  "cdev2",
1899 };
1900 
1901 static const char * const apb_clk_groups[] = {
1902  "cdev2",
1903 };
1904 
1905 static const char * const audio_sync_groups[] = {
1906  "cdev1",
1907 };
1908 
1909 static const char * const crt_groups[] = {
1910  "crtp",
1911  "lm1",
1912 };
1913 
1914 static const char * const dap1_groups[] = {
1915  "dap1",
1916 };
1917 
1918 static const char * const dap2_groups[] = {
1919  "dap2",
1920 };
1921 
1922 static const char * const dap3_groups[] = {
1923  "dap3",
1924 };
1925 
1926 static const char * const dap4_groups[] = {
1927  "dap4",
1928 };
1929 
1930 static const char * const dap5_groups[] = {
1931  "gme",
1932 };
1933 
1934 static const char * const displaya_groups[] = {
1935  "lcsn",
1936  "ld0",
1937  "ld1",
1938  "ld10",
1939  "ld11",
1940  "ld12",
1941  "ld13",
1942  "ld14",
1943  "ld15",
1944  "ld16",
1945  "ld17",
1946  "ld2",
1947  "ld3",
1948  "ld4",
1949  "ld5",
1950  "ld6",
1951  "ld7",
1952  "ld8",
1953  "ld9",
1954  "ldc",
1955  "ldi",
1956  "lhp0",
1957  "lhp1",
1958  "lhp2",
1959  "lhs",
1960  "lm0",
1961  "lm1",
1962  "lpp",
1963  "lpw0",
1964  "lpw1",
1965  "lpw2",
1966  "lsc0",
1967  "lsc1",
1968  "lsck",
1969  "lsda",
1970  "lsdi",
1971  "lspi",
1972  "lvp0",
1973  "lvp1",
1974  "lvs",
1975 };
1976 
1977 static const char * const displayb_groups[] = {
1978  "lcsn",
1979  "ld0",
1980  "ld1",
1981  "ld10",
1982  "ld11",
1983  "ld12",
1984  "ld13",
1985  "ld14",
1986  "ld15",
1987  "ld16",
1988  "ld17",
1989  "ld2",
1990  "ld3",
1991  "ld4",
1992  "ld5",
1993  "ld6",
1994  "ld7",
1995  "ld8",
1996  "ld9",
1997  "ldc",
1998  "ldi",
1999  "lhp0",
2000  "lhp1",
2001  "lhp2",
2002  "lhs",
2003  "lm0",
2004  "lm1",
2005  "lpp",
2006  "lpw0",
2007  "lpw1",
2008  "lpw2",
2009  "lsc0",
2010  "lsc1",
2011  "lsck",
2012  "lsda",
2013  "lsdi",
2014  "lspi",
2015  "lvp0",
2016  "lvp1",
2017  "lvs",
2018 };
2019 
2020 static const char * const emc_test0_dll_groups[] = {
2021  "kbca",
2022 };
2023 
2024 static const char * const emc_test1_dll_groups[] = {
2025  "kbcc",
2026 };
2027 
2028 static const char * const gmi_groups[] = {
2029  "ata",
2030  "atb",
2031  "atc",
2032  "atd",
2033  "ate",
2034  "dap1",
2035  "dap2",
2036  "dap4",
2037  "gma",
2038  "gmb",
2039  "gmc",
2040  "gmd",
2041  "gme",
2042  "gpu",
2043  "irrx",
2044  "irtx",
2045  "pta",
2046  "spia",
2047  "spib",
2048  "spic",
2049  "spid",
2050  "spie",
2051  "uca",
2052  "ucb",
2053 };
2054 
2055 static const char * const gmi_int_groups[] = {
2056  "gmb",
2057 };
2058 
2059 static const char * const hdmi_groups[] = {
2060  "hdint",
2061  "lpw0",
2062  "lpw2",
2063  "lsc1",
2064  "lsck",
2065  "lsda",
2066  "lspi",
2067  "pta",
2068 };
2069 
2070 static const char * const i2cp_groups[] = {
2071  "i2cp",
2072 };
2073 
2074 static const char * const i2c1_groups[] = {
2075  "rm",
2076  "spdi",
2077  "spdo",
2078  "spig",
2079  "spih",
2080 };
2081 
2082 static const char * const i2c2_groups[] = {
2083  "ddc",
2084  "pta",
2085 };
2086 
2087 static const char * const i2c3_groups[] = {
2088  "dtf",
2089 };
2090 
2091 static const char * const ide_groups[] = {
2092  "ata",
2093  "atb",
2094  "atc",
2095  "atd",
2096  "ate",
2097  "gmb",
2098 };
2099 
2100 static const char * const irda_groups[] = {
2101  "uad",
2102 };
2103 
2104 static const char * const kbc_groups[] = {
2105  "kbca",
2106  "kbcb",
2107  "kbcc",
2108  "kbcd",
2109  "kbce",
2110  "kbcf",
2111 };
2112 
2113 static const char * const mio_groups[] = {
2114  "kbcb",
2115  "kbcd",
2116  "kbcf",
2117 };
2118 
2119 static const char * const mipi_hs_groups[] = {
2120  "uaa",
2121  "uab",
2122 };
2123 
2124 static const char * const nand_groups[] = {
2125  "ata",
2126  "atb",
2127  "atc",
2128  "atd",
2129  "ate",
2130  "gmb",
2131  "gmd",
2132  "kbca",
2133  "kbcb",
2134  "kbcc",
2135  "kbcd",
2136  "kbce",
2137  "kbcf",
2138 };
2139 
2140 static const char * const osc_groups[] = {
2141  "cdev1",
2142  "cdev2",
2143 };
2144 
2145 static const char * const owr_groups[] = {
2146  "kbce",
2147  "owc",
2148  "uac",
2149 };
2150 
2151 static const char * const pcie_groups[] = {
2152  "gpv",
2153  "slxa",
2154  "slxk",
2155 };
2156 
2157 static const char * const plla_out_groups[] = {
2158  "cdev1",
2159 };
2160 
2161 static const char * const pllc_out1_groups[] = {
2162  "csus",
2163 };
2164 
2165 static const char * const pllm_out1_groups[] = {
2166  "cdev1",
2167 };
2168 
2169 static const char * const pllp_out2_groups[] = {
2170  "csus",
2171 };
2172 
2173 static const char * const pllp_out3_groups[] = {
2174  "csus",
2175 };
2176 
2177 static const char * const pllp_out4_groups[] = {
2178  "cdev2",
2179 };
2180 
2181 static const char * const pwm_groups[] = {
2182  "gpu",
2183  "sdb",
2184  "sdc",
2185  "sdd",
2186  "ucb",
2187 };
2188 
2189 static const char * const pwr_intr_groups[] = {
2190  "pmc",
2191 };
2192 
2193 static const char * const pwr_on_groups[] = {
2194  "pmc",
2195 };
2196 
2197 static const char * const rsvd1_groups[] = {
2198  "dta",
2199  "dtb",
2200  "dtc",
2201  "dtd",
2202  "dte",
2203  "gmd",
2204  "gme",
2205 };
2206 
2207 static const char * const rsvd2_groups[] = {
2208  "crtp",
2209  "dap1",
2210  "dap3",
2211  "dap4",
2212  "ddc",
2213  "dtb",
2214  "dtc",
2215  "dte",
2216  "dtf",
2217  "gpu7",
2218  "gpv",
2219  "hdint",
2220  "i2cp",
2221  "owc",
2222  "rm",
2223  "sdio1",
2224  "spdi",
2225  "spdo",
2226  "uac",
2227  "uca",
2228  "uda",
2229 };
2230 
2231 static const char * const rsvd3_groups[] = {
2232  "crtp",
2233  "dap2",
2234  "dap3",
2235  "ddc",
2236  "gpu7",
2237  "gpv",
2238  "hdint",
2239  "i2cp",
2240  "ld17",
2241  "ldc",
2242  "ldi",
2243  "lhp0",
2244  "lhp1",
2245  "lhp2",
2246  "lm1",
2247  "lpp",
2248  "lpw1",
2249  "lvp0",
2250  "lvp1",
2251  "owc",
2252  "pmc",
2253  "rm",
2254  "uac",
2255 };
2256 
2257 static const char * const rsvd4_groups[] = {
2258  "ata",
2259  "ate",
2260  "crtp",
2261  "dap3",
2262  "dap4",
2263  "ddc",
2264  "dta",
2265  "dtc",
2266  "dtd",
2267  "dtf",
2268  "gpu",
2269  "gpu7",
2270  "gpv",
2271  "hdint",
2272  "i2cp",
2273  "kbce",
2274  "lcsn",
2275  "ld0",
2276  "ld1",
2277  "ld2",
2278  "ld3",
2279  "ld4",
2280  "ld5",
2281  "ld6",
2282  "ld7",
2283  "ld8",
2284  "ld9",
2285  "ld10",
2286  "ld11",
2287  "ld12",
2288  "ld13",
2289  "ld14",
2290  "ld15",
2291  "ld16",
2292  "ld17",
2293  "ldc",
2294  "ldi",
2295  "lhp0",
2296  "lhp1",
2297  "lhp2",
2298  "lhs",
2299  "lm0",
2300  "lpp",
2301  "lpw1",
2302  "lsc0",
2303  "lsdi",
2304  "lvp0",
2305  "lvp1",
2306  "lvs",
2307  "owc",
2308  "pmc",
2309  "pta",
2310  "rm",
2311  "spif",
2312  "uac",
2313  "uca",
2314  "ucb",
2315 };
2316 
2317 static const char * const rtck_groups[] = {
2318  "gpu7",
2319 };
2320 
2321 static const char * const sdio1_groups[] = {
2322  "sdio1",
2323 };
2324 
2325 static const char * const sdio2_groups[] = {
2326  "dap1",
2327  "dta",
2328  "dtd",
2329  "kbca",
2330  "kbcb",
2331  "kbcd",
2332  "spdi",
2333  "spdo",
2334 };
2335 
2336 static const char * const sdio3_groups[] = {
2337  "sdb",
2338  "sdc",
2339  "sdd",
2340  "slxa",
2341  "slxc",
2342  "slxd",
2343  "slxk",
2344 };
2345 
2346 static const char * const sdio4_groups[] = {
2347  "atb",
2348  "atc",
2349  "atd",
2350  "gma",
2351  "gme",
2352 };
2353 
2354 static const char * const sflash_groups[] = {
2355  "gmc",
2356  "gmd",
2357 };
2358 
2359 static const char * const spdif_groups[] = {
2360  "slxc",
2361  "slxd",
2362  "spdi",
2363  "spdo",
2364  "uad",
2365 };
2366 
2367 static const char * const spi1_groups[] = {
2368  "dtb",
2369  "dte",
2370  "spia",
2371  "spib",
2372  "spic",
2373  "spid",
2374  "spie",
2375  "spif",
2376  "uda",
2377 };
2378 
2379 static const char * const spi2_groups[] = {
2380  "sdb",
2381  "slxa",
2382  "slxc",
2383  "slxd",
2384  "slxk",
2385  "spia",
2386  "spib",
2387  "spic",
2388  "spid",
2389  "spie",
2390  "spif",
2391  "spig",
2392  "spih",
2393  "uab",
2394 };
2395 
2396 static const char * const spi2_alt_groups[] = {
2397  "spid",
2398  "spie",
2399  "spig",
2400  "spih",
2401 };
2402 
2403 static const char * const spi3_groups[] = {
2404  "gma",
2405  "lcsn",
2406  "lm0",
2407  "lpw0",
2408  "lpw2",
2409  "lsc1",
2410  "lsck",
2411  "lsda",
2412  "lsdi",
2413  "sdc",
2414  "sdd",
2415  "spia",
2416  "spib",
2417  "spic",
2418  "spif",
2419  "spig",
2420  "spih",
2421  "uaa",
2422 };
2423 
2424 static const char * const spi4_groups[] = {
2425  "gmc",
2426  "irrx",
2427  "irtx",
2428  "slxa",
2429  "slxc",
2430  "slxd",
2431  "slxk",
2432  "uad",
2433 };
2434 
2435 static const char * const trace_groups[] = {
2436  "kbcc",
2437  "kbcf",
2438 };
2439 
2440 static const char * const twc_groups[] = {
2441  "dap2",
2442  "sdc",
2443 };
2444 
2445 static const char * const uarta_groups[] = {
2446  "gpu",
2447  "irrx",
2448  "irtx",
2449  "sdb",
2450  "sdd",
2451  "sdio1",
2452  "uaa",
2453  "uab",
2454  "uad",
2455 };
2456 
2457 static const char * const uartb_groups[] = {
2458  "irrx",
2459  "irtx",
2460 };
2461 
2462 static const char * const uartc_groups[] = {
2463  "uca",
2464  "ucb",
2465 };
2466 
2467 static const char * const uartd_groups[] = {
2468  "gmc",
2469  "uda",
2470 };
2471 
2472 static const char * const uarte_groups[] = {
2473  "gma",
2474  "sdio1",
2475 };
2476 
2477 static const char * const ulpi_groups[] = {
2478  "uaa",
2479  "uab",
2480  "uda",
2481 };
2482 
2483 static const char * const vi_groups[] = {
2484  "dta",
2485  "dtb",
2486  "dtc",
2487  "dtd",
2488  "dte",
2489  "dtf",
2490 };
2491 
2492 static const char * const vi_sensor_clk_groups[] = {
2493  "csus",
2494 };
2495 
2496 static const char * const xio_groups[] = {
2497  "ld0",
2498  "ld1",
2499  "ld10",
2500  "ld11",
2501  "ld12",
2502  "ld13",
2503  "ld14",
2504  "ld15",
2505  "ld16",
2506  "ld2",
2507  "ld3",
2508  "ld4",
2509  "ld5",
2510  "ld6",
2511  "ld7",
2512  "ld8",
2513  "ld9",
2514  "lhs",
2515  "lsc0",
2516  "lspi",
2517  "lvs",
2518 };
2519 
2520 #define FUNCTION(fname) \
2521  { \
2522  .name = #fname, \
2523  .groups = fname##_groups, \
2524  .ngroups = ARRAY_SIZE(fname##_groups), \
2525  }
2526 
2527 static const struct tegra_function tegra20_functions[] = {
2528  FUNCTION(ahb_clk),
2529  FUNCTION(apb_clk),
2530  FUNCTION(audio_sync),
2531  FUNCTION(crt),
2532  FUNCTION(dap1),
2533  FUNCTION(dap2),
2534  FUNCTION(dap3),
2535  FUNCTION(dap4),
2536  FUNCTION(dap5),
2537  FUNCTION(displaya),
2538  FUNCTION(displayb),
2539  FUNCTION(emc_test0_dll),
2540  FUNCTION(emc_test1_dll),
2541  FUNCTION(gmi),
2542  FUNCTION(gmi_int),
2543  FUNCTION(hdmi),
2544  FUNCTION(i2cp),
2545  FUNCTION(i2c1),
2546  FUNCTION(i2c2),
2547  FUNCTION(i2c3),
2548  FUNCTION(ide),
2549  FUNCTION(irda),
2550  FUNCTION(kbc),
2551  FUNCTION(mio),
2552  FUNCTION(mipi_hs),
2553  FUNCTION(nand),
2554  FUNCTION(osc),
2555  FUNCTION(owr),
2556  FUNCTION(pcie),
2557  FUNCTION(plla_out),
2558  FUNCTION(pllc_out1),
2559  FUNCTION(pllm_out1),
2560  FUNCTION(pllp_out2),
2561  FUNCTION(pllp_out3),
2562  FUNCTION(pllp_out4),
2563  FUNCTION(pwm),
2564  FUNCTION(pwr_intr),
2565  FUNCTION(pwr_on),
2566  FUNCTION(rsvd1),
2567  FUNCTION(rsvd2),
2568  FUNCTION(rsvd3),
2569  FUNCTION(rsvd4),
2570  FUNCTION(rtck),
2571  FUNCTION(sdio1),
2572  FUNCTION(sdio2),
2573  FUNCTION(sdio3),
2574  FUNCTION(sdio4),
2575  FUNCTION(sflash),
2576  FUNCTION(spdif),
2577  FUNCTION(spi1),
2578  FUNCTION(spi2),
2579  FUNCTION(spi2_alt),
2580  FUNCTION(spi3),
2581  FUNCTION(spi4),
2582  FUNCTION(trace),
2583  FUNCTION(twc),
2584  FUNCTION(uarta),
2585  FUNCTION(uartb),
2586  FUNCTION(uartc),
2587  FUNCTION(uartd),
2588  FUNCTION(uarte),
2589  FUNCTION(ulpi),
2590  FUNCTION(vi),
2591  FUNCTION(vi_sensor_clk),
2592  FUNCTION(xio),
2593 };
2594 
2595 #define TRISTATE_REG_A 0x14
2596 #define PIN_MUX_CTL_REG_A 0x80
2597 #define PULLUPDOWN_REG_A 0xa0
2598 #define PINGROUP_REG_A 0x868
2599 
2600 /* Pin group with mux control, and typically tri-state and pull-up/down too */
2601 #define MUX_PG(pg_name, f0, f1, f2, f3, f_safe, \
2602  tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
2603  { \
2604  .name = #pg_name, \
2605  .pins = pg_name##_pins, \
2606  .npins = ARRAY_SIZE(pg_name##_pins), \
2607  .funcs = { \
2608  TEGRA_MUX_ ## f0, \
2609  TEGRA_MUX_ ## f1, \
2610  TEGRA_MUX_ ## f2, \
2611  TEGRA_MUX_ ## f3, \
2612  }, \
2613  .func_safe = TEGRA_MUX_ ## f_safe, \
2614  .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
2615  .mux_bank = 1, \
2616  .mux_bit = mux_b, \
2617  .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
2618  .pupd_bank = 2, \
2619  .pupd_bit = pupd_b, \
2620  .tri_reg = ((tri_r) - TRISTATE_REG_A), \
2621  .tri_bank = 0, \
2622  .tri_bit = tri_b, \
2623  .einput_reg = -1, \
2624  .odrain_reg = -1, \
2625  .lock_reg = -1, \
2626  .ioreset_reg = -1, \
2627  .drv_reg = -1, \
2628  }
2629 
2630 /* Pin groups with only pull up and pull down control */
2631 #define PULL_PG(pg_name, pupd_r, pupd_b) \
2632  { \
2633  .name = #pg_name, \
2634  .pins = pg_name##_pins, \
2635  .npins = ARRAY_SIZE(pg_name##_pins), \
2636  .mux_reg = -1, \
2637  .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
2638  .pupd_bank = 2, \
2639  .pupd_bit = pupd_b, \
2640  .tri_reg = -1, \
2641  .einput_reg = -1, \
2642  .odrain_reg = -1, \
2643  .lock_reg = -1, \
2644  .ioreset_reg = -1, \
2645  .drv_reg = -1, \
2646  }
2647 
2648 /* Pin groups for drive strength registers (configurable version) */
2649 #define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2650  drvdn_b, drvup_b, \
2651  slwr_b, slwr_w, slwf_b, slwf_w) \
2652  { \
2653  .name = "drive_" #pg_name, \
2654  .pins = drive_##pg_name##_pins, \
2655  .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2656  .mux_reg = -1, \
2657  .pupd_reg = -1, \
2658  .tri_reg = -1, \
2659  .einput_reg = -1, \
2660  .odrain_reg = -1, \
2661  .lock_reg = -1, \
2662  .ioreset_reg = -1, \
2663  .drv_reg = ((r) - PINGROUP_REG_A), \
2664  .drv_bank = 3, \
2665  .hsm_bit = hsm_b, \
2666  .schmitt_bit = schmitt_b, \
2667  .lpmd_bit = lpmd_b, \
2668  .drvdn_bit = drvdn_b, \
2669  .drvdn_width = 5, \
2670  .drvup_bit = drvup_b, \
2671  .drvup_width = 5, \
2672  .slwr_bit = slwr_b, \
2673  .slwr_width = slwr_w, \
2674  .slwf_bit = slwf_b, \
2675  .slwf_width = slwf_w, \
2676  }
2677 
2678 /* Pin groups for drive strength registers (simple version) */
2679 #define DRV_PG(pg_name, r) \
2680  DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
2681 
2682 static const struct tegra_pingroup tegra20_groups[] = {
2683  /* name, f0, f1, f2, f3, f_safe, tri r/b, mux r/b, pupd r/b */
2684  MUX_PG(ata, IDE, NAND, GMI, RSVD4, IDE, 0x14, 0, 0x80, 24, 0xa0, 0),
2685  MUX_PG(atb, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xa0, 2),
2686  MUX_PG(atc, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xa0, 4),
2687  MUX_PG(atd, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xa0, 6),
2688  MUX_PG(ate, IDE, NAND, GMI, RSVD4, IDE, 0x18, 25, 0x80, 12, 0xa0, 8),
2689  MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xa8, 0),
2690  MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xa8, 2),
2691  MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, RSVD2, 0x20, 14, 0x98, 20, 0xa4, 24),
2692  MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xac, 24),
2693  MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xa0, 10),
2694  MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, DAP2, 0x14, 8, 0x88, 22, 0xa0, 12),
2695  MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, DAP3, 0x14, 9, 0x88, 24, 0xa0, 14),
2696  MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, DAP4, 0x14, 10, 0x88, 26, 0xa0, 16),
2697  MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
2698  MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
2699  MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xa0, 20),
2700  MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, RSVD1, 0x14, 13, 0x84, 26, 0xa0, 22),
2701  MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, RSVD1, 0x14, 14, 0x84, 28, 0xa0, 24),
2702  MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xa0, 26),
2703  MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
2704  MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xb0, 20),
2705  MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xb0, 22),
2706  MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xb0, 24),
2707  MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xb0, 26),
2708  MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8c, 0, 0xa8, 24),
2709  MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
2710  MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x20, 11, 0x98, 28, 0xa4, 6),
2711  MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, PCIE, 0x14, 17, 0x8c, 2, 0xa0, 30),
2712  MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, HDMI, 0x1c, 23, 0x84, 4, -1, -1),
2713  MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
2714  MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xa8, 22),
2715  MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xa8, 20),
2716  MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xa4, 8),
2717  MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xa4, 10),
2718  MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xa4, 12),
2719  MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xa4, 14),
2720  MUX_PG(kbce, KBC, NAND, OWR, RSVD4, KBC, 0x14, 26, 0x80, 28, 0xb0, 2),
2721  MUX_PG(kbcf, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xb0, 0),
2722  MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
2723  MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
2724  MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
2725  MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
2726  MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
2727  MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
2728  MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
2729  MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
2730  MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
2731  MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
2732  MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
2733  MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
2734  MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
2735  MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
2736  MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
2737  MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
2738  MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
2739  MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
2740  MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
2741  MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
2742  MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
2743  MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
2744  MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
2745  MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
2746  MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
2747  MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
2748  MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, RSVD3, 0x1c, 25, 0x90, 28, -1, -1),
2749  MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
2750  MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, -1, -1),
2751  MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
2752  MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, -1, -1),
2753  MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
2754  MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 28, 0x90, 20, -1, -1),
2755  MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 29, 0x90, 16, -1, -1),
2756  MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, -1, -1),
2757  MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, DISPLAYA, 0x20, 2, 0x90, 6, -1, -1),
2758  MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, -1, -1),
2759  MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
2760  MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
2761  MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
2762  MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, OWR, 0x14, 31, 0x84, 8, 0xb0, 30),
2763  MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
2764  MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
2765  MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
2766  MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8c, 10, -1, -1),
2767  MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8c, 12, 0xac, 28),
2768  MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8c, 14, 0xac, 30),
2769  MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xb0, 18),
2770  MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xa4, 22),
2771  MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xa4, 26),
2772  MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xa4, 28),
2773  MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xa4, 30),
2774  MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 8, 0x8c, 8, 0xa4, 16),
2775  MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 9, 0x8c, 6, 0xa4, 18),
2776  MUX_PG(spia, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
2777  MUX_PG(spib, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
2778  MUX_PG(spic, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
2779  MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
2780  MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
2781  MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
2782  MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 16, 0x8c, 18, 0xa8, 16),
2783  MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 17, 0x8c, 16, 0xa8, 18),
2784  MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xac, 0),
2785  MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xac, 2),
2786  MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
2787  MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xac, 6),
2788  MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
2789  MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
2790  MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xb0, 16),
2791  /* pg_name, pupd_r/b */
2792  PULL_PG(ck32, 0xb0, 14),
2793  PULL_PG(ddrc, 0xac, 26),
2794  PULL_PG(pmca, 0xb0, 4),
2795  PULL_PG(pmcb, 0xb0, 6),
2796  PULL_PG(pmcc, 0xb0, 8),
2797  PULL_PG(pmcd, 0xb0, 10),
2798  PULL_PG(pmce, 0xb0, 12),
2799  PULL_PG(xm2c, 0xa8, 30),
2800  PULL_PG(xm2d, 0xa8, 28),
2801  PULL_PG(ls, 0xac, 20),
2802  PULL_PG(lc, 0xac, 22),
2803  PULL_PG(ld17_0, 0xac, 12),
2804  PULL_PG(ld19_18, 0xac, 14),
2805  PULL_PG(ld21_20, 0xac, 16),
2806  PULL_PG(ld23_22, 0xac, 18),
2807  /* pg_name, r */
2808  DRV_PG(ao1, 0x868),
2809  DRV_PG(ao2, 0x86c),
2810  DRV_PG(at1, 0x870),
2811  DRV_PG(at2, 0x874),
2812  DRV_PG(cdev1, 0x878),
2813  DRV_PG(cdev2, 0x87c),
2814  DRV_PG(csus, 0x880),
2815  DRV_PG(dap1, 0x884),
2816  DRV_PG(dap2, 0x888),
2817  DRV_PG(dap3, 0x88c),
2818  DRV_PG(dap4, 0x890),
2819  DRV_PG(dbg, 0x894),
2820  DRV_PG(lcd1, 0x898),
2821  DRV_PG(lcd2, 0x89c),
2822  DRV_PG(sdmmc2, 0x8a0),
2823  DRV_PG(sdmmc3, 0x8a4),
2824  DRV_PG(spi, 0x8a8),
2825  DRV_PG(uaa, 0x8ac),
2826  DRV_PG(uab, 0x8b0),
2827  DRV_PG(uart2, 0x8b4),
2828  DRV_PG(uart3, 0x8b8),
2829  DRV_PG(vi1, 0x8bc),
2830  DRV_PG(vi2, 0x8c0),
2831  /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
2832  DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
2833  DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
2834  DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
2835  DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
2836  /* pg_name, r */
2837  DRV_PG(sdio1, 0x8e0),
2838  DRV_PG(crt, 0x8ec),
2839  DRV_PG(ddc, 0x8f0),
2840  DRV_PG(gma, 0x8f4),
2841  DRV_PG(gmb, 0x8f8),
2842  DRV_PG(gmc, 0x8fc),
2843  DRV_PG(gmd, 0x900),
2844  DRV_PG(gme, 0x904),
2845  DRV_PG(owr, 0x908),
2846  DRV_PG(uda, 0x90c),
2847 };
2848 
2849 static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2850  .ngpios = NUM_GPIOS,
2851  .pins = tegra20_pins,
2852  .npins = ARRAY_SIZE(tegra20_pins),
2853  .functions = tegra20_functions,
2854  .nfunctions = ARRAY_SIZE(tegra20_functions),
2855  .groups = tegra20_groups,
2856  .ngroups = ARRAY_SIZE(tegra20_groups),
2857 };
2858 
2859 static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
2860 {
2861  return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2862 }
2863 
2864 static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
2865  { .compatible = "nvidia,tegra20-pinmux", },
2866  { },
2867 };
2868 
2869 static struct platform_driver tegra20_pinctrl_driver = {
2870  .driver = {
2871  .name = "tegra20-pinctrl",
2872  .owner = THIS_MODULE,
2873  .of_match_table = tegra20_pinctrl_of_match,
2874  },
2875  .probe = tegra20_pinctrl_probe,
2876  .remove = __devexit_p(tegra_pinctrl_remove),
2877 };
2878 
2879 static int __init tegra20_pinctrl_init(void)
2880 {
2881  return platform_driver_register(&tegra20_pinctrl_driver);
2882 }
2883 arch_initcall(tegra20_pinctrl_init);
2884 
2885 static void __exit tegra20_pinctrl_exit(void)
2886 {
2887  platform_driver_unregister(&tegra20_pinctrl_driver);
2888 }
2889 module_exit(tegra20_pinctrl_exit);
2890 
2891 MODULE_AUTHOR("Stephen Warren <[email protected]>");
2892 MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
2893 MODULE_LICENSE("GPL v2");
2894 MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
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