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pinmux-sh7723.c
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1 /*
2  * SH7723 Pinmux
3  *
4  * Copyright (C) 2008 Magnus Damm
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License. See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/gpio.h>
14 #include <cpu/sh7723.h>
15 
16 enum {
18 
61 
103 
109 
151 
193 
194 
220 
225 
229 
233 
239 
243 
247 
255 
266 
269 
272 
277 
282 
285 
289 
292 
294 
300 
304 
308 
312 
316 
318 
322 
324 
326 
328 
330 
340 
350 };
351 
352 static pinmux_enum_t pinmux_data[] = {
353  /* PTA GPIO */
362 
363  /* PTB GPIO */
372 
373  /* PTC GPIO */
382 
383  /* PTD GPIO */
392 
393  /* PTE GPIO */
400 
401  /* PTF GPIO */
410 
411  /* PTG GPIO */
418 
419  /* PTH GPIO */
428 
429  /* PTJ GPIO */
436 
437  /* PTK GPIO */
446 
447  /* PTL GPIO */
456 
457  /* PTM GPIO */
466 
467  /* PTN GPIO */
476 
477  /* PTQ GPIO */
482 
483  /* PTR GPIO */
492 
493  /* PTS GPIO */
502 
503  /* PTT GPIO */
510 
511  /* PTU GPIO */
518 
519  /* PTV GPIO */
528 
529  /* PTW GPIO */
538 
539  /* PTX GPIO */
548 
549  /* PTY GPIO */
558 
559  /* PTZ GPIO */
568 
569  /* PTA FN */
586 
587  /* PTB FN */
599 
600  /* PTC FN */
617 
618  /* PTD FN */
635 
636  /* PTE FN */
649 
650  /* PTF FN */
668 
669  /* PTG FN */
680 
681  /* PTG FN */
695 
696  /* PTJ FN */
703 
704  /* PTK FN */
722 
723  /* PTL FN */
740 
741  /* PTM FN */
758 
759  /* PTN FN */
776 
777  /* PTQ FN */
782 
783  /* PTR FN */
793 
794  /* PTS FN */
811 
812  /* PTT FN */
827 
828  /* PTU FN */
844 
845  /* PTV FN */
870 
871  /* PTW FN */
886 
887  /* PTX FN */
899 
900  /* PTY FN */
909 
910  /* PTZ FN */
923 };
924 
925 static struct pinmux_gpio pinmux_gpios[] = {
926  /* PTA */
935 
936  /* PTB */
945 
946  /* PTC */
955 
956  /* PTD */
965 
966  /* PTE */
973 
974  /* PTF */
983 
984  /* PTG */
991 
992  /* PTH */
1001 
1002  /* PTJ */
1009 
1010  /* PTK */
1019 
1020  /* PTL */
1029 
1030  /* PTM */
1039 
1040  /* PTN */
1049 
1050  /* PTQ */
1055 
1056  /* PTR */
1065 
1066  /* PTS */
1075 
1076  /* PTT */
1083 
1084  /* PTU */
1091 
1092  /* PTV */
1101 
1102  /* PTW */
1111 
1112  /* PTX */
1121 
1122  /* PTY */
1131 
1132  /* PTZ */
1141 
1142  /* SCIF0 */
1149 
1150  /* SCIF1 */
1157 
1158  /* SCIF2 */
1165 
1166  /* SCIF3 */
1177 
1178  /* SCIF4 */
1185 
1186  /* SCIF5 */
1193 
1194  /* CEU */
1219 
1220  /* LCDC */
1247  /* Main LCD */
1252  /* Main LCD - RGB Mode */
1256  /* Main LCD - SYS Mode */
1261 
1262  /* IRQ */
1271 
1272  /* AUD */
1279 
1280  /* SDHI0 (PTD) */
1289 
1290  /* SDHI0 (PTS) */
1299 
1300  /* SDHI1 */
1309 
1310  /* SIUA */
1321 
1322  /* SIUB */
1331 
1332  /* IRDA */
1335 
1336  /* VOU */
1357 
1358  /* KEYSC */
1370 
1371  /* MSIOF0 (PTF) */
1381 
1382  /* MSIOF0 (PTT+PTX) */
1392 
1393  /* MSIOF1 */
1403 
1404  /* TSIF */
1409 
1410  /* FLCTL */
1425 
1426  /* DMAC */
1431 
1432  /* ADC */
1438 
1439  /* CPG */
1442 
1443  /* TPU */
1448 
1449  /* BSC */
1479 
1480  /* ATAPI */
1511  };
1512 
1513 static struct pinmux_cfg_reg pinmux_config_regs[] = {
1514  { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1515  PTA7_FN, PTA7_OUT, 0, PTA7_IN,
1516  PTA6_FN, PTA6_OUT, 0, PTA6_IN,
1517  PTA5_FN, PTA5_OUT, 0, PTA5_IN,
1523  },
1524  { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1525  PTB7_FN, PTB7_OUT, 0, PTB7_IN,
1526  PTB6_FN, PTB6_OUT, 0, PTB6_IN,
1527  PTB5_FN, PTB5_OUT, 0, PTB5_IN,
1528  PTB4_FN, PTB4_OUT, 0, PTB4_IN,
1529  PTB3_FN, PTB3_OUT, 0, PTB3_IN,
1532  PTB0_FN, PTB0_OUT, 0, PTB0_IN }
1533  },
1534  { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1535  PTC7_FN, PTC7_OUT, 0, PTC7_IN,
1536  PTC6_FN, PTC6_OUT, 0, PTC6_IN,
1537  PTC5_FN, PTC5_OUT, 0, PTC5_IN,
1538  PTC4_FN, PTC4_OUT, 0, PTC4_IN,
1539  PTC3_FN, PTC3_OUT, 0, PTC3_IN,
1540  PTC2_FN, PTC2_OUT, 0, PTC2_IN,
1541  PTC1_FN, PTC1_OUT, 0, PTC1_IN,
1542  PTC0_FN, PTC0_OUT, 0, PTC0_IN }
1543  },
1544  { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1545  PTD7_FN, PTD7_OUT, 0, PTD7_IN,
1546  PTD6_FN, PTD6_OUT, 0, PTD6_IN,
1547  PTD5_FN, PTD5_OUT, 0, PTD5_IN,
1548  PTD4_FN, PTD4_OUT, 0, PTD4_IN,
1549  PTD3_FN, PTD3_OUT, 0, PTD3_IN,
1550  PTD2_FN, PTD2_OUT, 0, PTD2_IN,
1551  PTD1_FN, PTD1_OUT, 0, PTD1_IN,
1552  PTD0_FN, PTD0_OUT, 0, PTD0_IN }
1553  },
1554  { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1555  0, 0, 0, 0,
1556  0, 0, 0, 0,
1557  PTE5_FN, PTE5_OUT, 0, PTE5_IN,
1558  PTE4_FN, PTE4_OUT, 0, PTE4_IN,
1559  PTE3_FN, PTE3_OUT, 0, PTE3_IN,
1560  PTE2_FN, PTE2_OUT, 0, PTE2_IN,
1561  PTE1_FN, PTE1_OUT, 0, PTE1_IN,
1562  PTE0_FN, PTE0_OUT, 0, PTE0_IN }
1563  },
1564  { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1565  PTF7_FN, PTF7_OUT, 0, PTF7_IN,
1566  PTF6_FN, PTF6_OUT, 0, PTF6_IN,
1567  PTF5_FN, PTF5_OUT, 0, PTF5_IN,
1568  PTF4_FN, PTF4_OUT, 0, PTF4_IN,
1569  PTF3_FN, PTF3_OUT, 0, PTF3_IN,
1570  PTF2_FN, PTF2_OUT, 0, PTF2_IN,
1571  PTF1_FN, PTF1_OUT, 0, PTF1_IN,
1572  PTF0_FN, PTF0_OUT, 0, PTF0_IN }
1573  },
1574  { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1575  0, 0, 0, 0,
1576  0, 0, 0, 0,
1577  PTG5_FN, PTG5_OUT, 0, 0,
1578  PTG4_FN, PTG4_OUT, 0, 0,
1579  PTG3_FN, PTG3_OUT, 0, 0,
1580  PTG2_FN, PTG2_OUT, 0, 0,
1581  PTG1_FN, PTG1_OUT, 0, 0,
1582  PTG0_FN, PTG0_OUT, 0, 0 }
1583  },
1584  { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1585  PTH7_FN, PTH7_OUT, 0, PTH7_IN,
1586  PTH6_FN, PTH6_OUT, 0, PTH6_IN,
1587  PTH5_FN, PTH5_OUT, 0, PTH5_IN,
1588  PTH4_FN, PTH4_OUT, 0, PTH4_IN,
1589  PTH3_FN, PTH3_OUT, 0, PTH3_IN,
1590  PTH2_FN, PTH2_OUT, 0, PTH2_IN,
1591  PTH1_FN, PTH1_OUT, 0, PTH1_IN,
1592  PTH0_FN, PTH0_OUT, 0, PTH0_IN }
1593  },
1594  { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1595  PTJ7_FN, PTJ7_OUT, 0, 0,
1596  0, 0, 0, 0,
1597  PTJ5_FN, PTJ5_OUT, 0, 0,
1598  0, 0, 0, 0,
1599  PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
1600  PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
1601  PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
1602  PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN }
1603  },
1604  { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
1605  PTK7_FN, PTK7_OUT, 0, PTK7_IN,
1606  PTK6_FN, PTK6_OUT, 0, PTK6_IN,
1607  PTK5_FN, PTK5_OUT, 0, PTK5_IN,
1608  PTK4_FN, PTK4_OUT, 0, PTK4_IN,
1609  PTK3_FN, PTK3_OUT, 0, PTK3_IN,
1610  PTK2_FN, PTK2_OUT, 0, PTK2_IN,
1611  PTK1_FN, PTK1_OUT, 0, PTK1_IN,
1612  PTK0_FN, PTK0_OUT, 0, PTK0_IN }
1613  },
1614  { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
1615  PTL7_FN, PTL7_OUT, 0, PTL7_IN,
1616  PTL6_FN, PTL6_OUT, 0, PTL6_IN,
1617  PTL5_FN, PTL5_OUT, 0, PTL5_IN,
1618  PTL4_FN, PTL4_OUT, 0, PTL4_IN,
1619  PTL3_FN, PTL3_OUT, 0, PTL3_IN,
1620  PTL2_FN, PTL2_OUT, 0, PTL2_IN,
1621  PTL1_FN, PTL1_OUT, 0, PTL1_IN,
1622  PTL0_FN, PTL0_OUT, 0, PTL0_IN }
1623  },
1624  { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
1625  PTM7_FN, PTM7_OUT, 0, PTM7_IN,
1626  PTM6_FN, PTM6_OUT, 0, PTM6_IN,
1627  PTM5_FN, PTM5_OUT, 0, PTM5_IN,
1628  PTM4_FN, PTM4_OUT, 0, PTM4_IN,
1629  PTM3_FN, PTM3_OUT, 0, PTM3_IN,
1630  PTM2_FN, PTM2_OUT, 0, PTM2_IN,
1631  PTM1_FN, PTM1_OUT, 0, PTM1_IN,
1632  PTM0_FN, PTM0_OUT, 0, PTM0_IN }
1633  },
1634  { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
1635  PTN7_FN, PTN7_OUT, 0, PTN7_IN,
1636  PTN6_FN, PTN6_OUT, 0, PTN6_IN,
1637  PTN5_FN, PTN5_OUT, 0, PTN5_IN,
1638  PTN4_FN, PTN4_OUT, 0, PTN4_IN,
1639  PTN3_FN, PTN3_OUT, 0, PTN3_IN,
1640  PTN2_FN, PTN2_OUT, 0, PTN2_IN,
1641  PTN1_FN, PTN1_OUT, 0, PTN1_IN,
1642  PTN0_FN, PTN0_OUT, 0, PTN0_IN }
1643  },
1644  { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
1645  0, 0, 0, 0,
1646  0, 0, 0, 0,
1647  0, 0, 0, 0,
1648  0, 0, 0, 0,
1649  PTQ3_FN, 0, 0, PTQ3_IN,
1650  PTQ2_FN, 0, 0, PTQ2_IN,
1651  PTQ1_FN, 0, 0, PTQ1_IN,
1652  PTQ0_FN, 0, 0, PTQ0_IN }
1653  },
1654  { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
1655  PTR7_FN, PTR7_OUT, 0, PTR7_IN,
1656  PTR6_FN, PTR6_OUT, 0, PTR6_IN,
1657  PTR5_FN, PTR5_OUT, 0, PTR5_IN,
1658  PTR4_FN, PTR4_OUT, 0, PTR4_IN,
1659  PTR3_FN, 0, 0, PTR3_IN,
1660  PTR2_FN, 0, PTR2_IN_PU, PTR2_IN,
1661  PTR1_FN, PTR1_OUT, 0, PTR1_IN,
1662  PTR0_FN, PTR0_OUT, 0, PTR0_IN }
1663  },
1664  { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
1665  PTS7_FN, PTS7_OUT, 0, PTS7_IN,
1666  PTS6_FN, PTS6_OUT, 0, PTS6_IN,
1667  PTS5_FN, PTS5_OUT, 0, PTS5_IN,
1668  PTS4_FN, PTS4_OUT, 0, PTS4_IN,
1669  PTS3_FN, PTS3_OUT, 0, PTS3_IN,
1670  PTS2_FN, PTS2_OUT, 0, PTS2_IN,
1671  PTS1_FN, PTS1_OUT, 0, PTS1_IN,
1672  PTS0_FN, PTS0_OUT, 0, PTS0_IN }
1673  },
1674  { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
1675  0, 0, 0, 0,
1676  0, 0, 0, 0,
1677  PTT5_FN, PTT5_OUT, 0, PTT5_IN,
1678  PTT4_FN, PTT4_OUT, 0, PTT4_IN,
1679  PTT3_FN, PTT3_OUT, 0, PTT3_IN,
1680  PTT2_FN, PTT2_OUT, 0, PTT2_IN,
1681  PTT1_FN, PTT1_OUT, 0, PTT1_IN,
1682  PTT0_FN, PTT0_OUT, 0, PTT0_IN }
1683  },
1684  { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
1685  0, 0, 0, 0,
1686  0, 0, 0, 0,
1687  PTU5_FN, PTU5_OUT, 0, PTU5_IN,
1688  PTU4_FN, PTU4_OUT, 0, PTU4_IN,
1689  PTU3_FN, PTU3_OUT, 0, PTU3_IN,
1690  PTU2_FN, PTU2_OUT, 0, PTU2_IN,
1691  PTU1_FN, PTU1_OUT, 0, PTU1_IN,
1692  PTU0_FN, PTU0_OUT, 0, PTU0_IN }
1693  },
1694  { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
1695  PTV7_FN, PTV7_OUT, 0, PTV7_IN,
1696  PTV6_FN, PTV6_OUT, 0, PTV6_IN,
1697  PTV5_FN, PTV5_OUT, 0, PTV5_IN,
1698  PTV4_FN, PTV4_OUT, 0, PTV4_IN,
1699  PTV3_FN, PTV3_OUT, 0, PTV3_IN,
1700  PTV2_FN, PTV2_OUT, 0, PTV2_IN,
1701  PTV1_FN, PTV1_OUT, 0, PTV1_IN,
1702  PTV0_FN, PTV0_OUT, 0, PTV0_IN }
1703  },
1704  { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
1705  PTW7_FN, PTW7_OUT, 0, PTW7_IN,
1706  PTW6_FN, PTW6_OUT, 0, PTW6_IN,
1707  PTW5_FN, PTW5_OUT, 0, PTW5_IN,
1708  PTW4_FN, PTW4_OUT, 0, PTW4_IN,
1709  PTW3_FN, PTW3_OUT, 0, PTW3_IN,
1710  PTW2_FN, PTW2_OUT, 0, PTW2_IN,
1711  PTW1_FN, PTW1_OUT, 0, PTW1_IN,
1712  PTW0_FN, PTW0_OUT, 0, PTW0_IN }
1713  },
1714  { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
1715  PTX7_FN, PTX7_OUT, 0, PTX7_IN,
1716  PTX6_FN, PTX6_OUT, 0, PTX6_IN,
1717  PTX5_FN, PTX5_OUT, 0, PTX5_IN,
1718  PTX4_FN, PTX4_OUT, 0, PTX4_IN,
1719  PTX3_FN, PTX3_OUT, 0, PTX3_IN,
1720  PTX2_FN, PTX2_OUT, 0, PTX2_IN,
1721  PTX1_FN, PTX1_OUT, 0, PTX1_IN,
1722  PTX0_FN, PTX0_OUT, 0, PTX0_IN }
1723  },
1724  { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
1725  PTY7_FN, PTY7_OUT, 0, PTY7_IN,
1726  PTY6_FN, PTY6_OUT, 0, PTY6_IN,
1727  PTY5_FN, PTY5_OUT, 0, PTY5_IN,
1728  PTY4_FN, PTY4_OUT, 0, PTY4_IN,
1729  PTY3_FN, PTY3_OUT, 0, PTY3_IN,
1730  PTY2_FN, PTY2_OUT, 0, PTY2_IN,
1731  PTY1_FN, PTY1_OUT, 0, PTY1_IN,
1732  PTY0_FN, PTY0_OUT, 0, PTY0_IN }
1733  },
1734  { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
1735  PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
1736  PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
1737  PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
1738  PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN,
1739  PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
1740  PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
1741  PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
1742  PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN }
1743  },
1744  { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2) {
1748  0, 0, 0, 0,
1749  0, 0, 0, 0,
1752  0, 0, 0, 0 }
1753  },
1754  { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2) {
1757  0, 0, 0, 0,
1762  0, 0, 0, 0 }
1763  },
1764  { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2) {
1770  0, 0, 0, 0,
1771  0, 0, 0, 0,
1772  0, 0, 0, 0 }
1773  },
1774  { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2) {
1782  PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 }
1783  },
1784  {}
1785 };
1786 
1787 static struct pinmux_data_reg pinmux_data_regs[] = {
1788  { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
1791  },
1792  { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
1795  },
1796  { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
1799  },
1800  { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
1803  },
1804  { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
1805  0, 0, PTE5_DATA, PTE4_DATA,
1807  },
1808  { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
1811  },
1812  { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
1813  0, 0, PTG5_DATA, PTG4_DATA,
1815  },
1816  { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
1819  },
1820  { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
1821  PTJ7_DATA, 0, PTJ5_DATA, 0,
1823  },
1824  { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
1827  },
1828  { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
1831  },
1832  { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
1835  },
1836  { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
1839  },
1840  { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
1841  0, 0, 0, 0,
1843  },
1844  { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
1847  },
1848  { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
1851  },
1852  { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
1853  0, 0, PTT5_DATA, PTT4_DATA,
1855  },
1856  { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
1857  0, 0, PTU5_DATA, PTU4_DATA,
1859  },
1860  { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
1863  },
1864  { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
1867  },
1868  { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
1871  },
1872  { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
1875  },
1876  { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
1879  },
1880  { },
1881 };
1882 
1883 static struct pinmux_info sh7723_pinmux_info = {
1884  .name = "sh7723_pfc",
1885  .reserved_id = PINMUX_RESERVED,
1886  .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1887  .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1889  .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1890  .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1891  .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1892 
1893  .first_gpio = GPIO_PTA7,
1894  .last_gpio = GPIO_FN_IDEA0,
1895 
1896  .gpios = pinmux_gpios,
1897  .cfg_regs = pinmux_config_regs,
1898  .data_regs = pinmux_data_regs,
1899 
1900  .gpio_data = pinmux_data,
1901  .gpio_data_size = ARRAY_SIZE(pinmux_data),
1902 };
1903 
1904 static int __init plat_pinmux_setup(void)
1905 {
1906  return register_pinmux(&sh7723_pinmux_info);
1907 }
1908 
1909 arch_initcall(plat_pinmux_setup);