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drivers
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cxt1e1
pmcc4_private.h
Go to the documentation of this file.
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#ifndef _INC_PMCC4_PRIVATE_H_
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#define _INC_PMCC4_PRIVATE_H_
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/*-----------------------------------------------------------------------------
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* pmcc4_private.h -
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*
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* Copyright (C) 2005 SBE, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <
linux/semaphore.h
>
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#include <
linux/spinlock.h
>
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#include <
linux/interrupt.h
>
/* support for tasklets */
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#include <
linux/timer.h
>
/* support for timer */
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#include <
linux/workqueue.h
>
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#include <linux/hdlc.h>
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#include "
libsbew.h
"
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#include "
pmcc4_defs.h
"
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#include "
pmcc4_cpld.h
"
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#include "
musycc.h
"
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#include "
sbe_promformat.h
"
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#include "
comet.h
"
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/* driver state */
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#define SBE_DRVR_INIT 0x0
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#define SBE_DRVR_AVAILABLE 0x69734F4E
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#define SBE_DRVR_DOWN 0x1
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/******************************************************************************
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* MUSYCC Message Descriptor - coupled to hardware implementation, the first
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* three u_int32 must not be reordered.
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*/
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struct
mdesc
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{
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volatile
u_int32_t
status
;
/* Buffer Descriptor */
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u_int32_t
data
;
/* Data Pointer */
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u_int32_t
next
;
/* MUSYCC view of Next Pointer */
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void
*
mem_token
;
/* Data */
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struct
mdesc
*
snext
;
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};
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/*************************************************************************
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* Private driver data structures, internal use only.
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*/
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struct
c4_chan_info
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{
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int
gchan
;
/* channel number within group/port 0-31 */
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int
channum
;
/* absolute channel number 0-128 */
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u_int8_t
status
;
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#define TX_RECOVERY_MASK 0x0f
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#define TX_ONR_RECOVERY 0x01
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#define TX_BUFF_RECOVERY 0x02
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#define RX_RECOVERY_MASK 0xf0
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#define RX_ONR_RECOVERY 0x10
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unsigned
char
ch_start_rx
;
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#define CH_START_RX_NOW 1
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#define CH_START_RX_ONR 2
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#define CH_START_RX_BUF 3
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unsigned
char
ch_start_tx
;
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#define CH_START_TX_1ST 1
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#define CH_START_TX_ONR 2
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#define CH_START_TX_BUF 3
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char
tx_full
;
/* boolean */
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short
txd_free
;
/* count of TX Desc available */
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short
txd_required
;
/* count of TX Desc needed by mesg */
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unsigned
short
rxd_num
;
/* must support range up to 2000 */
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unsigned
short
txd_num
;
/* must support range up to 1000 */
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int
rxix_irq_srv
;
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enum
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{
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UNASSIGNED
,
/* AVAILABLE, NOTINUSE */
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DOWN
,
/* ASSIGNED, NOTINUSE */
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UP
/* ASSIGNED and INUSE */
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}
state
;
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struct
c4_port_info
*
up
;
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void
*
user
;
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struct
work_struct
ch_work
;
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struct
mdesc
*
mdt
;
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struct
mdesc
*
mdr
;
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struct
mdesc
*
txd_irq_srv
;
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struct
mdesc
*
txd_usr_add
;
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#if 0
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/*
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* FUTURE CODE MIGHT SEPARATE TIMESLOT MAP SETUPS INTO SINGLE IOCTL and
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* REMOVE MAPS FROM CHANNEL PARAMETER STRUCTURE
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*/
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/*
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* each byte in bitmask below represents one timeslot (bitmask[0] is for
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* timeslot 0 and so on), each bit in the byte selects timeslot bits for
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* this channel (0xff - whole timeslot, 0x7f - 56kbps mode)
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*/
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u_int8_t
ts_bitmask[32];
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#endif
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spinlock_t
ch_rxlock
;
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spinlock_t
ch_txlock
;
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atomic_t
tx_pending
;
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struct
sbecom_chan_stats
s
;
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struct
sbecom_chan_param
p
;
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};
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typedef
struct
c4_chan_info
mch_t
;
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struct
c4_port_info
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{
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struct
musycc_globalr
*
reg
;
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struct
musycc_groupr
*
regram
;
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void
*
regram_saved
;
/* Original malloc value may have non-2KB
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* boundary. Need to save for use when
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* freeing. */
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comet_t
*
cometbase
;
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struct
sbe_card_info
*
up
;
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/*
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* The workqueue is used for TX restart of ONR'd channels when in
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* Transparent mode.
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*/
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struct
workqueue_struct
*
wq_port
;
/* chan restart work queue */
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struct
semaphore
sr_sem_busy
;
/* service request exclusion
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* semaphore */
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struct
semaphore
sr_sem_wait
;
/* service request handshake
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* semaphore */
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u_int32_t
sr_last
;
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short
openchans
;
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char
portnum
;
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char
group_is_set
;
/* GROUP_INIT command issued to MUSYCC,
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* otherwise SET_CHAN Ioctl fails */
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mch_t
*
chan
[
MUSYCC_NCHANS
];
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struct
sbecom_port_param
p
;
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/*
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* The MUSYCC timeslot mappings are maintained within the driver and are
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* modified and reloaded as each of a group's channels are configured.
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*/
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u_int8_t
tsm
[32];
/* tsm (time slot map) */
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int
fifomap
[32];
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};
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typedef
struct
c4_port_info
mpi_t
;
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#define COMET_OFFSET(x) (0x80000+(x)*0x10000)
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#define EEPROM_OFFSET 0xC0000
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#define ISPLD_OFFSET 0xD0000
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/* iSPLD control chip registers */
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#define ISPLD_MCSR 0x0
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#define ISPLD_MCLK 0x1
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#define ISPLD_LEDS 0x2
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#define ISPLD_INTR 0x3
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#define ISPLD_MAX 0x3
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struct
sbe_card_info
180
{
181
struct
musycc_globalr
*
reg
;
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struct
musycc_groupr
*
regram
;
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u_int32_t
*
iqd_p
;
/* pointer to dword aligned interrupt queue
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* descriptors */
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void
*
iqd_p_saved
;
/* Original malloc value may have non-dword
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* aligned boundary. Need to save for use
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* when freeing. */
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unsigned
int
iqp_headx
,
iqp_tailx
;
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struct
semaphore
sem_wdbusy
;
/* watchdog exclusion semaphore */
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struct
watchdog
wd
;
/* statically allocated watchdog structure */
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atomic_t
bh_pending
;
/* bh queued, but not yet running */
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u_int32_t
brd_id
;
/* unique PCI ID */
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u_int16_t
hdw_bid
;
/* on/board hardware ID */
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unsigned
short
wdcount
;
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unsigned
char
max_port
;
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unsigned
char
brdno
;
/* our board number */
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unsigned
char
wd_notify
;
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#define WD_NOTIFY_1TX 1
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#define WD_NOTIFY_BUF 2
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#define WD_NOTIFY_ONR 4
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enum
/* state as regards interrupt processing */
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{
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C_INIT
,
/* of-board-address not configured or are in
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* process of being removed, don't access
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* hardware */
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C_IDLE
,
/* off-board-addresses are configured, but
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* don't service interrupts, just clear them
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* from hardware */
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C_RUNNING
/* life is good, service away */
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}
state
;
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struct
sbe_card_info
*
next
;
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u_int32_t
*
eeprombase
;
/* mapped address of board's EEPROM */
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c4cpld_t
*
cpldbase
;
/* mapped address of board's CPLD hardware */
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char
*
release
;
/* SBE ID string w/in sbeRelease.c */
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void
*
hdw_info
;
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#ifdef CONFIG_PROC_FS
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struct
proc_dir_entry
*dir_dev;
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#endif
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/* saved off interface assignments which bound a board */
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hdlc_device
*
first_if
;
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hdlc_device
*
last_if
;
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short
first_channum
,
last_channum
;
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struct
intlog
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{
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u_int32_t
this_status_new
;
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u_int32_t
last_status_new
;
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u_int32_t
drvr_intr_thcount
;
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u_int32_t
drvr_intr_bhcount
;
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u_int32_t
drvr_int_failure
;
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}
intlog
;
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mpi_t
port
[MUSYCC_NPORTS];
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char
devname
[
SBE_IFACETMPL_SIZE
+ 1];
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atomic_t
tx_pending
;
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u_int32_t
alarmed
[4];
/* dpm211 */
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#if defined(SBE_ISR_TASKLET)
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struct
tasklet_struct
ci_musycc_isr_tasklet
;
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#elif defined(SBE_ISR_IMMEDIATE)
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struct
tq_struct ci_musycc_isr_tq;
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#endif
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};
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typedef
struct
sbe_card_info
ci_t
;
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struct
s_hdw_info
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{
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u_int8_t
pci_busno
;
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u_int8_t
pci_slot
;
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u_int8_t
pci_pin
[2];
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u_int8_t
revid
[2];
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u_int8_t
mfg_info_sts
;
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#define EEPROM_OK 0x00
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#define EEPROM_CRCERR 0x01
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char
promfmt
;
/* prom type, from sbe_promformat.h */
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char
devname
[
SBE_IFACETMPL_SIZE
];
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struct
pci_bus
*
bus
;
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struct
net_device
*
ndev
;
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struct
pci_dev
*
pdev
[2];
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unsigned
long
addr
[2];
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unsigned
long
addr_mapped
[2];
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unsigned
long
len
[2];
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union
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{
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char
data
[128];
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FLD_TYPE1
pft1
;
/* prom field, type #1 */
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FLD_TYPE2
pft2
;
/* prom field, type #2 */
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}
mfg_info
;
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};
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typedef
struct
s_hdw_info
hdw_info_t
;
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/*****************************************************************/
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struct
c4_priv
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{
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int
channum
;
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struct
sbe_card_info
*
ci
;
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};
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/*****************************************************************/
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extern
ci_t
*
c4_list
;
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mch_t
*
c4_find_chan
(
int
);
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int
c4_set_chan
(
int
channum,
struct
sbecom_chan_param
*);
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int
c4_get_chan
(
int
channum,
struct
sbecom_chan_param
*);
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int
c4_get_chan_stats
(
int
channum,
struct
sbecom_chan_stats
*);
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#endif
/* _INC_PMCC4_PRIVATE_H_ */
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