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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | musycc_groupr |
| struct | musycc_globalr |
Macros | |
| #define | VINT8 volatile u_int8_t |
| #define | VINT32 volatile u_int32_t |
| #define | PCI_VENDOR_ID_CONEXANT 0x14f1 |
| #define | PCI_DEVICE_ID_CN8471 0x8471 |
| #define | PCI_DEVICE_ID_CN8472 0x8472 |
| #define | PCI_DEVICE_ID_CN8474 0x8474 |
| #define | PCI_DEVICE_ID_CN8478 0x8478 |
| #define | PCI_DEVICE_ID_CN8500 0x8500 |
| #define | PCI_DEVICE_ID_CN8501 0x8501 |
| #define | PCI_DEVICE_ID_CN8502 0x8502 |
| #define | PCI_DEVICE_ID_CN8503 0x8503 |
| #define | INT_QUEUE_SIZE MUSYCC_NIQD |
| #define | MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */ |
| #define | MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */ |
| #define | MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */ |
| #define | MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */ |
| #define | MUSYCC_GCD_BLAPSE |
| #define | MUSYCC_GCD_ALAPSE |
| #define | MUSYCC_GCD_ELAPSE |
| #define | MUSYCC_GCD_PORTMAP_3 3 /* Reserved */ |
| #define | MUSYCC_GCD_PORTMAP_2 |
| #define | MUSYCC_GCD_PORTMAP_1 |
| #define | MUSYCC_GCD_PORTMAP_0 |
| #define | GCD_MAGIC |
| #define | MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */ |
| #define | MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */ |
| #define | MUSYCC_GRCD_SUBCHAN_DISABLE |
| #define | MUSYCC_GRCD_OOFMP_DISABLE |
| #define | MUSYCC_GRCD_OOFIRQ_DISABLE |
| #define | MUSYCC_GRCD_COFAIRQ_DISABLE |
| #define | MUSYCC_GRCD_INHRBSD |
| #define | MUSYCC_GRCD_INHTBSD |
| #define | MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */ |
| #define | MUSYCC_GRCD_MC_ENABLE |
| #define | MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */ |
| #define | MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */ |
| #define | MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */ |
| #define | MUSYCC_GRCD_POLLTH_SHIFT |
| #define | MUSYCC_GRCD_SUERM_THRESH_SHIFT |
| #define | MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */ |
| #define | MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */ |
| #define | MUSYCC_PCD_NX64_MODE 4 |
| #define | MUSYCC_PCD_TXDATA_RISING |
| #define | MUSYCC_PCD_TXSYNC_RISING |
| #define | MUSYCC_PCD_RXDATA_RISING |
| #define | MUSYCC_PCD_RXSYNC_RISING |
| #define | MUSYCC_PCD_ROOF_RISING |
| #define | MUSYCC_PCD_TX_DRIVEN |
| #define | MUSYCC_PCD_PORTMODE_MASK |
| #define | MUSYCC_TSD_MODE_64KBPS 4 |
| #define | MUSYCC_TSD_MODE_56KBPS 5 |
| #define | MUSYCC_TSD_SUBCHANNEL_WO_FIRST 6 |
| #define | MUSYCC_TSD_SUBCHANNEL_WITH_FIRST 7 |
| #define | MUSYCC_MDT_BASE03_ADDR 0x00006000 |
| #define | MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */ |
| #define | MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */ |
| #define | MUSYCC_CCD_MSGIRQ_DISABLE |
| #define | MUSYCC_CCD_IDLEIRQ_DISABLE |
| #define | MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */ |
| #define | MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */ |
| #define | MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */ |
| #define | MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */ |
| #define | MUSYCC_CCD_FCS_XFER |
| #define | MUSYCC_CCD_PROTO_SHIFT |
| #define | MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */ |
| #define | MUSYCC_CCD_SS7 1 |
| #define | MUSYCC_CCD_HDLC_FCS16 2 |
| #define | MUSYCC_CCD_HDLC_FCS32 3 |
| #define | MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */ |
| #define | MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */ |
| #define | MUSYCC_CCD_MAX_LENGTH |
| #define | MUSYCC_CCD_BUFFER_LENGTH |
| #define | MUSYCC_CCD_BUFFER_LOC |
| #define | INT_EMPTY_ENTRY 0xfeedface |
| #define | INT_EMPTY_ENTRY2 0xdeadface |
| #define | INTRPTS_NEXTINT_M 0x7FFF0000 |
| #define | INTRPTS_NEXTINT_S 16 |
| #define | INTRPTS_NEXTINT(x) ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S) |
| #define | INTRPTS_INTFULL_M 0x00008000 |
| #define | INTRPTS_INTFULL_S 15 |
| #define | INTRPTS_INTFULL(x) ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S) |
| #define | INTRPTS_INTCNT_M 0x00007FFF |
| #define | INTRPTS_INTCNT_S 0 |
| #define | INTRPTS_INTCNT(x) ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S) |
| #define | INTRPT_DIR_M 0x80000000 |
| #define | INTRPT_DIR_S 31 |
| #define | INTRPT_DIR(x) ((x & INTRPT_DIR_M) >> INTRPT_DIR_S) |
| #define | INTRPT_GRP_M 0x60000000 |
| #define | INTRPT_GRP_MSB_M 0x00004000 |
| #define | INTRPT_GRP_S 29 |
| #define | INTRPT_GRP_MSB_S 12 |
| #define | INTRPT_GRP(x) |
| #define | INTRPT_CH_M 0x1F000000 |
| #define | INTRPT_CH_S 24 |
| #define | INTRPT_CH(x) ((x & INTRPT_CH_M) >> INTRPT_CH_S) |
| #define | INTRPT_EVENT_M 0x00F00000 |
| #define | INTRPT_EVENT_S 20 |
| #define | INTRPT_EVENT(x) ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S) |
| #define | INTRPT_ERROR_M 0x000F0000 |
| #define | INTRPT_ERROR_S 16 |
| #define | INTRPT_ERROR(x) ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S) |
| #define | INTRPT_ILOST_M 0x00008000 |
| #define | INTRPT_ILOST_S 15 |
| #define | INTRPT_ILOST(x) ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S) |
| #define | INTRPT_PERR_M 0x00004000 |
| #define | INTRPT_PERR_S 14 |
| #define | INTRPT_PERR(x) ((x & INTRPT_PERR_M) >> INTRPT_PERR_S) |
| #define | INTRPT_BLEN_M 0x00003FFF |
| #define | INTRPT_BLEN_S 0 |
| #define | INTRPT_BLEN(x) ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S) |
| #define | OWNER_BIT |
| #define | HOST_TX_OWNED 0x00000000 /* Host owns descriptor */ |
| #define | MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */ |
| #define | HOST_RX_OWNED 0x80000000 /* Host owns descriptor */ |
| #define | MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */ |
| #define | POLL_DISABLED |
| #define | EOMIRQ_ENABLE |
| #define | EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */ |
| #define | PADFILL_ENABLE 0x01000000 /* Enable padfill */ |
| #define | REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */ |
| #define | LENGTH_MASK |
| #define | IDLE_CODE |
| #define | EXTRA_FLAGS |
| #define | IDLE_CODE_MASK |
| #define | EXTRA_FLAGS_MASK |
| #define | PCI_PERMUTED_OWNER_BIT |
| #define | SREQ |
| #define | SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */ |
| #define | SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */ |
| #define | SR_GROUP_RESET (2<<(SREQ)) /* Group reset */ |
| #define | SR_GLOBAL_INIT |
| #define | SR_GROUP_INIT |
| #define | SR_CHANNEL_ACTIVATE |
| #define | SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */ |
| #define | SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */ |
| #define | SR_JUMP |
| #define | SR_CHANNEL_CONFIG |
| #define | SR_GLOBAL_CONFIG |
| #define | SR_INTERRUPT_Q |
| #define | SR_GROUP_CONFIG |
| #define | SR_MEMORY_PROTECT |
| #define | SR_MESSAGE_LENGTH |
| #define | SR_PORT_CONFIG |
| #define | SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */ |
| #define | SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */ |
| #define | SR_CHAN_CONFIG_TABLE |
| #define | SR_TX_DIRECTION |
| #define | SR_RX_DIRECTION 0x00000000 |
| #define | GROUP10 |
| #define | CHANNEL 24 /* Position index for channel bits */ |
| #define | INT_IQD_TX 0x80000000 |
| #define | INT_IQD_GRP 0x60000000 |
| #define | INT_IQD_CHAN 0x1f000000 |
| #define | INT_IQD_EVENT 0x00f00000 |
| #define | INT_IQD_ERROR 0x000f0000 |
| #define | INT_IQD_ILOST 0x00008000 |
| #define | INT_IQD_PERR 0x00004000 |
| #define | INT_IQD_BLEN 0x00003fff |
| #define | EVE_EVENT 20 /* Position index for event bits */ |
| #define | EVE_NONE |
| #define | EVE_SACK 1 /* Service Request acknowledge */ |
| #define | EVE_EOB 2 /* End of Buffer */ |
| #define | EVE_EOM 3 /* End of Message */ |
| #define | EVE_EOP 4 /* End of Padfill */ |
| #define | EVE_CHABT 5 /* Change to Abort Code */ |
| #define | EVE_CHIC 6 /* Change to Idle Code */ |
| #define | EVE_FREC 7 /* Frame Recovery */ |
| #define | EVE_SINC 8 /* MTP2 SUERM Increment */ |
| #define | EVE_SDEC 9 /* MTP2 SUERM Decrement */ |
| #define | EVE_SFILT 10 /* MTP2 SUERM Filtered Message */ |
| #define | ERR_ERRORS 16 /* Position index for error bits */ |
| #define | ERR_BUF 1 /* Buffer Error */ |
| #define | ERR_COFA 2 /* Change of Frame Alignment Error */ |
| #define | ERR_ONR 3 /* Owner Bit Error */ |
| #define | ERR_PROT 4 /* Memory Protection Error */ |
| #define | ERR_OOF 8 /* Out of Frame Error */ |
| #define | ERR_FCS 9 /* FCS Error */ |
| #define | ERR_ALIGN 10 /* Octet Alignment Error */ |
| #define | ERR_ABT 11 /* Abort Termination */ |
| #define | ERR_LNG 12 /* Long Message Error */ |
| #define | ERR_SHT 13 /* Short Message Error */ |
| #define | ERR_SUERR 14 /* SUERM threshold exceeded */ |
| #define | ERR_PERR 15 /* PCI Parity Error */ |
| #define | TRANSMIT_DIRECTION |
| #define | ILOST 0x00008000 /* Interrupt Lost */ |
| #define | GROUPMSB 0x00004000 /* Group number MSB */ |
| #define | SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */ |
| #define | INITIAL_STATUS |
| #define | SUERM_THRESHOLD 0x1f |
| #define EOMIRQ_ENABLE |
| #define ERR_PROT 4 /* Memory Protection Error */ |
| #define EVE_NONE |
| #define EXTRA_FLAGS |
| #define EXTRA_FLAGS_MASK |
| #define GCD_MAGIC |
| #define GROUP10 |
| #define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */ |
| #define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */ |
| #define IDLE_CODE |
| #define IDLE_CODE_MASK |
| #define INITIAL_STATUS |
| #define INT_QUEUE_SIZE MUSYCC_NIQD |
| #define INTRPT_BLEN | ( | x | ) | ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S) |
| #define INTRPT_CH | ( | x | ) | ((x & INTRPT_CH_M) >> INTRPT_CH_S) |
| #define INTRPT_DIR | ( | x | ) | ((x & INTRPT_DIR_M) >> INTRPT_DIR_S) |
| #define INTRPT_ERROR | ( | x | ) | ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S) |
| #define INTRPT_EVENT | ( | x | ) | ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S) |
| #define INTRPT_GRP | ( | x | ) |
| #define INTRPT_ILOST | ( | x | ) | ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S) |
| #define INTRPT_PERR | ( | x | ) | ((x & INTRPT_PERR_M) >> INTRPT_PERR_S) |
| #define INTRPTS_INTCNT | ( | x | ) | ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S) |
| #define INTRPTS_INTFULL | ( | x | ) | ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S) |
| #define INTRPTS_NEXTINT | ( | x | ) | ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S) |
| #define LENGTH_MASK |
| #define MUSYCC_CCD_BUFFER_LENGTH |
| #define MUSYCC_CCD_BUFFER_LOC |
| #define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */ |
| #define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */ |
| #define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */ |
| #define MUSYCC_CCD_FCS_XFER |
| #define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */ |
| #define MUSYCC_CCD_IDLEIRQ_DISABLE |
| #define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */ |
| #define MUSYCC_CCD_MAX_LENGTH |
| #define MUSYCC_CCD_MSGIRQ_DISABLE |
| #define MUSYCC_CCD_PROTO_SHIFT |
| #define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */ |
| #define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */ |
| #define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */ |
| #define MUSYCC_GCD_ALAPSE |
| #define MUSYCC_GCD_BLAPSE |
| #define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */ |
| #define MUSYCC_GCD_ELAPSE |
| #define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */ |
| #define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */ |
| #define MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */ |
| #define MUSYCC_GCD_PORTMAP_0 |
| #define MUSYCC_GCD_PORTMAP_1 |
| #define MUSYCC_GCD_PORTMAP_2 |
| #define MUSYCC_GRCD_COFAIRQ_DISABLE |
| #define MUSYCC_GRCD_INHRBSD |
| #define MUSYCC_GRCD_INHTBSD |
| #define MUSYCC_GRCD_MC_ENABLE |
| #define MUSYCC_GRCD_OOFIRQ_DISABLE |
| #define MUSYCC_GRCD_OOFMP_DISABLE |
| #define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */ |
| #define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */ |
| #define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */ |
| #define MUSYCC_GRCD_POLLTH_SHIFT |
| #define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */ |
| #define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */ |
| #define MUSYCC_GRCD_SUBCHAN_DISABLE |
| #define MUSYCC_GRCD_SUERM_THRESH_SHIFT |
| #define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */ |
| #define MUSYCC_PCD_PORTMODE_MASK |
| #define MUSYCC_PCD_ROOF_RISING |
| #define MUSYCC_PCD_RXDATA_RISING |
| #define MUSYCC_PCD_RXSYNC_RISING |
| #define MUSYCC_PCD_TX_DRIVEN |
| #define MUSYCC_PCD_TXDATA_RISING |
| #define MUSYCC_PCD_TXSYNC_RISING |
| #define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */ |
| #define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */ |
| #define OWNER_BIT |
| #define PCI_PERMUTED_OWNER_BIT |
| #define POLL_DISABLED |
| #define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */ |
| #define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */ |
| #define SR_CHAN_CONFIG_TABLE |
| #define SR_CHANNEL_ACTIVATE |
| #define SR_CHANNEL_CONFIG |
| #define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */ |
| #define SR_GLOBAL_CONFIG |
| #define SR_GLOBAL_INIT |
| #define SR_GROUP_CONFIG |
| #define SR_GROUP_INIT |
| #define SR_INTERRUPT_Q |
| #define SR_JUMP |
| #define SR_MEMORY_PROTECT |
| #define SR_MESSAGE_LENGTH |
| #define SR_PORT_CONFIG |
| #define SR_TX_DIRECTION |
| #define SREQ |
| #define TRANSMIT_DIRECTION |
1.8.2