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ppc-opc.c
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1 /* ppc-opc.c -- PowerPC opcode list
2  Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3  2005 Free Software Foundation, Inc.
4  Written by Ian Lance Taylor, Cygnus Support
5 
6  This file is part of GDB, GAS, and the GNU binutils.
7 
8  GDB, GAS, and the GNU binutils are free software; you can redistribute
9  them and/or modify them under the terms of the GNU General Public
10  License as published by the Free Software Foundation; either version
11  2, or (at your option) any later version.
12 
13  GDB, GAS, and the GNU binutils are distributed in the hope that they
14  will be useful, but WITHOUT ANY WARRANTY; without even the implied
15  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16  the GNU General Public License for more details.
17 
18  You should have received a copy of the GNU General Public License
19  along with this file; see the file COPYING. If not, write to the Free
20  Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21  02110-1301, USA. */
22 
23 #include <linux/stddef.h>
24 #include <linux/kernel.h>
25 #include <linux/bug.h>
26 #include "nonstdio.h"
27 #include "ppc.h"
28 
29 #define ATTRIBUTE_UNUSED
30 #define _(x) x
31 
32 /* This file holds the PowerPC opcode table. The opcode table
33  includes almost all of the extended instruction mnemonics. This
34  permits the disassembler to use them, and simplifies the assembler
35  logic, at the cost of increasing the table size. The table is
36  strictly constant data, so the compiler should be able to put it in
37  the .text section.
38 
39  This file also holds the operand table. All knowledge about
40  inserting operands into instructions and vice-versa is kept in this
41  file. */
42 
43 /* Local insertion and extraction functions. */
44 
45 static unsigned long insert_bat (unsigned long, long, int, const char **);
46 static long extract_bat (unsigned long, int, int *);
47 static unsigned long insert_bba (unsigned long, long, int, const char **);
48 static long extract_bba (unsigned long, int, int *);
49 static unsigned long insert_bd (unsigned long, long, int, const char **);
50 static long extract_bd (unsigned long, int, int *);
51 static unsigned long insert_bdm (unsigned long, long, int, const char **);
52 static long extract_bdm (unsigned long, int, int *);
53 static unsigned long insert_bdp (unsigned long, long, int, const char **);
54 static long extract_bdp (unsigned long, int, int *);
55 static unsigned long insert_bo (unsigned long, long, int, const char **);
56 static long extract_bo (unsigned long, int, int *);
57 static unsigned long insert_boe (unsigned long, long, int, const char **);
58 static long extract_boe (unsigned long, int, int *);
59 static unsigned long insert_dq (unsigned long, long, int, const char **);
60 static long extract_dq (unsigned long, int, int *);
61 static unsigned long insert_ds (unsigned long, long, int, const char **);
62 static long extract_ds (unsigned long, int, int *);
63 static unsigned long insert_de (unsigned long, long, int, const char **);
64 static long extract_de (unsigned long, int, int *);
65 static unsigned long insert_des (unsigned long, long, int, const char **);
66 static long extract_des (unsigned long, int, int *);
67 static unsigned long insert_fxm (unsigned long, long, int, const char **);
68 static long extract_fxm (unsigned long, int, int *);
69 static unsigned long insert_li (unsigned long, long, int, const char **);
70 static long extract_li (unsigned long, int, int *);
71 static unsigned long insert_mbe (unsigned long, long, int, const char **);
72 static long extract_mbe (unsigned long, int, int *);
73 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
74 static long extract_mb6 (unsigned long, int, int *);
75 static unsigned long insert_nb (unsigned long, long, int, const char **);
76 static long extract_nb (unsigned long, int, int *);
77 static unsigned long insert_nsi (unsigned long, long, int, const char **);
78 static long extract_nsi (unsigned long, int, int *);
79 static unsigned long insert_ral (unsigned long, long, int, const char **);
80 static unsigned long insert_ram (unsigned long, long, int, const char **);
81 static unsigned long insert_raq (unsigned long, long, int, const char **);
82 static unsigned long insert_ras (unsigned long, long, int, const char **);
83 static unsigned long insert_rbs (unsigned long, long, int, const char **);
84 static long extract_rbs (unsigned long, int, int *);
85 static unsigned long insert_rsq (unsigned long, long, int, const char **);
86 static unsigned long insert_rtq (unsigned long, long, int, const char **);
87 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
88 static long extract_sh6 (unsigned long, int, int *);
89 static unsigned long insert_spr (unsigned long, long, int, const char **);
90 static long extract_spr (unsigned long, int, int *);
91 static unsigned long insert_sprg (unsigned long, long, int, const char **);
92 static long extract_sprg (unsigned long, int, int *);
93 static unsigned long insert_tbr (unsigned long, long, int, const char **);
94 static long extract_tbr (unsigned long, int, int *);
95 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
96 static long extract_ev2 (unsigned long, int, int *);
97 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
98 static long extract_ev4 (unsigned long, int, int *);
99 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
100 static long extract_ev8 (unsigned long, int, int *);
101 
102 /* The operands table.
103 
104  The fields are bits, shift, insert, extract, flags.
105 
106  We used to put parens around the various additions, like the one
107  for BA just below. However, that caused trouble with feeble
108  compilers with a limit on depth of a parenthesized expression, like
109  (reportedly) the compiler in Microsoft Developer Studio 5. So we
110  omit the parens, since the macros are never used in a context where
111  the addition will be ambiguous. */
112 
113 const struct powerpc_operand powerpc_operands[] =
114 {
115  /* The zero index is used to indicate the end of the list of
116  operands. */
117 #define UNUSED 0
118  { 0, 0, NULL, NULL, 0 },
119 
120  /* The BA field in an XL form instruction. */
121 #define BA UNUSED + 1
122 #define BA_MASK (0x1f << 16)
123  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
124 
125  /* The BA field in an XL form instruction when it must be the same
126  as the BT field in the same instruction. */
127 #define BAT BA + 1
128  { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
129 
130  /* The BB field in an XL form instruction. */
131 #define BB BAT + 1
132 #define BB_MASK (0x1f << 11)
133  { 5, 11, NULL, NULL, PPC_OPERAND_CR },
134 
135  /* The BB field in an XL form instruction when it must be the same
136  as the BA field in the same instruction. */
137 #define BBA BB + 1
138  { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
139 
140  /* The BD field in a B form instruction. The lower two bits are
141  forced to zero. */
142 #define BD BBA + 1
143  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
144 
145  /* The BD field in a B form instruction when absolute addressing is
146  used. */
147 #define BDA BD + 1
148  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
149 
150  /* The BD field in a B form instruction when the - modifier is used.
151  This sets the y bit of the BO field appropriately. */
152 #define BDM BDA + 1
153  { 16, 0, insert_bdm, extract_bdm,
154  PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
155 
156  /* The BD field in a B form instruction when the - modifier is used
157  and absolute address is used. */
158 #define BDMA BDM + 1
159  { 16, 0, insert_bdm, extract_bdm,
160  PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
161 
162  /* The BD field in a B form instruction when the + modifier is used.
163  This sets the y bit of the BO field appropriately. */
164 #define BDP BDMA + 1
165  { 16, 0, insert_bdp, extract_bdp,
166  PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
167 
168  /* The BD field in a B form instruction when the + modifier is used
169  and absolute addressing is used. */
170 #define BDPA BDP + 1
171  { 16, 0, insert_bdp, extract_bdp,
172  PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
173 
174  /* The BF field in an X or XL form instruction. */
175 #define BF BDPA + 1
176  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
177 
178  /* An optional BF field. This is used for comparison instructions,
179  in which an omitted BF field is taken as zero. */
180 #define OBF BF + 1
181  { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
182 
183  /* The BFA field in an X or XL form instruction. */
184 #define BFA OBF + 1
185  { 3, 18, NULL, NULL, PPC_OPERAND_CR },
186 
187  /* The BI field in a B form or XL form instruction. */
188 #define BI BFA + 1
189 #define BI_MASK (0x1f << 16)
190  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
191 
192  /* The BO field in a B form instruction. Certain values are
193  illegal. */
194 #define BO BI + 1
195 #define BO_MASK (0x1f << 21)
196  { 5, 21, insert_bo, extract_bo, 0 },
197 
198  /* The BO field in a B form instruction when the + or - modifier is
199  used. This is like the BO field, but it must be even. */
200 #define BOE BO + 1
201  { 5, 21, insert_boe, extract_boe, 0 },
202 
203 #define BH BOE + 1
204  { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
205 
206  /* The BT field in an X or XL form instruction. */
207 #define BT BH + 1
208  { 5, 21, NULL, NULL, PPC_OPERAND_CR },
209 
210  /* The condition register number portion of the BI field in a B form
211  or XL form instruction. This is used for the extended
212  conditional branch mnemonics, which set the lower two bits of the
213  BI field. This field is optional. */
214 #define CR BT + 1
215  { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
216 
217  /* The CRB field in an X form instruction. */
218 #define CRB CR + 1
219  { 5, 6, NULL, NULL, 0 },
220 
221  /* The CRFD field in an X form instruction. */
222 #define CRFD CRB + 1
223  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
224 
225  /* The CRFS field in an X form instruction. */
226 #define CRFS CRFD + 1
227  { 3, 0, NULL, NULL, PPC_OPERAND_CR },
228 
229  /* The CT field in an X form instruction. */
230 #define CT CRFS + 1
231  { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
232 
233  /* The D field in a D form instruction. This is a displacement off
234  a register, and implies that the next operand is a register in
235  parentheses. */
236 #define D CT + 1
237  { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
238 
239  /* The DE field in a DE form instruction. This is like D, but is 12
240  bits only. */
241 #define DE D + 1
242  { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
243 
244  /* The DES field in a DES form instruction. This is like DS, but is 14
245  bits only (12 stored.) */
246 #define DES DE + 1
247  { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
248 
249  /* The DQ field in a DQ form instruction. This is like D, but the
250  lower four bits are forced to zero. */
251 #define DQ DES + 1
252  { 16, 0, insert_dq, extract_dq,
253  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
254 
255  /* The DS field in a DS form instruction. This is like D, but the
256  lower two bits are forced to zero. */
257 #define DS DQ + 1
258  { 16, 0, insert_ds, extract_ds,
259  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
260 
261  /* The E field in a wrteei instruction. */
262 #define E DS + 1
263  { 1, 15, NULL, NULL, 0 },
264 
265  /* The FL1 field in a POWER SC form instruction. */
266 #define FL1 E + 1
267  { 4, 12, NULL, NULL, 0 },
268 
269  /* The FL2 field in a POWER SC form instruction. */
270 #define FL2 FL1 + 1
271  { 3, 2, NULL, NULL, 0 },
272 
273  /* The FLM field in an XFL form instruction. */
274 #define FLM FL2 + 1
275  { 8, 17, NULL, NULL, 0 },
276 
277  /* The FRA field in an X or A form instruction. */
278 #define FRA FLM + 1
279 #define FRA_MASK (0x1f << 16)
280  { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
281 
282  /* The FRB field in an X or A form instruction. */
283 #define FRB FRA + 1
284 #define FRB_MASK (0x1f << 11)
285  { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
286 
287  /* The FRC field in an A form instruction. */
288 #define FRC FRB + 1
289 #define FRC_MASK (0x1f << 6)
290  { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
291 
292  /* The FRS field in an X form instruction or the FRT field in a D, X
293  or A form instruction. */
294 #define FRS FRC + 1
295 #define FRT FRS
296  { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
297 
298  /* The FXM field in an XFX instruction. */
299 #define FXM FRS + 1
300 #define FXM_MASK (0xff << 12)
301  { 8, 12, insert_fxm, extract_fxm, 0 },
302 
303  /* Power4 version for mfcr. */
304 #define FXM4 FXM + 1
305  { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
306 
307  /* The L field in a D or X form instruction. */
308 #define L FXM4 + 1
309  { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
310 
311  /* The LEV field in a POWER SVC form instruction. */
312 #define SVC_LEV L + 1
313  { 7, 5, NULL, NULL, 0 },
314 
315  /* The LEV field in an SC form instruction. */
316 #define LEV SVC_LEV + 1
317  { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
318 
319  /* The LI field in an I form instruction. The lower two bits are
320  forced to zero. */
321 #define LI LEV + 1
322  { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
323 
324  /* The LI field in an I form instruction when used as an absolute
325  address. */
326 #define LIA LI + 1
327  { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
328 
329  /* The LS field in an X (sync) form instruction. */
330 #define LS LIA + 1
331  { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
332 
333  /* The MB field in an M form instruction. */
334 #define MB LS + 1
335 #define MB_MASK (0x1f << 6)
336  { 5, 6, NULL, NULL, 0 },
337 
338  /* The ME field in an M form instruction. */
339 #define ME MB + 1
340 #define ME_MASK (0x1f << 1)
341  { 5, 1, NULL, NULL, 0 },
342 
343  /* The MB and ME fields in an M form instruction expressed a single
344  operand which is a bitmask indicating which bits to select. This
345  is a two operand form using PPC_OPERAND_NEXT. See the
346  description in opcode/ppc.h for what this means. */
347 #define MBE ME + 1
348  { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
349  { 32, 0, insert_mbe, extract_mbe, 0 },
350 
351  /* The MB or ME field in an MD or MDS form instruction. The high
352  bit is wrapped to the low end. */
353 #define MB6 MBE + 2
354 #define ME6 MB6
355 #define MB6_MASK (0x3f << 5)
356  { 6, 5, insert_mb6, extract_mb6, 0 },
357 
358  /* The MO field in an mbar instruction. */
359 #define MO MB6 + 1
360  { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
361 
362  /* The NB field in an X form instruction. The value 32 is stored as
363  0. */
364 #define NB MO + 1
365  { 6, 11, insert_nb, extract_nb, 0 },
366 
367  /* The NSI field in a D form instruction. This is the same as the
368  SI field, only negated. */
369 #define NSI NB + 1
370  { 16, 0, insert_nsi, extract_nsi,
371  PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
372 
373  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
374 #define RA NSI + 1
375 #define RA_MASK (0x1f << 16)
376  { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
377 
378  /* As above, but 0 in the RA field means zero, not r0. */
379 #define RA0 RA + 1
380  { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
381 
382  /* The RA field in the DQ form lq instruction, which has special
383  value restrictions. */
384 #define RAQ RA0 + 1
385  { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
386 
387  /* The RA field in a D or X form instruction which is an updating
388  load, which means that the RA field may not be zero and may not
389  equal the RT field. */
390 #define RAL RAQ + 1
391  { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
392 
393  /* The RA field in an lmw instruction, which has special value
394  restrictions. */
395 #define RAM RAL + 1
396  { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
397 
398  /* The RA field in a D or X form instruction which is an updating
399  store or an updating floating point load, which means that the RA
400  field may not be zero. */
401 #define RAS RAM + 1
402  { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
403 
404  /* The RA field of the tlbwe instruction, which is optional. */
405 #define RAOPT RAS + 1
406  { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
407 
408  /* The RB field in an X, XO, M, or MDS form instruction. */
409 #define RB RAOPT + 1
410 #define RB_MASK (0x1f << 11)
411  { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
412 
413  /* The RB field in an X form instruction when it must be the same as
414  the RS field in the instruction. This is used for extended
415  mnemonics like mr. */
416 #define RBS RB + 1
417  { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
418 
419  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
420  instruction or the RT field in a D, DS, X, XFX or XO form
421  instruction. */
422 #define RS RBS + 1
423 #define RT RS
424 #define RT_MASK (0x1f << 21)
425  { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
426 
427  /* The RS field of the DS form stq instruction, which has special
428  value restrictions. */
429 #define RSQ RS + 1
430  { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
431 
432  /* The RT field of the DQ form lq instruction, which has special
433  value restrictions. */
434 #define RTQ RSQ + 1
435  { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
436 
437  /* The RS field of the tlbwe instruction, which is optional. */
438 #define RSO RTQ + 1
439 #define RTO RSO
440  { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
441 
442  /* The SH field in an X or M form instruction. */
443 #define SH RSO + 1
444 #define SH_MASK (0x1f << 11)
445  { 5, 11, NULL, NULL, 0 },
446 
447  /* The SH field in an MD form instruction. This is split. */
448 #define SH6 SH + 1
449 #define SH6_MASK ((0x1f << 11) | (1 << 1))
450  { 6, 1, insert_sh6, extract_sh6, 0 },
451 
452  /* The SH field of the tlbwe instruction, which is optional. */
453 #define SHO SH6 + 1
454  { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
455 
456  /* The SI field in a D form instruction. */
457 #define SI SHO + 1
458  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
459 
460  /* The SI field in a D form instruction when we accept a wide range
461  of positive values. */
462 #define SISIGNOPT SI + 1
463  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
464 
465  /* The SPR field in an XFX form instruction. This is flipped--the
466  lower 5 bits are stored in the upper 5 and vice- versa. */
467 #define SPR SISIGNOPT + 1
468 #define PMR SPR
469 #define SPR_MASK (0x3ff << 11)
470  { 10, 11, insert_spr, extract_spr, 0 },
471 
472  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
473 #define SPRBAT SPR + 1
474 #define SPRBAT_MASK (0x3 << 17)
475  { 2, 17, NULL, NULL, 0 },
476 
477  /* The SPRG register number in an XFX form m[ft]sprg instruction. */
478 #define SPRG SPRBAT + 1
479  { 5, 16, insert_sprg, extract_sprg, 0 },
480 
481  /* The SR field in an X form instruction. */
482 #define SR SPRG + 1
483  { 4, 16, NULL, NULL, 0 },
484 
485  /* The STRM field in an X AltiVec form instruction. */
486 #define STRM SR + 1
487 #define STRM_MASK (0x3 << 21)
488  { 2, 21, NULL, NULL, 0 },
489 
490  /* The SV field in a POWER SC form instruction. */
491 #define SV STRM + 1
492  { 14, 2, NULL, NULL, 0 },
493 
494  /* The TBR field in an XFX form instruction. This is like the SPR
495  field, but it is optional. */
496 #define TBR SV + 1
497  { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
498 
499  /* The TO field in a D or X form instruction. */
500 #define TO TBR + 1
501 #define TO_MASK (0x1f << 21)
502  { 5, 21, NULL, NULL, 0 },
503 
504  /* The U field in an X form instruction. */
505 #define U TO + 1
506  { 4, 12, NULL, NULL, 0 },
507 
508  /* The UI field in a D form instruction. */
509 #define UI U + 1
510  { 16, 0, NULL, NULL, 0 },
511 
512  /* The VA field in a VA, VX or VXR form instruction. */
513 #define VA UI + 1
514 #define VA_MASK (0x1f << 16)
515  { 5, 16, NULL, NULL, PPC_OPERAND_VR },
516 
517  /* The VB field in a VA, VX or VXR form instruction. */
518 #define VB VA + 1
519 #define VB_MASK (0x1f << 11)
520  { 5, 11, NULL, NULL, PPC_OPERAND_VR },
521 
522  /* The VC field in a VA form instruction. */
523 #define VC VB + 1
524 #define VC_MASK (0x1f << 6)
525  { 5, 6, NULL, NULL, PPC_OPERAND_VR },
526 
527  /* The VD or VS field in a VA, VX, VXR or X form instruction. */
528 #define VD VC + 1
529 #define VS VD
530 #define VD_MASK (0x1f << 21)
531  { 5, 21, NULL, NULL, PPC_OPERAND_VR },
532 
533  /* The SIMM field in a VX form instruction. */
534 #define SIMM VD + 1
535  { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
536 
537  /* The UIMM field in a VX form instruction. */
538 #define UIMM SIMM + 1
539  { 5, 16, NULL, NULL, 0 },
540 
541  /* The SHB field in a VA form instruction. */
542 #define SHB UIMM + 1
543  { 4, 6, NULL, NULL, 0 },
544 
545  /* The other UIMM field in a EVX form instruction. */
546 #define EVUIMM SHB + 1
547  { 5, 11, NULL, NULL, 0 },
548 
549  /* The other UIMM field in a half word EVX form instruction. */
550 #define EVUIMM_2 EVUIMM + 1
551  { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
552 
553  /* The other UIMM field in a word EVX form instruction. */
554 #define EVUIMM_4 EVUIMM_2 + 1
555  { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
556 
557  /* The other UIMM field in a double EVX form instruction. */
558 #define EVUIMM_8 EVUIMM_4 + 1
559  { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
560 
561  /* The WS field. */
562 #define WS EVUIMM_8 + 1
563 #define WS_MASK (0x7 << 11)
564  { 3, 11, NULL, NULL, 0 },
565 
566  /* The L field in an mtmsrd or A form instruction. */
567 #define MTMSRD_L WS + 1
568 #define A_L MTMSRD_L
569  { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
570 
571  /* The DCM field in a Z form instruction. */
572 #define DCM MTMSRD_L + 1
573  { 6, 16, NULL, NULL, 0 },
574 
575  /* Likewise, the DGM field in a Z form instruction. */
576 #define DGM DCM + 1
577  { 6, 16, NULL, NULL, 0 },
578 
579 #define TE DGM + 1
580  { 5, 11, NULL, NULL, 0 },
581 
582 #define RMC TE + 1
583  { 2, 21, NULL, NULL, 0 },
584 
585 #define R RMC + 1
586  { 1, 15, NULL, NULL, 0 },
587 
588 #define SP R + 1
589  { 2, 11, NULL, NULL, 0 },
590 
591 #define S SP + 1
592  { 1, 11, NULL, NULL, 0 },
593 
594  /* SH field starting at bit position 16. */
595 #define SH16 S + 1
596  { 6, 10, NULL, NULL, 0 },
597 
598  /* The L field in an X form with the RT field fixed instruction. */
599 #define XRT_L SH16 + 1
600  { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
601 
602  /* The EH field in larx instruction. */
603 #define EH XRT_L + 1
604  { 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
605 };
606 
607 /* The functions used to insert and extract complicated operands. */
608 
609 /* The BA field in an XL form instruction when it must be the same as
610  the BT field in the same instruction. This operand is marked FAKE.
611  The insertion function just copies the BT field into the BA field,
612  and the extraction function just checks that the fields are the
613  same. */
614 
615 static unsigned long
616 insert_bat (unsigned long insn,
617  long value ATTRIBUTE_UNUSED,
618  int dialect ATTRIBUTE_UNUSED,
619  const char **errmsg ATTRIBUTE_UNUSED)
620 {
621  return insn | (((insn >> 21) & 0x1f) << 16);
622 }
623 
624 static long
625 extract_bat (unsigned long insn,
626  int dialect ATTRIBUTE_UNUSED,
627  int *invalid)
628 {
629  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
630  *invalid = 1;
631  return 0;
632 }
633 
634 /* The BB field in an XL form instruction when it must be the same as
635  the BA field in the same instruction. This operand is marked FAKE.
636  The insertion function just copies the BA field into the BB field,
637  and the extraction function just checks that the fields are the
638  same. */
639 
640 static unsigned long
641 insert_bba (unsigned long insn,
642  long value ATTRIBUTE_UNUSED,
643  int dialect ATTRIBUTE_UNUSED,
644  const char **errmsg ATTRIBUTE_UNUSED)
645 {
646  return insn | (((insn >> 16) & 0x1f) << 11);
647 }
648 
649 static long
650 extract_bba (unsigned long insn,
651  int dialect ATTRIBUTE_UNUSED,
652  int *invalid)
653 {
654  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
655  *invalid = 1;
656  return 0;
657 }
658 
659 /* The BD field in a B form instruction. The lower two bits are
660  forced to zero. */
661 
662 static unsigned long
663 insert_bd (unsigned long insn,
664  long value,
665  int dialect ATTRIBUTE_UNUSED,
666  const char **errmsg ATTRIBUTE_UNUSED)
667 {
668  return insn | (value & 0xfffc);
669 }
670 
671 static long
672 extract_bd (unsigned long insn,
673  int dialect ATTRIBUTE_UNUSED,
674  int *invalid ATTRIBUTE_UNUSED)
675 {
676  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
677 }
678 
679 /* The BD field in a B form instruction when the - modifier is used.
680  This modifier means that the branch is not expected to be taken.
681  For chips built to versions of the architecture prior to version 2
682  (ie. not Power4 compatible), we set the y bit of the BO field to 1
683  if the offset is negative. When extracting, we require that the y
684  bit be 1 and that the offset be positive, since if the y bit is 0
685  we just want to print the normal form of the instruction.
686  Power4 compatible targets use two bits, "a", and "t", instead of
687  the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
688  "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
689  in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
690  for branch on CTR. We only handle the taken/not-taken hint here. */
691 
692 static unsigned long
693 insert_bdm (unsigned long insn,
694  long value,
695  int dialect,
696  const char **errmsg ATTRIBUTE_UNUSED)
697 {
698  if ((dialect & PPC_OPCODE_POWER4) == 0)
699  {
700  if ((value & 0x8000) != 0)
701  insn |= 1 << 21;
702  }
703  else
704  {
705  if ((insn & (0x14 << 21)) == (0x04 << 21))
706  insn |= 0x02 << 21;
707  else if ((insn & (0x14 << 21)) == (0x10 << 21))
708  insn |= 0x08 << 21;
709  }
710  return insn | (value & 0xfffc);
711 }
712 
713 static long
714 extract_bdm (unsigned long insn,
715  int dialect,
716  int *invalid)
717 {
718  if ((dialect & PPC_OPCODE_POWER4) == 0)
719  {
720  if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
721  *invalid = 1;
722  }
723  else
724  {
725  if ((insn & (0x17 << 21)) != (0x06 << 21)
726  && (insn & (0x1d << 21)) != (0x18 << 21))
727  *invalid = 1;
728  }
729 
730  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
731 }
732 
733 /* The BD field in a B form instruction when the + modifier is used.
734  This is like BDM, above, except that the branch is expected to be
735  taken. */
736 
737 static unsigned long
738 insert_bdp (unsigned long insn,
739  long value,
740  int dialect,
741  const char **errmsg ATTRIBUTE_UNUSED)
742 {
743  if ((dialect & PPC_OPCODE_POWER4) == 0)
744  {
745  if ((value & 0x8000) == 0)
746  insn |= 1 << 21;
747  }
748  else
749  {
750  if ((insn & (0x14 << 21)) == (0x04 << 21))
751  insn |= 0x03 << 21;
752  else if ((insn & (0x14 << 21)) == (0x10 << 21))
753  insn |= 0x09 << 21;
754  }
755  return insn | (value & 0xfffc);
756 }
757 
758 static long
759 extract_bdp (unsigned long insn,
760  int dialect,
761  int *invalid)
762 {
763  if ((dialect & PPC_OPCODE_POWER4) == 0)
764  {
765  if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
766  *invalid = 1;
767  }
768  else
769  {
770  if ((insn & (0x17 << 21)) != (0x07 << 21)
771  && (insn & (0x1d << 21)) != (0x19 << 21))
772  *invalid = 1;
773  }
774 
775  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
776 }
777 
778 /* Check for legal values of a BO field. */
779 
780 static int
781 valid_bo (long value, int dialect)
782 {
783  if ((dialect & PPC_OPCODE_POWER4) == 0)
784  {
785  /* Certain encodings have bits that are required to be zero.
786  These are (z must be zero, y may be anything):
787  001zy
788  011zy
789  1z00y
790  1z01y
791  1z1zz
792  */
793  switch (value & 0x14)
794  {
795  default:
796  case 0:
797  return 1;
798  case 0x4:
799  return (value & 0x2) == 0;
800  case 0x10:
801  return (value & 0x8) == 0;
802  case 0x14:
803  return value == 0x14;
804  }
805  }
806  else
807  {
808  /* Certain encodings have bits that are required to be zero.
809  These are (z must be zero, a & t may be anything):
810  0000z
811  0001z
812  0100z
813  0101z
814  001at
815  011at
816  1a00t
817  1a01t
818  1z1zz
819  */
820  if ((value & 0x14) == 0)
821  return (value & 0x1) == 0;
822  else if ((value & 0x14) == 0x14)
823  return value == 0x14;
824  else
825  return 1;
826  }
827 }
828 
829 /* The BO field in a B form instruction. Warn about attempts to set
830  the field to an illegal value. */
831 
832 static unsigned long
833 insert_bo (unsigned long insn,
834  long value,
835  int dialect,
836  const char **errmsg)
837 {
838  if (!valid_bo (value, dialect))
839  *errmsg = _("invalid conditional option");
840  return insn | ((value & 0x1f) << 21);
841 }
842 
843 static long
844 extract_bo (unsigned long insn,
845  int dialect,
846  int *invalid)
847 {
848  long value;
849 
850  value = (insn >> 21) & 0x1f;
851  if (!valid_bo (value, dialect))
852  *invalid = 1;
853  return value;
854 }
855 
856 /* The BO field in a B form instruction when the + or - modifier is
857  used. This is like the BO field, but it must be even. When
858  extracting it, we force it to be even. */
859 
860 static unsigned long
861 insert_boe (unsigned long insn,
862  long value,
863  int dialect,
864  const char **errmsg)
865 {
866  if (!valid_bo (value, dialect))
867  *errmsg = _("invalid conditional option");
868  else if ((value & 1) != 0)
869  *errmsg = _("attempt to set y bit when using + or - modifier");
870 
871  return insn | ((value & 0x1f) << 21);
872 }
873 
874 static long
875 extract_boe (unsigned long insn,
876  int dialect,
877  int *invalid)
878 {
879  long value;
880 
881  value = (insn >> 21) & 0x1f;
882  if (!valid_bo (value, dialect))
883  *invalid = 1;
884  return value & 0x1e;
885 }
886 
887 /* The DQ field in a DQ form instruction. This is like D, but the
888  lower four bits are forced to zero. */
889 
890 static unsigned long
891 insert_dq (unsigned long insn,
892  long value,
893  int dialect ATTRIBUTE_UNUSED,
894  const char **errmsg)
895 {
896  if ((value & 0xf) != 0)
897  *errmsg = _("offset not a multiple of 16");
898  return insn | (value & 0xfff0);
899 }
900 
901 static long
902 extract_dq (unsigned long insn,
903  int dialect ATTRIBUTE_UNUSED,
904  int *invalid ATTRIBUTE_UNUSED)
905 {
906  return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
907 }
908 
909 static unsigned long
910 insert_ev2 (unsigned long insn,
911  long value,
912  int dialect ATTRIBUTE_UNUSED,
913  const char **errmsg)
914 {
915  if ((value & 1) != 0)
916  *errmsg = _("offset not a multiple of 2");
917  if ((value > 62) != 0)
918  *errmsg = _("offset greater than 62");
919  return insn | ((value & 0x3e) << 10);
920 }
921 
922 static long
923 extract_ev2 (unsigned long insn,
924  int dialect ATTRIBUTE_UNUSED,
925  int *invalid ATTRIBUTE_UNUSED)
926 {
927  return (insn >> 10) & 0x3e;
928 }
929 
930 static unsigned long
931 insert_ev4 (unsigned long insn,
932  long value,
933  int dialect ATTRIBUTE_UNUSED,
934  const char **errmsg)
935 {
936  if ((value & 3) != 0)
937  *errmsg = _("offset not a multiple of 4");
938  if ((value > 124) != 0)
939  *errmsg = _("offset greater than 124");
940  return insn | ((value & 0x7c) << 9);
941 }
942 
943 static long
944 extract_ev4 (unsigned long insn,
945  int dialect ATTRIBUTE_UNUSED,
946  int *invalid ATTRIBUTE_UNUSED)
947 {
948  return (insn >> 9) & 0x7c;
949 }
950 
951 static unsigned long
952 insert_ev8 (unsigned long insn,
953  long value,
954  int dialect ATTRIBUTE_UNUSED,
955  const char **errmsg)
956 {
957  if ((value & 7) != 0)
958  *errmsg = _("offset not a multiple of 8");
959  if ((value > 248) != 0)
960  *errmsg = _("offset greater than 248");
961  return insn | ((value & 0xf8) << 8);
962 }
963 
964 static long
965 extract_ev8 (unsigned long insn,
966  int dialect ATTRIBUTE_UNUSED,
967  int *invalid ATTRIBUTE_UNUSED)
968 {
969  return (insn >> 8) & 0xf8;
970 }
971 
972 /* The DS field in a DS form instruction. This is like D, but the
973  lower two bits are forced to zero. */
974 
975 static unsigned long
976 insert_ds (unsigned long insn,
977  long value,
978  int dialect ATTRIBUTE_UNUSED,
979  const char **errmsg)
980 {
981  if ((value & 3) != 0)
982  *errmsg = _("offset not a multiple of 4");
983  return insn | (value & 0xfffc);
984 }
985 
986 static long
987 extract_ds (unsigned long insn,
988  int dialect ATTRIBUTE_UNUSED,
989  int *invalid ATTRIBUTE_UNUSED)
990 {
991  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
992 }
993 
994 /* The DE field in a DE form instruction. */
995 
996 static unsigned long
997 insert_de (unsigned long insn,
998  long value,
999  int dialect ATTRIBUTE_UNUSED,
1000  const char **errmsg)
1001 {
1002  if (value > 2047 || value < -2048)
1003  *errmsg = _("offset not between -2048 and 2047");
1004  return insn | ((value << 4) & 0xfff0);
1005 }
1006 
1007 static long
1008 extract_de (unsigned long insn,
1009  int dialect ATTRIBUTE_UNUSED,
1010  int *invalid ATTRIBUTE_UNUSED)
1011 {
1012  return (insn & 0xfff0) >> 4;
1013 }
1014 
1015 /* The DES field in a DES form instruction. */
1016 
1017 static unsigned long
1018 insert_des (unsigned long insn,
1019  long value,
1020  int dialect ATTRIBUTE_UNUSED,
1021  const char **errmsg)
1022 {
1023  if (value > 8191 || value < -8192)
1024  *errmsg = _("offset not between -8192 and 8191");
1025  else if ((value & 3) != 0)
1026  *errmsg = _("offset not a multiple of 4");
1027  return insn | ((value << 2) & 0xfff0);
1028 }
1029 
1030 static long
1031 extract_des (unsigned long insn,
1032  int dialect ATTRIBUTE_UNUSED,
1033  int *invalid ATTRIBUTE_UNUSED)
1034 {
1035  return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
1036 }
1037 
1038 /* FXM mask in mfcr and mtcrf instructions. */
1039 
1040 static unsigned long
1041 insert_fxm (unsigned long insn,
1042  long value,
1043  int dialect,
1044  const char **errmsg)
1045 {
1046  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1047  one bit of the mask field is set. */
1048  if ((insn & (1 << 20)) != 0)
1049  {
1050  if (value == 0 || (value & -value) != value)
1051  {
1052  *errmsg = _("invalid mask field");
1053  value = 0;
1054  }
1055  }
1056 
1057  /* If the optional field on mfcr is missing that means we want to use
1058  the old form of the instruction that moves the whole cr. In that
1059  case we'll have VALUE zero. There doesn't seem to be a way to
1060  distinguish this from the case where someone writes mfcr %r3,0. */
1061  else if (value == 0)
1062  ;
1063 
1064  /* If only one bit of the FXM field is set, we can use the new form
1065  of the instruction, which is faster. Unlike the Power4 branch hint
1066  encoding, this is not backward compatible. Do not generate the
1067  new form unless -mpower4 has been given, or -many and the two
1068  operand form of mfcr was used. */
1069  else if ((value & -value) == value
1070  && ((dialect & PPC_OPCODE_POWER4) != 0
1071  || ((dialect & PPC_OPCODE_ANY) != 0
1072  && (insn & (0x3ff << 1)) == 19 << 1)))
1073  insn |= 1 << 20;
1074 
1075  /* Any other value on mfcr is an error. */
1076  else if ((insn & (0x3ff << 1)) == 19 << 1)
1077  {
1078  *errmsg = _("ignoring invalid mfcr mask");
1079  value = 0;
1080  }
1081 
1082  return insn | ((value & 0xff) << 12);
1083 }
1084 
1085 static long
1086 extract_fxm (unsigned long insn,
1087  int dialect ATTRIBUTE_UNUSED,
1088  int *invalid)
1089 {
1090  long mask = (insn >> 12) & 0xff;
1091 
1092  /* Is this a Power4 insn? */
1093  if ((insn & (1 << 20)) != 0)
1094  {
1095  /* Exactly one bit of MASK should be set. */
1096  if (mask == 0 || (mask & -mask) != mask)
1097  *invalid = 1;
1098  }
1099 
1100  /* Check that non-power4 form of mfcr has a zero MASK. */
1101  else if ((insn & (0x3ff << 1)) == 19 << 1)
1102  {
1103  if (mask != 0)
1104  *invalid = 1;
1105  }
1106 
1107  return mask;
1108 }
1109 
1110 /* The LI field in an I form instruction. The lower two bits are
1111  forced to zero. */
1112 
1113 static unsigned long
1114 insert_li (unsigned long insn,
1115  long value,
1116  int dialect ATTRIBUTE_UNUSED,
1117  const char **errmsg)
1118 {
1119  if ((value & 3) != 0)
1120  *errmsg = _("ignoring least significant bits in branch offset");
1121  return insn | (value & 0x3fffffc);
1122 }
1123 
1124 static long
1125 extract_li (unsigned long insn,
1126  int dialect ATTRIBUTE_UNUSED,
1127  int *invalid ATTRIBUTE_UNUSED)
1128 {
1129  return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1130 }
1131 
1132 /* The MB and ME fields in an M form instruction expressed as a single
1133  operand which is itself a bitmask. The extraction function always
1134  marks it as invalid, since we never want to recognize an
1135  instruction which uses a field of this type. */
1136 
1137 static unsigned long
1138 insert_mbe (unsigned long insn,
1139  long value,
1140  int dialect ATTRIBUTE_UNUSED,
1141  const char **errmsg)
1142 {
1143  unsigned long uval, mask;
1144  int mb, me, mx, count, last;
1145 
1146  uval = value;
1147 
1148  if (uval == 0)
1149  {
1150  *errmsg = _("illegal bitmask");
1151  return insn;
1152  }
1153 
1154  mb = 0;
1155  me = 32;
1156  if ((uval & 1) != 0)
1157  last = 1;
1158  else
1159  last = 0;
1160  count = 0;
1161 
1162  /* mb: location of last 0->1 transition */
1163  /* me: location of last 1->0 transition */
1164  /* count: # transitions */
1165 
1166  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1167  {
1168  if ((uval & mask) && !last)
1169  {
1170  ++count;
1171  mb = mx;
1172  last = 1;
1173  }
1174  else if (!(uval & mask) && last)
1175  {
1176  ++count;
1177  me = mx;
1178  last = 0;
1179  }
1180  }
1181  if (me == 0)
1182  me = 32;
1183 
1184  if (count != 2 && (count != 0 || ! last))
1185  *errmsg = _("illegal bitmask");
1186 
1187  return insn | (mb << 6) | ((me - 1) << 1);
1188 }
1189 
1190 static long
1191 extract_mbe (unsigned long insn,
1192  int dialect ATTRIBUTE_UNUSED,
1193  int *invalid)
1194 {
1195  long ret;
1196  int mb, me;
1197  int i;
1198 
1199  *invalid = 1;
1200 
1201  mb = (insn >> 6) & 0x1f;
1202  me = (insn >> 1) & 0x1f;
1203  if (mb < me + 1)
1204  {
1205  ret = 0;
1206  for (i = mb; i <= me; i++)
1207  ret |= 1L << (31 - i);
1208  }
1209  else if (mb == me + 1)
1210  ret = ~0;
1211  else /* (mb > me + 1) */
1212  {
1213  ret = ~0;
1214  for (i = me + 1; i < mb; i++)
1215  ret &= ~(1L << (31 - i));
1216  }
1217  return ret;
1218 }
1219 
1220 /* The MB or ME field in an MD or MDS form instruction. The high bit
1221  is wrapped to the low end. */
1222 
1223 static unsigned long
1224 insert_mb6 (unsigned long insn,
1225  long value,
1226  int dialect ATTRIBUTE_UNUSED,
1227  const char **errmsg ATTRIBUTE_UNUSED)
1228 {
1229  return insn | ((value & 0x1f) << 6) | (value & 0x20);
1230 }
1231 
1232 static long
1233 extract_mb6 (unsigned long insn,
1234  int dialect ATTRIBUTE_UNUSED,
1235  int *invalid ATTRIBUTE_UNUSED)
1236 {
1237  return ((insn >> 6) & 0x1f) | (insn & 0x20);
1238 }
1239 
1240 /* The NB field in an X form instruction. The value 32 is stored as
1241  0. */
1242 
1243 static unsigned long
1244 insert_nb (unsigned long insn,
1245  long value,
1246  int dialect ATTRIBUTE_UNUSED,
1247  const char **errmsg)
1248 {
1249  if (value < 0 || value > 32)
1250  *errmsg = _("value out of range");
1251  if (value == 32)
1252  value = 0;
1253  return insn | ((value & 0x1f) << 11);
1254 }
1255 
1256 static long
1257 extract_nb (unsigned long insn,
1258  int dialect ATTRIBUTE_UNUSED,
1259  int *invalid ATTRIBUTE_UNUSED)
1260 {
1261  long ret;
1262 
1263  ret = (insn >> 11) & 0x1f;
1264  if (ret == 0)
1265  ret = 32;
1266  return ret;
1267 }
1268 
1269 /* The NSI field in a D form instruction. This is the same as the SI
1270  field, only negated. The extraction function always marks it as
1271  invalid, since we never want to recognize an instruction which uses
1272  a field of this type. */
1273 
1274 static unsigned long
1275 insert_nsi (unsigned long insn,
1276  long value,
1277  int dialect ATTRIBUTE_UNUSED,
1278  const char **errmsg ATTRIBUTE_UNUSED)
1279 {
1280  return insn | (-value & 0xffff);
1281 }
1282 
1283 static long
1284 extract_nsi (unsigned long insn,
1285  int dialect ATTRIBUTE_UNUSED,
1286  int *invalid)
1287 {
1288  *invalid = 1;
1289  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1290 }
1291 
1292 /* The RA field in a D or X form instruction which is an updating
1293  load, which means that the RA field may not be zero and may not
1294  equal the RT field. */
1295 
1296 static unsigned long
1297 insert_ral (unsigned long insn,
1298  long value,
1299  int dialect ATTRIBUTE_UNUSED,
1300  const char **errmsg)
1301 {
1302  if (value == 0
1303  || (unsigned long) value == ((insn >> 21) & 0x1f))
1304  *errmsg = "invalid register operand when updating";
1305  return insn | ((value & 0x1f) << 16);
1306 }
1307 
1308 /* The RA field in an lmw instruction, which has special value
1309  restrictions. */
1310 
1311 static unsigned long
1312 insert_ram (unsigned long insn,
1313  long value,
1314  int dialect ATTRIBUTE_UNUSED,
1315  const char **errmsg)
1316 {
1317  if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1318  *errmsg = _("index register in load range");
1319  return insn | ((value & 0x1f) << 16);
1320 }
1321 
1322 /* The RA field in the DQ form lq instruction, which has special
1323  value restrictions. */
1324 
1325 static unsigned long
1326 insert_raq (unsigned long insn,
1327  long value,
1328  int dialect ATTRIBUTE_UNUSED,
1329  const char **errmsg)
1330 {
1331  long rtvalue = (insn & RT_MASK) >> 21;
1332 
1333  if (value == rtvalue)
1334  *errmsg = _("source and target register operands must be different");
1335  return insn | ((value & 0x1f) << 16);
1336 }
1337 
1338 /* The RA field in a D or X form instruction which is an updating
1339  store or an updating floating point load, which means that the RA
1340  field may not be zero. */
1341 
1342 static unsigned long
1343 insert_ras (unsigned long insn,
1344  long value,
1345  int dialect ATTRIBUTE_UNUSED,
1346  const char **errmsg)
1347 {
1348  if (value == 0)
1349  *errmsg = _("invalid register operand when updating");
1350  return insn | ((value & 0x1f) << 16);
1351 }
1352 
1353 /* The RB field in an X form instruction when it must be the same as
1354  the RS field in the instruction. This is used for extended
1355  mnemonics like mr. This operand is marked FAKE. The insertion
1356  function just copies the BT field into the BA field, and the
1357  extraction function just checks that the fields are the same. */
1358 
1359 static unsigned long
1360 insert_rbs (unsigned long insn,
1361  long value ATTRIBUTE_UNUSED,
1362  int dialect ATTRIBUTE_UNUSED,
1363  const char **errmsg ATTRIBUTE_UNUSED)
1364 {
1365  return insn | (((insn >> 21) & 0x1f) << 11);
1366 }
1367 
1368 static long
1369 extract_rbs (unsigned long insn,
1370  int dialect ATTRIBUTE_UNUSED,
1371  int *invalid)
1372 {
1373  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1374  *invalid = 1;
1375  return 0;
1376 }
1377 
1378 /* The RT field of the DQ form lq instruction, which has special
1379  value restrictions. */
1380 
1381 static unsigned long
1382 insert_rtq (unsigned long insn,
1383  long value,
1384  int dialect ATTRIBUTE_UNUSED,
1385  const char **errmsg)
1386 {
1387  if ((value & 1) != 0)
1388  *errmsg = _("target register operand must be even");
1389  return insn | ((value & 0x1f) << 21);
1390 }
1391 
1392 /* The RS field of the DS form stq instruction, which has special
1393  value restrictions. */
1394 
1395 static unsigned long
1396 insert_rsq (unsigned long insn,
1397  long value ATTRIBUTE_UNUSED,
1398  int dialect ATTRIBUTE_UNUSED,
1399  const char **errmsg)
1400 {
1401  if ((value & 1) != 0)
1402  *errmsg = _("source register operand must be even");
1403  return insn | ((value & 0x1f) << 21);
1404 }
1405 
1406 /* The SH field in an MD form instruction. This is split. */
1407 
1408 static unsigned long
1409 insert_sh6 (unsigned long insn,
1410  long value,
1411  int dialect ATTRIBUTE_UNUSED,
1412  const char **errmsg ATTRIBUTE_UNUSED)
1413 {
1414  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1415 }
1416 
1417 static long
1418 extract_sh6 (unsigned long insn,
1419  int dialect ATTRIBUTE_UNUSED,
1420  int *invalid ATTRIBUTE_UNUSED)
1421 {
1422  return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1423 }
1424 
1425 /* The SPR field in an XFX form instruction. This is flipped--the
1426  lower 5 bits are stored in the upper 5 and vice- versa. */
1427 
1428 static unsigned long
1429 insert_spr (unsigned long insn,
1430  long value,
1431  int dialect ATTRIBUTE_UNUSED,
1432  const char **errmsg ATTRIBUTE_UNUSED)
1433 {
1434  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1435 }
1436 
1437 static long
1438 extract_spr (unsigned long insn,
1439  int dialect ATTRIBUTE_UNUSED,
1440  int *invalid ATTRIBUTE_UNUSED)
1441 {
1442  return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1443 }
1444 
1445 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1446 
1447 static unsigned long
1448 insert_sprg (unsigned long insn,
1449  long value,
1450  int dialect,
1451  const char **errmsg)
1452 {
1453  /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1454  as a synonym. If ever a 405 specific dialect is added this
1455  check should use that instead. */
1456  if (value > 7
1457  || (value > 3
1458  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1459  *errmsg = _("invalid sprg number");
1460 
1461  /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1462  user mode. Anything else must use spr 272..279. */
1463  if (value <= 3 || (insn & 0x100) != 0)
1464  value |= 0x10;
1465 
1466  return insn | ((value & 0x17) << 16);
1467 }
1468 
1469 static long
1470 extract_sprg (unsigned long insn,
1471  int dialect,
1472  int *invalid)
1473 {
1474  unsigned long val = (insn >> 16) & 0x1f;
1475 
1476  /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1477  If not BOOKE or 405, then both use only 272..275. */
1478  if (val <= 3
1479  || (val < 0x10 && (insn & 0x100) != 0)
1480  || (val - 0x10 > 3
1481  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1482  *invalid = 1;
1483  return val & 7;
1484 }
1485 
1486 /* The TBR field in an XFX instruction. This is just like SPR, but it
1487  is optional. When TBR is omitted, it must be inserted as 268 (the
1488  magic number of the TB register). These functions treat 0
1489  (indicating an omitted optional operand) as 268. This means that
1490  ``mftb 4,0'' is not handled correctly. This does not matter very
1491  much, since the architecture manual does not define mftb as
1492  accepting any values other than 268 or 269. */
1493 
1494 #define TB (268)
1495 
1496 static unsigned long
1497 insert_tbr (unsigned long insn,
1498  long value,
1499  int dialect ATTRIBUTE_UNUSED,
1500  const char **errmsg ATTRIBUTE_UNUSED)
1501 {
1502  if (value == 0)
1503  value = TB;
1504  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1505 }
1506 
1507 static long
1508 extract_tbr (unsigned long insn,
1509  int dialect ATTRIBUTE_UNUSED,
1510  int *invalid ATTRIBUTE_UNUSED)
1511 {
1512  long ret;
1513 
1514  ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1515  if (ret == TB)
1516  ret = 0;
1517  return ret;
1518 }
1519 
1520 /* Macros used to form opcodes. */
1521 
1522 /* The main opcode. */
1523 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1524 #define OP_MASK OP (0x3f)
1525 
1526 /* The main opcode combined with a trap code in the TO field of a D
1527  form instruction. Used for extended mnemonics for the trap
1528  instructions. */
1529 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1530 #define OPTO_MASK (OP_MASK | TO_MASK)
1531 
1532 /* The main opcode combined with a comparison size bit in the L field
1533  of a D form or X form instruction. Used for extended mnemonics for
1534  the comparison instructions. */
1535 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1536 #define OPL_MASK OPL (0x3f,1)
1537 
1538 /* An A form instruction. */
1539 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1540 #define A_MASK A (0x3f, 0x1f, 1)
1541 
1542 /* An A_MASK with the FRB field fixed. */
1543 #define AFRB_MASK (A_MASK | FRB_MASK)
1544 
1545 /* An A_MASK with the FRC field fixed. */
1546 #define AFRC_MASK (A_MASK | FRC_MASK)
1547 
1548 /* An A_MASK with the FRA and FRC fields fixed. */
1549 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1550 
1551 /* An AFRAFRC_MASK, but with L bit clear. */
1552 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1553 
1554 /* A B form instruction. */
1555 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1556 #define B_MASK B (0x3f, 1, 1)
1557 
1558 /* A B form instruction setting the BO field. */
1559 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1560 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1561 
1562 /* A BBO_MASK with the y bit of the BO field removed. This permits
1563  matching a conditional branch regardless of the setting of the y
1564  bit. Similarly for the 'at' bits used for power4 branch hints. */
1565 #define Y_MASK (((unsigned long) 1) << 21)
1566 #define AT1_MASK (((unsigned long) 3) << 21)
1567 #define AT2_MASK (((unsigned long) 9) << 21)
1568 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1569 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1570 
1571 /* A B form instruction setting the BO field and the condition bits of
1572  the BI field. */
1573 #define BBOCB(op, bo, cb, aa, lk) \
1574  (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1575 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1576 
1577 /* A BBOCB_MASK with the y bit of the BO field removed. */
1578 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1579 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1580 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1581 
1582 /* A BBOYCB_MASK in which the BI field is fixed. */
1583 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1584 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1585 
1586 /* An Context form instruction. */
1587 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1588 #define CTX_MASK CTX(0x3f, 0x7)
1589 
1590 /* An User Context form instruction. */
1591 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1592 #define UCTX_MASK UCTX(0x3f, 0x1f)
1593 
1594 /* The main opcode mask with the RA field clear. */
1595 #define DRA_MASK (OP_MASK | RA_MASK)
1596 
1597 /* A DS form instruction. */
1598 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1599 #define DS_MASK DSO (0x3f, 3)
1600 
1601 /* A DE form instruction. */
1602 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1603 #define DE_MASK DEO (0x3e, 0xf)
1604 
1605 /* An EVSEL form instruction. */
1606 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1607 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1608 
1609 /* An M form instruction. */
1610 #define M(op, rc) (OP (op) | ((rc) & 1))
1611 #define M_MASK M (0x3f, 1)
1612 
1613 /* An M form instruction with the ME field specified. */
1614 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1615 
1616 /* An M_MASK with the MB and ME fields fixed. */
1617 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1618 
1619 /* An M_MASK with the SH and ME fields fixed. */
1620 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1621 
1622 /* An MD form instruction. */
1623 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1624 #define MD_MASK MD (0x3f, 0x7, 1)
1625 
1626 /* An MD_MASK with the MB field fixed. */
1627 #define MDMB_MASK (MD_MASK | MB6_MASK)
1628 
1629 /* An MD_MASK with the SH field fixed. */
1630 #define MDSH_MASK (MD_MASK | SH6_MASK)
1631 
1632 /* An MDS form instruction. */
1633 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1634 #define MDS_MASK MDS (0x3f, 0xf, 1)
1635 
1636 /* An MDS_MASK with the MB field fixed. */
1637 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1638 
1639 /* An SC form instruction. */
1640 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1641 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1642 
1643 /* An VX form instruction. */
1644 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1645 
1646 /* The mask for an VX form instruction. */
1647 #define VX_MASK VX(0x3f, 0x7ff)
1648 
1649 /* An VA form instruction. */
1650 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1651 
1652 /* The mask for an VA form instruction. */
1653 #define VXA_MASK VXA(0x3f, 0x3f)
1654 
1655 /* An VXR form instruction. */
1656 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1657 
1658 /* The mask for a VXR form instruction. */
1659 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1660 
1661 /* An X form instruction. */
1662 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1663 
1664 /* A Z form instruction. */
1665 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1666 
1667 /* An X form instruction with the RC bit specified. */
1668 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1669 
1670 /* A Z form instruction with the RC bit specified. */
1671 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1672 
1673 /* The mask for an X form instruction. */
1674 #define X_MASK XRC (0x3f, 0x3ff, 1)
1675 
1676 /* The mask for a Z form instruction. */
1677 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1678 
1679 /* An X_MASK with the RA field fixed. */
1680 #define XRA_MASK (X_MASK | RA_MASK)
1681 
1682 /* An X_MASK with the RB field fixed. */
1683 #define XRB_MASK (X_MASK | RB_MASK)
1684 
1685 /* An X_MASK with the RT field fixed. */
1686 #define XRT_MASK (X_MASK | RT_MASK)
1687 
1688 /* An XRT_MASK mask with the L bits clear. */
1689 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1690 
1691 /* An X_MASK with the RA and RB fields fixed. */
1692 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1693 
1694 /* An XRARB_MASK, but with the L bit clear. */
1695 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1696 
1697 /* An X_MASK with the RT and RA fields fixed. */
1698 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1699 
1700 /* An XRTRA_MASK, but with L bit clear. */
1701 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1702 
1703 /* An X form instruction with the L bit specified. */
1704 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1705 
1706 /* The mask for an X form comparison instruction. */
1707 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1708 
1709 /* The mask for an X form comparison instruction with the L field
1710  fixed. */
1711 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1712 
1713 /* An X form trap instruction with the TO field specified. */
1714 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1715 #define XTO_MASK (X_MASK | TO_MASK)
1716 
1717 /* An X form tlb instruction with the SH field specified. */
1718 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1719 #define XTLB_MASK (X_MASK | SH_MASK)
1720 
1721 /* An X form sync instruction. */
1722 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1723 
1724 /* An X form sync instruction with everything filled in except the LS field. */
1725 #define XSYNC_MASK (0xff9fffff)
1726 
1727 /* An X_MASK, but with the EH bit clear. */
1728 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1729 
1730 /* An X form AltiVec dss instruction. */
1731 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1732 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1733 
1734 /* An XFL form instruction. */
1735 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1736 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1737 
1738 /* An X form isel instruction. */
1739 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1740 #define XISEL_MASK XISEL(0x3f, 0x1f)
1741 
1742 /* An XL form instruction with the LK field set to 0. */
1743 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1744 
1745 /* An XL form instruction which uses the LK field. */
1746 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1747 
1748 /* The mask for an XL form instruction. */
1749 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1750 
1751 /* An XL form instruction which explicitly sets the BO field. */
1752 #define XLO(op, bo, xop, lk) \
1753  (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1754 #define XLO_MASK (XL_MASK | BO_MASK)
1755 
1756 /* An XL form instruction which explicitly sets the y bit of the BO
1757  field. */
1758 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1759 #define XLYLK_MASK (XL_MASK | Y_MASK)
1760 
1761 /* An XL form instruction which sets the BO field and the condition
1762  bits of the BI field. */
1763 #define XLOCB(op, bo, cb, xop, lk) \
1764  (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1765 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1766 
1767 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1768 #define XLBB_MASK (XL_MASK | BB_MASK)
1769 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1770 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1771 
1772 /* A mask for branch instructions using the BH field. */
1773 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1774 
1775 /* An XL_MASK with the BO and BB fields fixed. */
1776 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1777 
1778 /* An XL_MASK with the BO, BI and BB fields fixed. */
1779 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1780 
1781 /* An XO form instruction. */
1782 #define XO(op, xop, oe, rc) \
1783  (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1784 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1785 
1786 /* An XO_MASK with the RB field fixed. */
1787 #define XORB_MASK (XO_MASK | RB_MASK)
1788 
1789 /* An XS form instruction. */
1790 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1791 #define XS_MASK XS (0x3f, 0x1ff, 1)
1792 
1793 /* A mask for the FXM version of an XFX form instruction. */
1794 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1795 
1796 /* An XFX form instruction with the FXM field filled in. */
1797 #define XFXM(op, xop, fxm, p4) \
1798  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1799  | ((unsigned long)(p4) << 20))
1800 
1801 /* An XFX form instruction with the SPR field filled in. */
1802 #define XSPR(op, xop, spr) \
1803  (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1804 #define XSPR_MASK (X_MASK | SPR_MASK)
1805 
1806 /* An XFX form instruction with the SPR field filled in except for the
1807  SPRBAT field. */
1808 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1809 
1810 /* An XFX form instruction with the SPR field filled in except for the
1811  SPRG field. */
1812 #define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
1813 
1814 /* An X form instruction with everything filled in except the E field. */
1815 #define XE_MASK (0xffff7fff)
1816 
1817 /* An X form user context instruction. */
1818 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1819 #define XUC_MASK XUC(0x3f, 0x1f)
1820 
1821 /* The BO encodings used in extended conditional branch mnemonics. */
1822 #define BODNZF (0x0)
1823 #define BODNZFP (0x1)
1824 #define BODZF (0x2)
1825 #define BODZFP (0x3)
1826 #define BODNZT (0x8)
1827 #define BODNZTP (0x9)
1828 #define BODZT (0xa)
1829 #define BODZTP (0xb)
1830 
1831 #define BOF (0x4)
1832 #define BOFP (0x5)
1833 #define BOFM4 (0x6)
1834 #define BOFP4 (0x7)
1835 #define BOT (0xc)
1836 #define BOTP (0xd)
1837 #define BOTM4 (0xe)
1838 #define BOTP4 (0xf)
1839 
1840 #define BODNZ (0x10)
1841 #define BODNZP (0x11)
1842 #define BODZ (0x12)
1843 #define BODZP (0x13)
1844 #define BODNZM4 (0x18)
1845 #define BODNZP4 (0x19)
1846 #define BODZM4 (0x1a)
1847 #define BODZP4 (0x1b)
1848 
1849 #define BOU (0x14)
1850 
1851 /* The BI condition bit encodings used in extended conditional branch
1852  mnemonics. */
1853 #define CBLT (0)
1854 #define CBGT (1)
1855 #define CBEQ (2)
1856 #define CBSO (3)
1857 
1858 /* The TO encodings used in extended trap mnemonics. */
1859 #define TOLGT (0x1)
1860 #define TOLLT (0x2)
1861 #define TOEQ (0x4)
1862 #define TOLGE (0x5)
1863 #define TOLNL (0x5)
1864 #define TOLLE (0x6)
1865 #define TOLNG (0x6)
1866 #define TOGT (0x8)
1867 #define TOGE (0xc)
1868 #define TONL (0xc)
1869 #define TOLT (0x10)
1870 #define TOLE (0x14)
1871 #define TONG (0x14)
1872 #define TONE (0x18)
1873 #define TOU (0x1f)
1874 
1875 /* Smaller names for the flags so each entry in the opcodes table will
1876  fit on a single line. */
1877 #undef PPC
1878 #define PPC PPC_OPCODE_PPC
1879 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1880 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1881 #define POWER4 PPC_OPCODE_POWER4
1882 #define POWER5 PPC_OPCODE_POWER5
1883 #define POWER6 PPC_OPCODE_POWER6
1884 #define CELL PPC_OPCODE_CELL
1885 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1886 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1887 #define PPC403 PPC_OPCODE_403
1888 #define PPC405 PPC403
1889 #define PPC440 PPC_OPCODE_440
1890 #define PPC750 PPC
1891 #define PPC860 PPC
1892 #define PPCVEC PPC_OPCODE_ALTIVEC
1893 #define POWER PPC_OPCODE_POWER
1894 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1895 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1896 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1897 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1898 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1899 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1900 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1901 #define MFDEC1 PPC_OPCODE_POWER
1902 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1903 #define BOOKE PPC_OPCODE_BOOKE
1904 #define BOOKE64 PPC_OPCODE_BOOKE64
1905 #define CLASSIC PPC_OPCODE_CLASSIC
1906 #define PPCE300 PPC_OPCODE_E300
1907 #define PPCSPE PPC_OPCODE_SPE
1908 #define PPCISEL PPC_OPCODE_ISEL
1909 #define PPCEFS PPC_OPCODE_EFS
1910 #define PPCBRLK PPC_OPCODE_BRLOCK
1911 #define PPCPMR PPC_OPCODE_PMR
1912 #define PPCCHLK PPC_OPCODE_CACHELCK
1913 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1914 #define PPCRFMCI PPC_OPCODE_RFMCI
1915 
1916 /* The opcode table.
1917 
1918  The format of the opcode table is:
1919 
1920  NAME OPCODE MASK FLAGS { OPERANDS }
1921 
1922  NAME is the name of the instruction.
1923  OPCODE is the instruction opcode.
1924  MASK is the opcode mask; this is used to tell the disassembler
1925  which bits in the actual opcode must match OPCODE.
1926  FLAGS are flags indicated what processors support the instruction.
1927  OPERANDS is the list of operands.
1928 
1929  The disassembler reads the table in order and prints the first
1930  instruction which matches, so this table is sorted to put more
1931  specific instructions before more general instructions. It is also
1932  sorted by major opcode. */
1933 
1934 const struct powerpc_opcode powerpc_opcodes[] = {
1935 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1936 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1937 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1938 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1939 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1940 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1941 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1942 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1943 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1944 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1945 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1946 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1947 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1948 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1949 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1950 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1951 
1952 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1953 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1954 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1955 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1956 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1957 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1958 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1959 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1960 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1961 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1962 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1963 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1964 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1965 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1966 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1967 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1968 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1969 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1970 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1971 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1972 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1973 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1974 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1975 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1976 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1977 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1978 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1979 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1980 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1981 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1982 
1983 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1984 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1985 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1986 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1987 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1988 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1991 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1992 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1993 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1994 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1995 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1996 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1997 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1998 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1999 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2000 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2001 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2002 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2003 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2004 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2005 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2006 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2007 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2008 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2009 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2010 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2011 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2012 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2013 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2014 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2015 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2016 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2017 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2018 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2019 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2020 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2021 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2022 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2023 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2024 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2025 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2026 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2027 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2028 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2029 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2030 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2031 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2032 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2033 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2034 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2035 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2036 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2037 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2038 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2039 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2040 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2041 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2042 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2043 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2044 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2045 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2046 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2047 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2048 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2049 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2050 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2051 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2052 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2053 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2054 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2055 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2056 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2057 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2068 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2069 
2070  /* Double-precision opcodes. */
2071  /* Some of these conflict with AltiVec, so move them before, since
2072  PPCVEC includes the PPC_OPCODE_PPC set. */
2073 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2074 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2075 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2076 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2077 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2078 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2079 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2080 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2081 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2082 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2083 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2084 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2085 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2086 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2087 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2088 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2089 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2090 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2091 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2092 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2093 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2094 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2095 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2096 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2097 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2098 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2099 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2100 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2101 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2102  /* End of double-precision opcodes. */
2103 
2104 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2105 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2106 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2107 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2108 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2109 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2110 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2111 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2112 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2113 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2114 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2115 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2116 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2117 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2118 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2119 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2120 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2121 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2122 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2123 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2124 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2125 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2126 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2127 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2128 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2129 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2130 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2131 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2132 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2133 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2134 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2135 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2136 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2137 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2138 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2139 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2140 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2141 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2142 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2143 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2144 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2145 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2146 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2147 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2148 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2149 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2150 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2151 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2152 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2153 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2154 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2155 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2156 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2157 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2158 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2159 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2160 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2161 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2162 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2163 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2164 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2165 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2166 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2167 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2168 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2169 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2170 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2171 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2172 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2173 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2174 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2175 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2176 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2177 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2178 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2179 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2180 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2181 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2182 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2183 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2184 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2185 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2186 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2187 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2188 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2189 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2190 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2191 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2192 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2193 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2194 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2195 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2196 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2197 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2198 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2199 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2200 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2201 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2202 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2203 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2204 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2205 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2206 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2207 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2208 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2209 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2210 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2211 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2212 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2213 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2214 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2215 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2216 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2217 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2218 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2219 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2220 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2221 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2222 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2223 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2224 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2225 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2226 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2227 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2228 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2229 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2230 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2231 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2232 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2233 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2234 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2235 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2236 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2237 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2238 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2239 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2240 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2241 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2242 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2243 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2244 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2245 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2246 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2247 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2248 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2249 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2250 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2251 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2252 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2253 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2254 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2255 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2256 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2257 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2258 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2259 
2260 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2261 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2262 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2263 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2264 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2265 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2266 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2267 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2268 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2269 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2270 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2271 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2272 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2273 
2274 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2275 
2276 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2279 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2285 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 
2287 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2288 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2289 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2291 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2294 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2295 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2296 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2297 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2301 
2302 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2303 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2304 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2305 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2306 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2307 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2308 
2309 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2310 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2312 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2314 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2316 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2318 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2320 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2322 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2324 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2326 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2328 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2330 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 
2332 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2333 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2335 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2337 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2338 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2339 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2341 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2343 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2344 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2345 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2346 
2347 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2348 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2349 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2350 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2351 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2352 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2353 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2355 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2356 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2357 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2358 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2359 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2360 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2361 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2362 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2363 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2364 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2365 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2366 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2367 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2368 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2369 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2370 
2371 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2372 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2373 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2374 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2375 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2376 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2377 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2378 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2379 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2380 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2381 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2382 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2383 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2384 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2385 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2386 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2387 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2388 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2389 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2390 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2391 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2392 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2393 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2394 
2395 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2396 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2397 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2398 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2400 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2402 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2403 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2404 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2406 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2408 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2409 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2410 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2411 
2412 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2413 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2415 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2417 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2418 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2419 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2421 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2422 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2423 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2424 
2425 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2426 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2427 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2428 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2429 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2430 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2432 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2433 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2434 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2435 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2436 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2437 
2438 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2439 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2440 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2441 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2442 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2443 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2444 
2445 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2446 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2447 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2448 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2449 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2450 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2451 
2452 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2453 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2454 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2455 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2456 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2457 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2458 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2459 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2460 
2461 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2462 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2463 
2464 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2465 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2466 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2467 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2468 
2469 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2470 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2471 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2472 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2473 
2474 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2475 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2477 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 
2483 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2486 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 
2488 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2491 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 
2493 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2494 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2495 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2496 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2497 
2498 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2499 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2500 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2501 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2502 
2503 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2504 
2505 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2506 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2507 
2508 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2509 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2510 
2511 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2512 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2513 
2514 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2515 
2516 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2517 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2518 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2519 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2520 
2521 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2522 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2523 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2524 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2525 
2526 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2527 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2528 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2529 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2530 
2531 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2532 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2533 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2534 
2535 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2536 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2537 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2538 
2539 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2540 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2541 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2542 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2543 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2544 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2545 
2546 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2547 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2548 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2549 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2550 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2551 
2552 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2553 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2554 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2555 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2556 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2557 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2558 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2559 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2560 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2561 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2562 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2563 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2564 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2565 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2566 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2567 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2568 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2569 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2570 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2571 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2572 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2573 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2574 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2575 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2576 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2577 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2578 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2579 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2580 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2581 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2582 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2583 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2584 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2585 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2586 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2587 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2588 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2589 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2590 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2591 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2592 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2593 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2594 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2595 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2596 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2597 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2598 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2599 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2600 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2601 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2602 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2603 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2604 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2605 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2606 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2607 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2608 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2609 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2610 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2611 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2612 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2613 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2614 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2615 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2616 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2617 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2618 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2619 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2620 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2621 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2622 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2623 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2624 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2625 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2626 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2627 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2628 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2629 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2630 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2631 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2632 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2633 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2634 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2635 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2636 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2637 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2638 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2639 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2640 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2641 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2642 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2643 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2644 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2645 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2646 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2647 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2648 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2649 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2650 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2651 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2652 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2653 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2654 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2655 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2656 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2657 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2658 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2659 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2660 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2661 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2662 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2663 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2664 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2665 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2666 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2667 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2668 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2669 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2670 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2671 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2672 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2673 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2674 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2675 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2676 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2677 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2678 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2679 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2680 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2681 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2682 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2683 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2684 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2685 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2686 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2687 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2688 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2689 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2690 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2691 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2692 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2693 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2694 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2695 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2696 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2697 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2698 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2699 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2700 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2701 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2702 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2703 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2704 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2705 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2706 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2707 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2708 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2709 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2710 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2711 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2712 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2713 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2714 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2715 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2716 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2717 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2718 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2719 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2720 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2721 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2722 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2723 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2724 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2725 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2726 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2727 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2728 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2729 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2730 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2731 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2732 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2733 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2734 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2735 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2736 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2737 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2738 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2739 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2740 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2741 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2742 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2743 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2744 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2745 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2746 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2747 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2748 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2749 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2750 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2751 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2752 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2753 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2754 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2755 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2756 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2757 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2758 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2759 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2760 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2761 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2762 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2763 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2764 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2765 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2766 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2767 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2768 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2769 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2770 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2771 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2772 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2773 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2774 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2775 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2776 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2777 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2778 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2779 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2780 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2781 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2782 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2783 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2784 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2785 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2786 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2787 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2788 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2789 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2790 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2791 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2792 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2793 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2794 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2795 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2796 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2797 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2798 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2799 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2800 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2801 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2802 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2803 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2804 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2805 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2806 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2807 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2808 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2809 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2810 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2811 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2812 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2813 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2814 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2815 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2816 
2817 { "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2818 { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2819 { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2820 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2821 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2822 
2823 { "b", B(18,0,0), B_MASK, COM, { LI } },
2824 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2825 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2826 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2827 
2828 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2829 
2830 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2831 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2832 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2833 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2834 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2835 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2836 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2837 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2838 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2839 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2840 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2841 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2842 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2843 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2844 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2845 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2846 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2847 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2848 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2849 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2850 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2851 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2852 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2853 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2854 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2855 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2856 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2857 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2858 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2859 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2860 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2861 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2862 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2863 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2864 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2865 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2866 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2867 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2868 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2869 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2870 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2871 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2872 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2873 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2874 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2875 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2876 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2877 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2878 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2879 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2880 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2881 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2882 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2883 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2884 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2885 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2886 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2887 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2888 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2889 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2890 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2891 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2892 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2893 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2894 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2895 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2896 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2897 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2898 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2899 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2900 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2901 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2902 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2903 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2904 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2905 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2906 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2907 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2908 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2909 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2910 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2911 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2912 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2913 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2914 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2915 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2916 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2917 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2918 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2919 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2920 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2921 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2922 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2923 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2924 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2925 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2926 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2927 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2930 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2931 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2932 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2933 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2934 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2935 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2936 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2937 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2938 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2939 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2941 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2942 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2943 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2945 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2946 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2947 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2948 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2949 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2951 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2952 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2953 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2954 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2955 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2956 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2957 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2958 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2959 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2960 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2961 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2962 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2963 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2965 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2966 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2967 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2968 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2969 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2971 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2972 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2973 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2975 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2976 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2977 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2978 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2979 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2981 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2982 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2983 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2984 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2985 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2986 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2987 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2990 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2991 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2992 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2995 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2996 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2997 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2998 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2999 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3000 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3001 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3002 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3003 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3004 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3005 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3006 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3007 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3008 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3009 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3010 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3011 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3012 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3013 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3014 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3015 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3016 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3017 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3018 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3019 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3020 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3021 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3022 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3023 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3024 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3025 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3026 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3027 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3028 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3029 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3030 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3031 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3032 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3033 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3034 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3035 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3036 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3037 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3038 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3039 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3040 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3041 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3042 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3043 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3044 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3045 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3046 { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3047 { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3048 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
3049 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
3050 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
3051 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
3052 
3053 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
3054 
3055 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
3056 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
3057 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
3058 
3059 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
3060 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
3061 
3062 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3063 
3064 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
3065 
3066 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3067 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3068 
3069 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3070 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3071 
3072 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3073 
3074 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3075 
3076 { "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
3077 
3078 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3079 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3080 
3081 { "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
3082 
3083 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3084 
3085 { "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
3086 
3087 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3088 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3089 
3090 { "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
3091 { "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
3092 
3093 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3094 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3095 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3096 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3097 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3098 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3099 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3100 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3101 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3102 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3103 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3104 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3105 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3106 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3107 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3108 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3109 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3110 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3111 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3112 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3113 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3114 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3115 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3116 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3117 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3118 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3119 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3120 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3121 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3122 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3123 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3124 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3125 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3126 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3127 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3128 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3129 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3130 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3131 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3132 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3133 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3134 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3135 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3136 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3137 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3138 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3139 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3140 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3141 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3142 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3143 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3144 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3145 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3146 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3147 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3148 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3149 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3150 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3151 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3152 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3153 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3154 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3155 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3156 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3157 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3158 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3159 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3160 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3161 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3162 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3163 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3164 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3165 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3166 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3167 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3168 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3169 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3170 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3171 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3172 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3173 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3174 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3175 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3176 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3177 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3178 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3179 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3180 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3181 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3182 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3183 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3184 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3185 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3186 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3187 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3188 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3189 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3190 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3191 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3192 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3193 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3194 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3195 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3196 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3197 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3198 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3199 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3200 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3201 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3202 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3203 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3204 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3205 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3206 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3207 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3208 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3209 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3210 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3211 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3212 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3213 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3214 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3215 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3216 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3217 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3218 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3219 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3220 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3221 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3222 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3223 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3224 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3225 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3226 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3227 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3228 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3229 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3230 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3231 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3232 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3233 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3234 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3235 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3236 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3237 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3238 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3239 { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3240 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3241 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3242 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3243 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3244 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3245 
3246 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3247 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3248 
3249 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3250 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3251 
3252 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3253 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3254 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3255 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3256 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3257 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3258 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3259 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3260 
3261 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3262 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3263 
3264 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3265 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3266 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3267 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3268 
3269 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3270 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3271 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3272 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3273 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3274 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3275 
3276 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3277 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3278 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3279 
3280 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3281 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3282 
3283 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3284 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3285 
3286 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3287 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3288 
3289 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3290 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3291 
3292 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3293 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3294 
3295 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3296 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3297 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3298 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3299 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3300 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3301 
3302 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3303 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3304 
3305 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3306 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3307 
3308 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3309 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3310 
3311 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3312 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3313 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3314 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3315 
3316 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3317 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3318 
3319 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3320 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3321 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3322 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3323 
3324 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3325 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3326 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3327 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3328 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3329 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3330 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3331 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3332 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3333 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3334 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3335 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3336 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3337 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3338 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3339 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3340 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3341 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3342 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3343 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3344 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3345 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3346 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3347 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3348 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3349 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3350 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3351 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3352 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3353 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3354 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3355 
3356 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3357 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3358 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3359 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3360 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3361 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3362 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3363 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3364 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3365 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3366 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3367 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3368 
3369 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3370 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3371 
3372 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3373 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3374 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3375 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3376 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3377 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3378 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3379 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3380 
3381 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3382 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3383 
3384 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3385 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3386 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3387 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3388 
3389 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3390 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3391 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3392 
3393 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3394 
3395 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3396 
3397 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3398 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3399 
3400 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3401 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3402 
3403 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3404 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3405 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3406 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3407 
3408 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3409 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3410 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3411 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3412 
3413 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3414 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3415 
3416 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3417 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3418 
3419 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3420 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3421 
3422 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3423 
3424 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3425 
3426 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3427 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3428 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3429 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3430 
3431 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3432 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3433 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3434 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3435 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3436 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3437 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3438 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3439 
3440 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3441 
3442 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3443 
3444 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3445 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3446 
3447 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3448 
3449 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3450 
3451 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3452 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3453 
3454 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3455 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3456 
3457 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3458 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3459 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3460 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3461 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3462 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3463 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3464 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3465 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3466 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3467 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3468 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3469 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3470 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3471 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3472 
3473 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3474 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3475 
3476 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3477 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3478 
3479 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3480 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3481 
3482 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3483 
3484 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3485 
3486 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3487 
3488 { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3489 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
3490 
3491 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3492 
3493 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3494 
3495 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3496 
3497 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3498 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3499 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3500 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3501 
3502 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3503 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3504 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3505 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3506 
3507 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3508 
3509 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3510 
3511 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3512 
3513 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3514 
3515 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3516 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3517 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3518 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3519 
3520 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3521 
3522 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3523 
3524 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3525 
3526 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3527 
3528 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3529 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3530 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3531 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3532 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3533 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3534 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3535 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3536 
3537 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3538 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3541 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3542 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3543 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3544 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3545 
3546 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3547 
3548 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3549 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3550 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3551 
3552 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3553 
3554 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3555 
3556 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3557 
3558 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3559 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3560 
3561 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3562 
3563 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3564 
3565 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3566 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3567 
3568 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3569 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3570 
3571 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3572 
3573 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3574 
3575 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3576 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3577 
3578 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3579 
3580 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3581 
3582 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3583 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3584 
3585 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3586 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3587 
3588 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3589 
3590 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3591 
3592 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3593 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3594 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3595 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3596 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3597 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3598 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3599 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3600 
3601 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3602 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3603 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3604 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3605 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3606 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3607 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3608 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3609 
3610 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3611 
3612 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3613 
3614 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3615 
3616 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3617 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3618 
3619 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3620 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3621 
3622 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3623 
3624 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3625 
3626 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3627 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3628 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3629 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3630 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3631 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3632 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3633 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3634 
3635 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3636 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3637 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3638 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3639 
3640 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3641 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3642 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3643 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3644 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3645 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3646 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3647 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3648 
3649 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3650 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3651 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3652 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3653 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3654 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3655 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3656 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3657 
3658 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3659 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3660 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3661 
3662 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3663 
3664 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3665 
3666 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3667 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3668 
3669 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3670 
3671 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3672 
3673 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3674 
3675 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3676 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3677 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3678 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3679 
3680 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3681 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3682 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3683 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3684 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3685 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3686 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3687 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3688 
3689 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3690 
3691 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3692 
3693 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3694 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3695 
3696 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3697 
3698 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3699 
3700 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3701 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3702 
3703 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3704 
3705 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3706 
3707 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3708 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3709 
3710 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3711 
3712 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3713 
3714 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3715 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3716 
3717 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3718 
3719 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3720 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3721 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3722 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3723 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3724 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3725 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3726 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3727 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3728 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3729 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3730 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3731 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3732 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3733 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3734 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3735 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3736 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3737 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3738 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3739 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3740 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3741 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3742 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3743 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3744 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3745 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3746 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3747 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3748 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3749 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3750 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3751 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3752 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3753 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3754 
3755 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3756 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3757 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3758 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3759 
3760 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3761 
3762 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3763 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3764 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3765 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3766 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3767 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3768 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3769 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3770 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3771 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3772 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3773 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3774 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3775 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3776 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3777 { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3778 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3779 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3780 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3781 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3782 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3783 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3784 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3785 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3786 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3787 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3788 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3789 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3790 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3791 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3792 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3793 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3794 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3795 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3796 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3797 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3798 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3799 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3800 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3801 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3802 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3803 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3804 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3805 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3806 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3807 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3808 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3809 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3810 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3811 { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3812 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3813 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3814 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3815 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3816 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3817 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3818 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3819 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3820 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3821 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3822 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3823 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3824 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3825 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3826 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3827 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3828 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3829 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3830 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3831 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3832 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3833 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3834 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3835 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3836 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3837 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3838 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3839 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3840 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3841 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3842 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3843 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3844 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3845 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3846 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3847 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3848 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3849 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3850 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3851 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3852 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3853 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3854 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3855 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3856 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3857 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3858 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3859 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3860 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3861 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3862 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3863 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3864 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3865 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3866 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3867 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3868 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3869 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3870 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3871 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3872 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3873 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3874 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3875 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3876 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3877 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3878 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3879 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3880 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3881 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3882 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3883 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3884 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3885 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3886 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3887 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3888 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3889 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3890 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3891 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3892 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3893 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3894 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3895 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3896 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3897 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3898 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3899 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3900 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3901 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3902 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3903 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3904 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3905 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3906 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3907 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3908 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3909 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3910 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3911 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3912 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3913 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3914 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3915 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3916 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3917 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3918 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3919 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3920 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3921 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3922 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3923 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3924 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3925 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3926 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3927 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3928 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3929 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3930 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3931 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3932 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3933 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3934 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3935 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3936 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3937 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3938 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3939 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3940 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3941 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3942 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3943 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3944 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3945 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3946 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3947 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3948 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3949 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3950 
3951 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3952 
3953 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3954 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3955 
3956 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3957 
3958 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3959 
3960 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3961 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3962 
3963 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3964 
3965 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3966 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3967 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3968 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3969 
3970 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3971 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3972 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3973 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3974 
3975 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3976 
3977 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3978 
3979 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3980 
3981 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3982 
3983 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3984 
3985 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3986 
3987 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3988 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3989 
3990 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3991 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3992 
3993 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3994 
3995 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3996 
3997 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3998 
3999 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4000 
4001 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4002 
4003 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4004 
4005 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4006 
4007 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4008 
4009 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4010 
4011 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4012 
4013 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4014 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4015 
4016 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4017 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
4018 
4019 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4020 
4021 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4022 
4023 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4024 
4025 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4026 
4027 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4028 
4029 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4030 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4031 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4032 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4033 
4034 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4035 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4036 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4037 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4038 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4039 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4040 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4041 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4042 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4043 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4044 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4045 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4046 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4047 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4048 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4049 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4050 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4051 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4052 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4053 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4054 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4055 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4056 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4057 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4058 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4059 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4060 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4061 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4062 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4063 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4064 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4065 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4066 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4067 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4068 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4069 
4070 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4071 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4072 
4073 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4074 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4075 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4076 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4077 
4078 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4079 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4080 
4081 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4082 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4083 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4084 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4085 
4086 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4087 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4088 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4089 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4090 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4091 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4092 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4093 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4094 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4095 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4096 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4097 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4098 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4099 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4100 { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
4101 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4102 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4103 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4104 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4105 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4106 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4107 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4108 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4109 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4110 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4111 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4112 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4113 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4114 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4115 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4116 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4117 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4118 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4119 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4120 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4121 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4122 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4123 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4124 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4125 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4126 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4127 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4128 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4129 { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4130 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4131 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4132 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4133 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4134 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4135 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4136 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4137 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4138 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4139 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4140 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4141 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4142 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4143 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4144 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4145 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4146 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4147 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4148 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4149 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4150 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4151 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4152 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4153 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4154 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4155 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4156 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4157 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4158 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4159 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4160 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4161 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4162 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4163 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4164 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4165 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4166 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4167 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4168 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4169 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4170 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4171 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4172 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4173 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4174 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4175 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4176 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4177 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4178 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4179 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4180 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4181 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4182 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4183 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4184 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4185 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4186 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4187 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4188 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4189 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4190 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4191 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4192 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4193 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4194 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4195 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4196 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4197 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4198 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4199 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4200 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4201 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4202 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4203 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4204 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4205 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4206 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4207 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4208 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4209 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4210 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4211 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4212 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4213 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4214 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4215 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4216 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4217 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4218 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4219 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4220 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4221 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4222 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4223 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4224 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4225 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4226 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4227 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4228 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4229 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4230 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4231 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4232 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4233 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4234 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4235 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4236 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4237 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4238 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4239 
4240 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4241 
4242 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4243 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4244 
4245 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4246 
4247 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4248 
4249 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4250 
4251 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4252 
4253 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4254 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4255 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4256 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4257 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4258 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4259 
4260 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4261 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4262 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4263 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4264 
4265 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4266 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4267 
4268 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4269 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4270 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4271 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4272 
4273 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4274 
4275 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4276 
4277 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4278 
4279 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4280 
4281 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4282 
4283 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4284 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4285 
4286 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4287 
4288 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4289 
4290 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4291 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4292 
4293 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4294 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4295 
4296 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4297 
4298 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4299 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4300 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4301 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4302 
4303 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4304 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4305 
4306 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4307 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4308 
4309 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4310 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4311 
4312 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4313 
4314 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4315 
4316 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4317 
4318 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4319 
4320 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4321 
4322 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4323 
4324 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4325 
4326 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4327 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4328 
4329 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4330 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4331 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4332 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4333 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4334 
4335 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4336 
4337 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4338 
4339 { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4340 
4341 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4342 
4343 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4344 
4345 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4346 
4347 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4348 
4349 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4350 
4351 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4352 
4353 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4354 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4355 
4356 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4357 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4358 
4359 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4360 
4361 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4362 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4363 
4364 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4365 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4366 
4367 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4368 
4369 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4370 
4371 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4372 
4373 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4374 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4375 
4376 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4377 
4378 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4379 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4380 
4381 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4382 
4383 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4384 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4385 
4386 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4387 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4388 
4389 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4390 
4391 { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4392 
4393 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4394 
4395 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4396 
4397 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4398 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4399 
4400 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4401 
4402 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4403 
4404 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4405 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4406 
4407 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4408 
4409 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4410 
4411 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4412 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4413 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4414 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4415 
4416 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4417 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4418 
4419 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4420 
4421 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4422 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4423 
4424 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4425 
4426 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4427 
4428 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4429 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4430 
4431 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4432 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4433 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4434 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4435 
4436 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4437 
4438 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4439 
4440 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4441 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4442 
4443 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4444 
4445 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4446 
4447 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4448 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4449 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4450 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4451 
4452 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4453 
4454 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4455 
4456 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4457 
4458 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4459 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4460 
4461 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4462 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4463 
4464 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4465 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4466 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4467 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4468 
4469 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4470 
4471 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4472 
4473 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4474 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4475 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4476 
4477 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4478 
4479 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4480 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4481 
4482 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4483 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4484 
4485 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4486 
4487 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4488 
4489 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4490 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4491 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4492 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4493 
4494 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4495 
4496 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4497 
4498 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4499 
4500 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4501 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4502 
4503 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4504 
4505 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4506 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4507 
4508 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4509 
4510 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4511 
4512 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4513 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4514 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4515 
4516 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4517 
4518 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4519 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4520 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4521 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4522 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4523 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4524 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4525 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4526 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4527 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4528 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4529 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4530 
4531 /* New load/store left/right index vector instructions that are in the Cell only. */
4532 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4533 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4534 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4535 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4536 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4537 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4538 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4539 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4540 
4541 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4542 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4543 
4544 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4545 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4546 
4547 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4548 
4549 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4550 
4551 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4552 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4553 
4554 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4555 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4556 
4557 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4558 
4559 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4560 
4561 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4562 
4563 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4564 
4565 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4566 
4567 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4568 
4569 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4570 
4571 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4572 
4573 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4574 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4575 
4576 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4577 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4578 
4579 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4580 
4581 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4582 
4583 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4584 
4585 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4586 
4587 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4588 
4589 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4590 
4591 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4592 
4593 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4594 
4595 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4596 
4597 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4598 
4599 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4600 
4601 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4602 
4603 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4604 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4605 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4606 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4607 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4608 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4609 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4610 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4611 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4612 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4613 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4614 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4615 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4616 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4617 
4618 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4619 
4620 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4621 
4622 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4623 
4624 { "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4625 { "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4626 
4627 { "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4628 { "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4629 
4630 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4631 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4632 
4633 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4634 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4635 
4636 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4637 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4638 
4639 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4640 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4641 
4642 { "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4643 { "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4644 
4645 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4646 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4647 
4648 { "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4649 { "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4650 
4651 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4652 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4653 
4654 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4655 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4656 
4657 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4658 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4659 
4660 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4661 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4662 
4663 { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4664 { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4665 
4666 { "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4667 { "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4668 
4669 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4670 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4671 
4672 { "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4673 { "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4674 
4675 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4676 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4677 
4678 { "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4679 { "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4680 
4681 { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4682 
4683 { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4684 { "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4685 { "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4686 
4687 { "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4688 { "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4689 
4690 { "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4691 { "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4692 
4693 { "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4694 { "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4695 
4696 { "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4697 { "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4698 
4699 { "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4700 { "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4701 
4702 { "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4703 { "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4704 
4705 { "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4706 { "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4707 
4708 { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4709 
4710 { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4711 
4712 { "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4713 { "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4714 
4715 { "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4716 { "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4717 
4718 { "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4719 { "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4720 
4721 { "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4722 { "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4723 
4724 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4725 
4726 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4727 
4728 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4729 
4730 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4731 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4732 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4733 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4734 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4735 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4736 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4737 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4738 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4739 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4740 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4741 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4742 
4743 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4744 
4745 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4746 
4747 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4748 
4749 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4750 
4751 { "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4752 { "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4753 
4754 { "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4755 { "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4756 
4757 { "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4758 { "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4759 
4760 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4761 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4762 
4763 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4764 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4765 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4766 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4767 
4768 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4769 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4770 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4771 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4772 
4773 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4774 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4775 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4776 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4777 
4778 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4779 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4780 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4781 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4782 
4783 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4784 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4785 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4786 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4787 
4788 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4789 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4790 
4791 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4792 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4793 
4794 { "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4795 { "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4796 
4797 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4798 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4799 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4800 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4801 
4802 { "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4803 { "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4804 
4805 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4806 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4807 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4808 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4809 
4810 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4811 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4812 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4813 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4814 
4815 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4816 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4817 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4818 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4819 
4820 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4821 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4822 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4823 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4824 
4825 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4826 
4827 { "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4828 { "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4829 
4830 { "drrndq", ZRC(63,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4831 { "drrndq.", ZRC(63,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4832 
4833 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4834 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4835 
4836 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4837 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4838 
4839 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4840 
4841 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4842 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4843 
4844 { "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4845 { "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4846 
4847 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4848 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4849 
4850 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4851 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4852 
4853 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4854 { "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4855 
4856 { "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4857 { "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4858 
4859 { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4860 
4861 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4862 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4863 
4864 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4865 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4866 
4867 { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4868 { "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4869 { "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4870 
4871 { "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4872 { "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4873 
4874 { "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4875 { "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4876 
4877 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4878 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4879 
4880 { "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4881 { "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4882 
4883 { "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4884 { "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4885 
4886 { "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4887 { "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4888 
4889 { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4890 { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4891 { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4892 { "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4893 { "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4894 { "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4895 { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4896 { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4897 
4898 { "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4899 { "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4900 
4901 { "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4902 { "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4903 
4904 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4905 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4906 
4907 { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4908 
4909 { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4910 
4911 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4912 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4913 
4914 { "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4915 { "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4916 
4917 { "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4918 { "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4919 
4920 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4921 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4922 
4923 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4924 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4925 
4926 { "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4927 { "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4928 
4929 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4930 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4931 
4932 { "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4933 { "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4934 
4935 };
4936 
4937 const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes);
4938 
4939 /* The macro table. This is only used by the assembler. */
4940 
4941 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4942  when x=0; 32-x when x is between 1 and 31; are negative if x is
4943  negative; and are 32 or more otherwise. This is what you want
4944  when, for instance, you are emulating a right shift by a
4945  rotate-left-and-mask, because the underlying instructions support
4946  shifts of size 0 but not shifts of size 32. By comparison, when
4947  extracting x bits from some word you want to use just 32-x, because
4948  the underlying instructions don't support extracting 0 bits but do
4949  support extracting the whole word (32 bits in this case). */
4950 
4951 const struct powerpc_macro powerpc_macros[] = {
4952 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4953 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4954 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4955 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4956 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4957 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4958 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4959 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4960 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4961 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4962 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4963 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4964 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4965 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4966 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4967 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4968 
4969 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4970 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4971 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4972 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4973 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4974 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4975 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4976 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4977 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4978 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4979 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4980 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4981 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4982 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4983 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4984 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4985 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4986 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4987 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4988 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4989 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4990 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4991 };
4992 
4993 const int powerpc_num_macros = ARRAY_SIZE(powerpc_macros);
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