Linux Kernel
3.7.1
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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <plat/common.h>
#include <plat/prcm.h>
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
Go to the source code of this file.
Macros | |
#define | OMAP_PRCM_MAX_NR_PENDING_REG 2 |
Functions | |
upon success, | |
or -ENOENT upon failure. | |
int | omap_prcm_event_to_irq (const char *name) |
void | omap_prcm_irq_cleanup (void) |
void | omap_prcm_irq_prepare (void) |
void | omap_prcm_irq_complete (void) |
int | omap_prcm_register_chain_handler (struct omap_prcm_irq_setup *irq_setup) |
u32 __weak | omap2_prm_read_mod_reg (s16 module, u16 idx) |
void __weak | omap2_prm_write_mod_reg (u32 val, s16 module, u16 idx) |
u32 __weak | omap2_prm_rmw_mod_reg_bits (u32 mask, u32 bits, s16 module, s16 idx) |
u32 __weak | omap2_prm_set_mod_reg_bits (u32 bits, s16 module, s16 idx) |
u32 __weak | omap2_prm_clear_mod_reg_bits (u32 bits, s16 module, s16 idx) |
u32 __weak | omap2_prm_read_mod_bits_shift (s16 domain, s16 idx, u32 mask) |
int __weak | omap2_prm_is_hardreset_asserted (s16 prm_mod, u8 shift) |
int __weak | omap2_prm_assert_hardreset (s16 prm_mod, u8 shift) |
int __weak | omap2_prm_deassert_hardreset (s16 prm_mod, u8 rst_shift, u8 st_shift) |
#define OMAP_PRCM_MAX_NR_PENDING_REG 2 |
Definition at line 39 of file prm_common.c.
omap2_prm_assert_hardreset - assert the HW reset line of a submodule : PRM submodule base (e.g. CORE_MOD) : register bit shift corresponding to the reset line to assert
Some IPs like dsp or iva contain processors that require an HW reset line to be asserted / deasserted in order to fully enable the IP. These modules may have multiple hard-reset lines that reset different 'submodules' inside the IP block. This function will place the submodule into reset. Returns 0 upon success or -EINVAL upon an argument error.
Definition at line 370 of file prm_common.c.
Definition at line 352 of file prm_common.c.
omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait : PRM submodule base (e.g. CORE_MOD) : register bit shift corresponding to the reset line to deassert : register bit shift for the status of the deasserted submodule
Some IPs like dsp or iva contain processors that require an HW reset line to be asserted / deasserted in order to fully enable the IP. These modules may have multiple hard-reset lines that reset different 'submodules' inside the IP block. This function will take the submodule out of reset and wait until the PRCM indicates that the reset has completed before returning. Returns 0 upon success or -EINVAL upon an argument error, -EEXIST if the submodule was already out of reset, or -EBUSY if the submodule did not exit reset promptly.
Definition at line 376 of file prm_common.c.
omap2_prm_is_hardreset_asserted - read the HW reset line state of submodules contained in the hwmod module : PRM submodule base (e.g. CORE_MOD) : register bit shift corresponding to the reset line to check
Returns 1 if the (sub)module hardreset line is currently asserted, 0 if the (sub)module hardreset line is not currently asserted, or -EINVAL if called while running on a non-OMAP2/3 chip.
Definition at line 364 of file prm_common.c.
Definition at line 358 of file prm_common.c.
Definition at line 328 of file prm_common.c.
Definition at line 339 of file prm_common.c.
Definition at line 346 of file prm_common.c.
Definition at line 334 of file prm_common.c.
Definition at line 149 of file prm_common.c.
omap_prcm_irq_cleanup - reverses memory allocated and other steps done by omap_prcm_register_chain_handler()
No return value.
Definition at line 170 of file prm_common.c.
Definition at line 209 of file prm_common.c.
Definition at line 204 of file prm_common.c.
int omap_prcm_register_chain_handler | ( | struct omap_prcm_irq_setup * | irq_setup | ) |
omap_prcm_register_chain_handler - initializes the prcm chained interrupt handler based on provided parameters : hardware data about the underlying PRM/PRCM
Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up one generic IRQ chip per PRM interrupt status/enable register pair. Returns 0 upon success, -EINVAL if called twice or if invalid arguments are passed, or -ENOMEM on any other error.
Definition at line 237 of file prm_common.c.