Data Structures
struct	dpst_ie_histogram_control

struct	dpst_guardband

Macros
#define	GPIOA 0x5010

#define	GPIOB 0x5014

#define	GPIOC 0x5018

#define	GPIOD 0x501c

#define	GPIOE 0x5020

#define	GPIOF 0x5024

#define	GPIOG 0x5028

#define	GPIOH 0x502c

#define	GPIO_CLOCK_DIR_MASK (1 << 0)

#define	GPIO_CLOCK_DIR_IN (0 << 1)

#define	GPIO_CLOCK_DIR_OUT (1 << 1)

#define	GPIO_CLOCK_VAL_MASK (1 << 2)

#define	GPIO_CLOCK_VAL_OUT (1 << 3)

#define	GPIO_CLOCK_VAL_IN (1 << 4)

#define	GPIO_CLOCK_PULLUP_DISABLE (1 << 5)

#define	GPIO_DATA_DIR_MASK (1 << 8)

#define	GPIO_DATA_DIR_IN (0 << 9)

#define	GPIO_DATA_DIR_OUT (1 << 9)

#define	GPIO_DATA_VAL_MASK (1 << 10)

#define	GPIO_DATA_VAL_OUT (1 << 11)

#define	GPIO_DATA_VAL_IN (1 << 12)

#define	GPIO_DATA_PULLUP_DISABLE (1 << 13)

#define	GMBUS0 0x5100 /* clock/port select */

#define	GMBUS_RATE_100KHZ (0<<8)

#define	GMBUS_RATE_50KHZ (1<<8)

#define	GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */

#define	GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */

#define	GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */

#define	GMBUS_PORT_DISABLED 0

#define	GMBUS_PORT_SSC 1

#define	GMBUS_PORT_VGADDC 2

#define	GMBUS_PORT_PANEL 3

#define	GMBUS_PORT_DPC 4 /* HDMIC */

#define	GMBUS_PORT_DPB 5 /* SDVO, HDMIB */

#define	GMBUS_PORT_DPD 7 /* HDMID */

#define	GMBUS_NUM_PORTS 8

#define	GMBUS1 0x5104 /* command/status */

#define	GMBUS_SW_CLR_INT (1<<31)

#define	GMBUS_SW_RDY (1<<30)

#define	GMBUS_ENT (1<<29) /* enable timeout */

#define	GMBUS_CYCLE_NONE (0<<25)

#define	GMBUS_CYCLE_WAIT (1<<25)

#define	GMBUS_CYCLE_INDEX (2<<25)

#define	GMBUS_CYCLE_STOP (4<<25)

#define	GMBUS_BYTE_COUNT_SHIFT 16

#define	GMBUS_SLAVE_INDEX_SHIFT 8

#define	GMBUS_SLAVE_ADDR_SHIFT 1

#define	GMBUS_SLAVE_READ (1<<0)

#define	GMBUS_SLAVE_WRITE (0<<0)

#define	GMBUS2 0x5108 /* status */

#define	GMBUS_INUSE (1<<15)

#define	GMBUS_HW_WAIT_PHASE (1<<14)

#define	GMBUS_STALL_TIMEOUT (1<<13)

#define	GMBUS_INT (1<<12)

#define	GMBUS_HW_RDY (1<<11)

#define	GMBUS_SATOER (1<<10)

#define	GMBUS_ACTIVE (1<<9)

#define	GMBUS3 0x510c /* data buffer bytes 3-0 */

#define	GMBUS4 0x5110 /* interrupt mask (Pineview+) */

#define	GMBUS_SLAVE_TIMEOUT_EN (1<<4)

#define	GMBUS_NAK_EN (1<<3)

#define	GMBUS_IDLE_EN (1<<2)

#define	GMBUS_HW_WAIT_EN (1<<1)

#define	GMBUS_HW_RDY_EN (1<<0)

#define	GMBUS5 0x5120 /* byte index */

#define	GMBUS_2BYTE_INDEX_EN (1<<31)

#define	BLC_PWM_CTL 0x61254

#define	BLC_PWM_CTL2 0x61250

#define	PWM_ENABLE (1 << 31)

#define	PWM_LEGACY_MODE (1 << 30)

#define	PWM_PIPE_B (1 << 29)

#define	BLC_PWM_CTL_C 0x62254

#define	BLC_PWM_CTL2_C 0x62250

#define	BACKLIGHT_MODULATION_FREQ_SHIFT (17)

#define	BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)

#define	BLM_LEGACY_MODE (1 << 16)

#define	BACKLIGHT_DUTY_CYCLE_SHIFT (0)

#define	BACKLIGHT_DUTY_CYCLE_MASK (0xffff)

#define	I915_GCFGC 0xf0

#define	I915_LOW_FREQUENCY_ENABLE (1 << 7)

#define	I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)

#define	I915_DISPLAY_CLOCK_333_MHZ (4 << 4)

#define	I915_DISPLAY_CLOCK_MASK (7 << 4)

#define	I855_HPLLCC 0xc0

#define	I855_CLOCK_CONTROL_MASK (3 << 0)

#define	I855_CLOCK_133_200 (0 << 0)

#define	I855_CLOCK_100_200 (1 << 0)

#define	I855_CLOCK_100_133 (2 << 0)

#define	I855_CLOCK_166_250 (3 << 0)

#define	HTOTAL_A 0x60000

#define	HBLANK_A 0x60004

#define	HSYNC_A 0x60008

#define	VTOTAL_A 0x6000c

#define	VBLANK_A 0x60010

#define	VSYNC_A 0x60014

#define	PIPEASRC 0x6001c

#define	BCLRPAT_A 0x60020

#define	VSYNCSHIFT_A 0x60028

#define	HTOTAL_B 0x61000

#define	HBLANK_B 0x61004

#define	HSYNC_B 0x61008

#define	VTOTAL_B 0x6100c

#define	VBLANK_B 0x61010

#define	VSYNC_B 0x61014

#define	PIPEBSRC 0x6101c

#define	BCLRPAT_B 0x61020

#define	VSYNCSHIFT_B 0x61028

#define	HTOTAL_C 0x62000

#define	HBLANK_C 0x62004

#define	HSYNC_C 0x62008

#define	VTOTAL_C 0x6200c

#define	VBLANK_C 0x62010

#define	VSYNC_C 0x62014

#define	PIPECSRC 0x6201c

#define	BCLRPAT_C 0x62020

#define	VSYNCSHIFT_C 0x62028

#define	PP_STATUS 0x61200

#define	PP_ON (1 << 31)

#define	PP_READY (1 << 30)

#define	PP_SEQUENCE_NONE (0 << 28)

#define	PP_SEQUENCE_ON (1 << 28)

#define	PP_SEQUENCE_OFF (2 << 28)

#define	PP_SEQUENCE_MASK 0x30000000

#define	PP_CYCLE_DELAY_ACTIVE (1 << 27)

#define	PP_SEQUENCE_STATE_ON_IDLE (1 << 3)

#define	PP_SEQUENCE_STATE_MASK 0x0000000f

#define	PP_CONTROL 0x61204

#define	POWER_TARGET_ON (1 << 0)

#define	PANEL_UNLOCK_REGS (0xabcd << 16)

#define	PANEL_UNLOCK_MASK (0xffff << 16)

#define	EDP_FORCE_VDD (1 << 3)

#define	EDP_BLC_ENABLE (1 << 2)

#define	PANEL_POWER_RESET (1 << 1)

#define	PANEL_POWER_OFF (0 << 0)

#define	PANEL_POWER_ON (1 << 0)

#define	LVDSPP_ON 0x61208

#define	LVDSPP_OFF 0x6120c

#define	PP_CYCLE 0x61210

#define	PP_ON_DELAYS 0x61208 /* Cedartrail */

#define	PANEL_PORT_SELECT_MASK (3 << 30)

#define	PANEL_PORT_SELECT_LVDS (0 << 30)

#define	PANEL_PORT_SELECT_EDP (1 << 30)

#define	PANEL_POWER_UP_DELAY_MASK (0x1fff0000)

#define	PANEL_POWER_UP_DELAY_SHIFT 16

#define	PANEL_LIGHT_ON_DELAY_MASK (0x1fff)

#define	PANEL_LIGHT_ON_DELAY_SHIFT 0

#define	PP_OFF_DELAYS 0x6120c /* Cedartrail */

#define	PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)

#define	PANEL_POWER_DOWN_DELAY_SHIFT 16

#define	PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)

#define	PANEL_LIGHT_OFF_DELAY_SHIFT 0

#define	PP_DIVISOR 0x61210 /* Cedartrail */

#define	PP_REFERENCE_DIVIDER_MASK (0xffffff00)

#define	PP_REFERENCE_DIVIDER_SHIFT 8

#define	PANEL_POWER_CYCLE_DELAY_MASK (0x1f)

#define	PANEL_POWER_CYCLE_DELAY_SHIFT 0

#define	PFIT_CONTROL 0x61230

#define	PFIT_ENABLE (1 << 31)

#define	PFIT_PIPE_MASK (3 << 29)

#define	PFIT_PIPE_SHIFT 29

#define	PFIT_SCALING_MODE_PILLARBOX (1 << 27)

#define	PFIT_SCALING_MODE_LETTERBOX (3 << 26)

#define	VERT_INTERP_DISABLE (0 << 10)

#define	VERT_INTERP_BILINEAR (1 << 10)

#define	VERT_INTERP_MASK (3 << 10)

#define	VERT_AUTO_SCALE (1 << 9)

#define	HORIZ_INTERP_DISABLE (0 << 6)

#define	HORIZ_INTERP_BILINEAR (1 << 6)

#define	HORIZ_INTERP_MASK (3 << 6)

#define	HORIZ_AUTO_SCALE (1 << 5)

#define	PANEL_8TO6_DITHER_ENABLE (1 << 3)

#define	PFIT_PGM_RATIOS 0x61234

#define	PFIT_VERT_SCALE_MASK 0xfff00000

#define	PFIT_HORIZ_SCALE_MASK 0x0000fff0

#define	PFIT_AUTO_RATIOS 0x61238

#define	DPLL_A 0x06014

#define	DPLL_B 0x06018

#define	DPLL_VCO_ENABLE (1 << 31)

#define	DPLL_DVO_HIGH_SPEED (1 << 30)

#define	DPLL_SYNCLOCK_ENABLE (1 << 29)

#define	DPLL_VGA_MODE_DIS (1 << 28)

#define	DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */

#define	DPLLB_MODE_LVDS (2 << 26) /* i915 */

#define	DPLL_MODE_MASK (3 << 26)

#define	DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */

#define	DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */

#define	DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */

#define	DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */

#define	DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */

#define	DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000 /* i915 */

#define	DPLL_LOCK (1 << 15) /* CDV */

#define	DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000

#define	DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000

#define	DPLL_FPA01_P1_POST_DIV_SHIFT 16

#define	PLL_P2_DIVIDE_BY_4

#define	PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */

#define	PLL_REF_INPUT_DREFCLK (0 << 13)

#define	PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */

#define	PLL_REF_INPUT_TVCLKINBC

#define	PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)

#define	PLL_REF_INPUT_MASK (3 << 13)

#define	PLL_LOAD_PULSE_PHASE_SHIFT 9

#define	PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)

#define	DISPLAY_RATE_SELECT_FPA1 (1 << 8)

#define	SDVO_MULTIPLIER_MASK 0x000000ff

#define	SDVO_MULTIPLIER_SHIFT_HIRES 4

#define	SDVO_MULTIPLIER_SHIFT_VGA 0

#define	DPLL_A_MD 0x0601c

#define	DPLL_B_MD 0x06020

#define	DPLL_MD_UDI_DIVIDER_MASK 0x3f000000

#define	DPLL_MD_UDI_DIVIDER_SHIFT 24

#define	DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000

#define	DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16

#define	DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00

#define	DPLL_MD_UDI_MULTIPLIER_SHIFT 8

#define	DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f

#define	DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0

#define	DPLL_TEST 0x606c

#define	DPLLB_TEST_SDVO_DIV_1 (0 << 22)

#define	DPLLB_TEST_SDVO_DIV_2 (1 << 22)

#define	DPLLB_TEST_SDVO_DIV_4 (2 << 22)

#define	DPLLB_TEST_SDVO_DIV_MASK (3 << 22)

#define	DPLLB_TEST_N_BYPASS (1 << 19)

#define	DPLLB_TEST_M_BYPASS (1 << 18)

#define	DPLLB_INPUT_BUFFER_ENABLE (1 << 16)

#define	DPLLA_TEST_N_BYPASS (1 << 3)

#define	DPLLA_TEST_M_BYPASS (1 << 2)

#define	DPLLA_INPUT_BUFFER_ENABLE (1 << 0)

#define	ADPA 0x61100

#define	ADPA_DAC_ENABLE (1 << 31)

#define	ADPA_DAC_DISABLE 0

#define	ADPA_PIPE_SELECT_MASK (1 << 30)

#define	ADPA_PIPE_A_SELECT 0

#define	ADPA_PIPE_B_SELECT (1 << 30)

#define	ADPA_USE_VGA_HVPOLARITY (1 << 15)

#define	ADPA_SETS_HVPOLARITY 0

#define	ADPA_VSYNC_CNTL_DISABLE (1 << 11)

#define	ADPA_VSYNC_CNTL_ENABLE 0

#define	ADPA_HSYNC_CNTL_DISABLE (1 << 10)

#define	ADPA_HSYNC_CNTL_ENABLE 0

#define	ADPA_VSYNC_ACTIVE_HIGH (1 << 4)

#define	ADPA_VSYNC_ACTIVE_LOW 0

#define	ADPA_HSYNC_ACTIVE_HIGH (1 << 3)

#define	ADPA_HSYNC_ACTIVE_LOW 0

#define	FPA0 0x06040

#define	FPA1 0x06044

#define	FPB0 0x06048

#define	FPB1 0x0604c

#define	FP_N_DIV_MASK 0x003f0000

#define	FP_N_DIV_SHIFT 16

#define	FP_M1_DIV_MASK 0x00003f00

#define	FP_M1_DIV_SHIFT 8

#define	FP_M2_DIV_MASK 0x0000003f

#define	FP_M2_DIV_SHIFT 0

#define	PORT_HOTPLUG_EN 0x61110

#define	HDMIB_HOTPLUG_INT_EN (1 << 29)

#define	HDMIC_HOTPLUG_INT_EN (1 << 28)

#define	HDMID_HOTPLUG_INT_EN (1 << 27)

#define	SDVOB_HOTPLUG_INT_EN (1 << 26)

#define	SDVOC_HOTPLUG_INT_EN (1 << 25)

#define	TV_HOTPLUG_INT_EN (1 << 18)

#define	CRT_HOTPLUG_INT_EN (1 << 9)

#define	CRT_HOTPLUG_FORCE_DETECT (1 << 3)

#define	CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)

#define	CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)

#define	CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)

#define	CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)

#define	CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)

#define	CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)

#define	CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)

#define	CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)

#define	CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)

#define	CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)

#define	CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)

#define	CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)

#define	CRT_HOTPLUG_DETECT_MASK 0x000000F8

#define	PORT_HOTPLUG_STAT 0x61114

#define	CRT_HOTPLUG_INT_STATUS (1 << 11)

#define	TV_HOTPLUG_INT_STATUS (1 << 10)

#define	CRT_HOTPLUG_MONITOR_MASK (3 << 8)

#define	CRT_HOTPLUG_MONITOR_COLOR (3 << 8)

#define	CRT_HOTPLUG_MONITOR_MONO (2 << 8)

#define	CRT_HOTPLUG_MONITOR_NONE (0 << 8)

#define	SDVOC_HOTPLUG_INT_STATUS (1 << 7)

#define	SDVOB_HOTPLUG_INT_STATUS (1 << 6)

#define	SDVOB 0x61140

#define	SDVOC 0x61160

#define	SDVO_ENABLE (1 << 31)

#define	SDVO_PIPE_B_SELECT (1 << 30)

#define	SDVO_STALL_SELECT (1 << 29)

#define	SDVO_INTERRUPT_ENABLE (1 << 26)

#define	SDVO_COLOR_RANGE_16_235 (1 << 8)

#define	SDVO_AUDIO_ENABLE (1 << 6)

#define	SDVO_PORT_MULTIPLY_MASK (7 << 23)

#define	SDVO_PORT_MULTIPLY_SHIFT 23

#define	SDVO_PHASE_SELECT_MASK (15 << 19)

#define	SDVO_PHASE_SELECT_DEFAULT (6 << 19)

#define	SDVO_CLOCK_OUTPUT_INVERT (1 << 18)

#define	SDVOC_GANG_MODE (1 << 16)

#define	SDVO_BORDER_ENABLE (1 << 7)

#define	SDVOB_PCIE_CONCURRENCY (1 << 3)

#define	SDVO_DETECTED (1 << 2)

#define	SDVOB_PRESERVE_MASK ((1 << 17) \| (1 << 16) \| (1 << 14))

#define	SDVOC_PRESERVE_MASK (1 << 17)

#define	LVDS 0x61180

#define	LVDS_PORT_EN (1 << 31)

#define	LVDS_PIPEB_SELECT (1 << 30)

#define	LVDS_BORDER_EN (1 << 15)

#define	LVDS_A0A2_CLKA_POWER_MASK (3 << 8)

#define	LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)

#define	LVDS_A0A2_CLKA_POWER_UP (3 << 8)

#define	LVDS_A3_POWER_MASK (3 << 6)

#define	LVDS_A3_POWER_DOWN (0 << 6)

#define	LVDS_A3_POWER_UP (3 << 6)

#define	LVDS_CLKB_POWER_MASK (3 << 4)

#define	LVDS_CLKB_POWER_DOWN (0 << 4)

#define	LVDS_CLKB_POWER_UP (3 << 4)

#define	LVDS_B0B3_POWER_MASK (3 << 2)

#define	LVDS_B0B3_POWER_DOWN (0 << 2)

#define	LVDS_B0B3_POWER_UP (3 << 2)

#define	PIPEACONF 0x70008

#define	PIPEACONF_ENABLE (1 << 31)

#define	PIPEACONF_DISABLE 0

#define	PIPEACONF_DOUBLE_WIDE (1 << 30)

#define	PIPECONF_ACTIVE (1 << 30)

#define	I965_PIPECONF_ACTIVE (1 << 30)

#define	PIPECONF_DSIPLL_LOCK (1 << 29)

#define	PIPEACONF_SINGLE_WIDE 0

#define	PIPEACONF_PIPE_UNLOCKED 0

#define	PIPEACONF_DSR (1 << 26)

#define	PIPEACONF_PIPE_LOCKED (1 << 25)

#define	PIPEACONF_PALETTE 0

#define	PIPECONF_FORCE_BORDER (1 << 25)

#define	PIPEACONF_GAMMA (1 << 24)

#define	PIPECONF_PROGRESSIVE (0 << 21)

#define	PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)

#define	PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)

#define	PIPECONF_PLANE_OFF (1 << 19)

#define	PIPECONF_CURSOR_OFF (1 << 18)

#define	PIPEBCONF 0x71008

#define	PIPEBCONF_ENABLE (1 << 31)

#define	PIPEBCONF_DISABLE 0

#define	PIPEBCONF_DOUBLE_WIDE (1 << 30)

#define	PIPEBCONF_DISABLE 0

#define	PIPEBCONF_GAMMA (1 << 24)

#define	PIPEBCONF_PALETTE 0

#define	PIPECCONF 0x72008

#define	PIPEBGCMAXRED 0x71010

#define	PIPEBGCMAXGREEN 0x71014

#define	PIPEBGCMAXBLUE 0x71018

#define	PIPEASTAT 0x70024

#define	PIPEBSTAT 0x71024

#define	PIPECSTAT 0x72024

#define	PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)

#define	PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)

#define	PIPE_VBLANK_CLEAR (1 << 1)

#define	PIPE_VBLANK_STATUS (1 << 1)

#define	PIPE_TE_STATUS (1UL << 6)

#define	PIPE_DPST_EVENT_STATUS (1UL << 7)

#define	PIPE_VSYNC_CLEAR (1UL << 9)

#define	PIPE_VSYNC_STATUS (1UL << 9)

#define	PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10)

#define	PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11)

#define	PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)

#define	PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)

#define	PIPE_TE_ENABLE (1UL << 22)

#define	PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)

#define	PIPE_DPST_EVENT_ENABLE (1UL << 23)

#define	PIPE_VSYNC_ENABL (1UL << 25)

#define	PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26)

#define	PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27)

#define	PIPE_FIFO_UNDERRUN (1UL << 31)

#define	PIPE_HDMI_AUDIO_INT_MASK

#define	PIPE_EVENT_MASK ((1 << 29)\|(1 << 28)\|(1 << 27)\|(1 << 26)\|(1 << 24)\|(1 << 23)\|(1 << 22)\|(1 << 21)\|(1 << 20)\|(1 << 16))

#define	PIPE_VBLANK_MASK ((1 << 25)\|(1 << 24)\|(1 << 18)\|(1 << 17))

#define	HISTOGRAM_INT_CONTROL 0x61268

#define	HISTOGRAM_BIN_DATA 0X61264

#define	HISTOGRAM_LOGIC_CONTROL 0x61260

#define	PWM_CONTROL_LOGIC 0x61250

#define	PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)

#define	HISTOGRAM_INTERRUPT_ENABLE (1UL << 31)

#define	HISTOGRAM_LOGIC_ENABLE (1UL << 31)

#define	PWM_LOGIC_ENABLE (1UL << 31)

#define	PWM_PHASEIN_ENABLE (1UL << 25)

#define	PWM_PHASEIN_INT_ENABLE (1UL << 24)

#define	PWM_PHASEIN_VB_COUNT 0x00001f00

#define	PWM_PHASEIN_INC 0x0000001f

#define	HISTOGRAM_INT_CTRL_CLEAR (1UL << 30)

#define	DPST_YUV_LUMA_MODE 0

#define	PIPEAFRAMEHIGH 0x70040

#define	PIPEAFRAMEPIXEL 0x70044

#define	PIPEBFRAMEHIGH 0x71040

#define	PIPEBFRAMEPIXEL 0x71044

#define	PIPECFRAMEHIGH 0x72040

#define	PIPECFRAMEPIXEL 0x72044

#define	PIPE_FRAME_HIGH_MASK 0x0000ffff

#define	PIPE_FRAME_HIGH_SHIFT 0

#define	PIPE_FRAME_LOW_MASK 0xff000000

#define	PIPE_FRAME_LOW_SHIFT 24

#define	PIPE_PIXEL_MASK 0x00ffffff

#define	PIPE_PIXEL_SHIFT 0

#define	FW_BLC_SELF 0x20e0

#define	FW_BLC_SELF_EN (1<<15)

#define	DSPARB 0x70030

#define	DSPFW1 0x70034

#define	DSP_FIFO_SR_WM_MASK 0xFF800000

#define	DSP_FIFO_SR_WM_SHIFT 23

#define	CURSOR_B_FIFO_WM_MASK 0x003F0000

#define	CURSOR_B_FIFO_WM_SHIFT 16

#define	DSPFW2 0x70038

#define	CURSOR_A_FIFO_WM_MASK 0x3F00

#define	CURSOR_A_FIFO_WM_SHIFT 8

#define	DSP_PLANE_C_FIFO_WM_MASK 0x7F

#define	DSP_PLANE_C_FIFO_WM_SHIFT 0

#define	DSPFW3 0x7003c

#define	DSPFW4 0x70050

#define	DSPFW5 0x70054

#define	DSP_PLANE_B_FIFO_WM1_SHIFT 24

#define	DSP_PLANE_A_FIFO_WM1_SHIFT 16

#define	CURSOR_B_FIFO_WM1_SHIFT 8

#define	CURSOR_FIFO_SR_WM1_SHIFT 0

#define	DSPFW6 0x70058

#define	DSPCHICKENBIT 0x70400

#define	DSPACNTR 0x70180

#define	DSPBCNTR 0x71180

#define	DSPCCNTR 0x72180

#define	DISPLAY_PLANE_ENABLE (1 << 31)

#define	DISPLAY_PLANE_DISABLE 0

#define	DISPPLANE_GAMMA_ENABLE (1 << 30)

#define	DISPPLANE_GAMMA_DISABLE 0

#define	DISPPLANE_PIXFORMAT_MASK (0xf << 26)

#define	DISPPLANE_8BPP (0x2 << 26)

#define	DISPPLANE_15_16BPP (0x4 << 26)

#define	DISPPLANE_16BPP (0x5 << 26)

#define	DISPPLANE_32BPP_NO_ALPHA (0x6 << 26)

#define	DISPPLANE_32BPP (0x7 << 26)

#define	DISPPLANE_STEREO_ENABLE (1 << 25)

#define	DISPPLANE_STEREO_DISABLE 0

#define	DISPPLANE_SEL_PIPE_MASK (1 << 24)

#define	DISPPLANE_SEL_PIPE_POS 24

#define	DISPPLANE_SEL_PIPE_A 0

#define	DISPPLANE_SEL_PIPE_B (1 << 24)

#define	DISPPLANE_SRC_KEY_ENABLE (1 << 22)

#define	DISPPLANE_SRC_KEY_DISABLE 0

#define	DISPPLANE_LINE_DOUBLE (1 << 20)

#define	DISPPLANE_NO_LINE_DOUBLE 0

#define	DISPPLANE_STEREO_POLARITY_FIRST 0

#define	DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)

#define	DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)

#define	DISPPLANE_ALPHA_TRANS_DISABLE 0

#define	DISPPLANE_SPRITE_ABOVE_DISPLAYA 0

#define	DISPPLANE_SPRITE_ABOVE_OVERLAY (1)

#define	DISPPLANE_BOTTOM (4)

#define	DSPABASE 0x70184

#define	DSPALINOFF 0x70184

#define	DSPASTRIDE 0x70188

#define	DSPBBASE 0x71184

#define	DSPBLINOFF 0X71184

#define	DSPBADDR DSPBBASE

#define	DSPBSTRIDE 0x71188

#define	DSPCBASE 0x72184

#define	DSPCLINOFF 0x72184

#define	DSPCSTRIDE 0x72188

#define	DSPAKEYVAL 0x70194

#define	DSPAKEYMASK 0x70198

#define	DSPAPOS 0x7018C /* reserved */

#define	DSPASIZE 0x70190

#define	DSPBPOS 0x7118C

#define	DSPBSIZE 0x71190

#define	DSPCPOS 0x7218C

#define	DSPCSIZE 0x72190

#define	DSPASURF 0x7019C

#define	DSPATILEOFF 0x701A4

#define	DSPBSURF 0x7119C

#define	DSPBTILEOFF 0x711A4

#define	DSPCSURF 0x7219C

#define	DSPCTILEOFF 0x721A4

#define	DSPCKEYMAXVAL 0x721A0

#define	DSPCKEYMINVAL 0x72194

#define	DSPCKEYMSK 0x72198

#define	VGACNTRL 0x71400

#define	VGA_DISP_DISABLE (1 << 31)

#define	VGA_2X_MODE (1 << 30)

#define	VGA_PIPE_B_SELECT (1 << 29)

#define	OV_C_OFFSET 0x08000

#define	OV_OVADD 0x30000

#define	OV_DOVASTA 0x30008

#define	OV_PIPE_SELECT ((1 << 6)\|(1 << 7))

#define	OV_PIPE_SELECT_POS 6

#define	OV_PIPE_A 0

#define	OV_PIPE_C 1

#define	OV_OGAMC5 0x30010

#define	OV_OGAMC4 0x30014

#define	OV_OGAMC3 0x30018

#define	OV_OGAMC2 0x3001C

#define	OV_OGAMC1 0x30020

#define	OV_OGAMC0 0x30024

#define	OVC_OVADD 0x38000

#define	OVC_DOVCSTA 0x38008

#define	OVC_OGAMC5 0x38010

#define	OVC_OGAMC4 0x38014

#define	OVC_OGAMC3 0x38018

#define	OVC_OGAMC2 0x3801C

#define	OVC_OGAMC1 0x38020

#define	OVC_OGAMC0 0x38024

#define	SWF0 0x71410

#define	SWF1 0x71414

#define	SWF2 0x71418

#define	SWF3 0x7141c

#define	SWF4 0x71420

#define	SWF5 0x71424

#define	SWF6 0x71428

#define	SWF00 0x70410

#define	SWF01 0x70414

#define	SWF02 0x70418

#define	SWF03 0x7041c

#define	SWF04 0x70420

#define	SWF05 0x70424

#define	SWF06 0x70428

#define	SWF10 SWF0

#define	SWF11 SWF1

#define	SWF12 SWF2

#define	SWF13 SWF3

#define	SWF14 SWF4

#define	SWF15 SWF5

#define	SWF16 SWF6

#define	SWF30 0x72414

#define	SWF31 0x72418

#define	SWF32 0x7241c

#define	PALETTE_A 0x0a000

#define	PALETTE_B 0x0a800

#define	PALETTE_C 0x0ac00

#define	CURACNTR 0x70080

#define	CURSOR_MODE_DISABLE 0x00

#define	CURSOR_MODE_64_32B_AX 0x07

#define	CURSOR_MODE_64_ARGB_AX ((1 << 5) \| CURSOR_MODE_64_32B_AX)

#define	MCURSOR_GAMMA_ENABLE (1 << 26)

#define	CURABASE 0x70084

#define	CURAPOS 0x70088

#define	CURSOR_POS_MASK 0x007FF

#define	CURSOR_POS_SIGN 0x8000

#define	CURSOR_X_SHIFT 0

#define	CURSOR_Y_SHIFT 16

#define	CURBCNTR 0x700c0

#define	CURBBASE 0x700c4

#define	CURBPOS 0x700c8

#define	CURCCNTR 0x700e0

#define	CURCBASE 0x700e4

#define	CURCPOS 0x700e8

#define	IER 0x020a0

#define	IIR 0x020a4

#define	IMR 0x020a8

#define	ISR 0x020ac

#define	MRST_DPLL_A 0x0f014

#define	MDFLD_DPLL_B 0x0f018

#define	MDFLD_INPUT_REF_SEL (1 << 14)

#define	MDFLD_VCO_SEL (1 << 16)

#define	DPLLA_MODE_LVDS (2 << 26) /* mrst */

#define	MDFLD_PLL_LATCHEN (1 << 28)

#define	MDFLD_PWR_GATE_EN (1 << 30)

#define	MDFLD_P1_MASK (0x1FF << 17)

#define	MRST_FPA0 0x0f040

#define	MRST_FPA1 0x0f044

#define	MDFLD_DPLL_DIV0 0x0f048

#define	MDFLD_DPLL_DIV1 0x0f04c

#define	MRST_PERF_MODE 0x020f4

#define	HDMIPHYMISCCTL 0x61134

#define	HDMI_PHY_POWER_DOWN 0x7f

#define	HDMIB_CONTROL 0x61140

#define	HDMIB_PORT_EN (1 << 31)

#define	HDMIB_PIPE_B_SELECT (1 << 30)

#define	HDMIB_NULL_PACKET (1 << 9)

#define	HDMIB_HDCP_PORT (1 << 5)

#define	MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25)

#define	MRST_PANEL_24_DOT_1_FORMAT (1 << 24)

#define	LVDS_A3_POWER_UP_0_OUTPUT (1 << 6)

#define	MIPI 0x61190

#define	MIPI_C 0x62190

#define	MIPI_PORT_EN (1 << 31)

#define	SEL_FLOPPED_HSTX (1 << 23)

#define	PASS_FROM_SPHY_TO_AFE (1 << 16)

#define	MIPI_BORDER_EN (1 << 15)

#define	MIPIA_3LANE_MIPIC_1LANE 0x1

#define	MIPIA_2LANE_MIPIC_2LANE 0x2

#define	TE_TRIGGER_DSI_PROTOCOL (1 << 2)

#define	TE_TRIGGER_GPIO_PIN (1 << 3)

#define	MIPI_TE_COUNT 0x61194

#define	POWER_DOWN_ON_RESET (1 << 1)

#define	PFIT_PIPE_SELECT (3 << 29)

#define	PFIT_PIPE_SELECT_SHIFT (29)

#define	MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16)

#define	MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)

#define	PIPEACONF_PIPE_STATE (1 << 30)

#define	MRST_DSPABASE 0x7019c

#define	MRST_DSPBBASE 0x7119c

#define	MDFLD_DSPCBASE 0x7219c

#define	MIPIC_REG_OFFSET 0x800

#define	DEVICE_READY_REG 0xb000

#define	LP_OUTPUT_HOLD (1 << 16)

#define	EXIT_ULPS_DEV_READY 0x3

#define	LP_OUTPUT_HOLD_RELEASE 0x810000

#define	ENTERING_ULPS (2 << 1)

#define	EXITING_ULPS (1 << 1)

#define	ULPS_MASK (3 << 1)

#define	BUS_POSSESSION (1 << 3)

#define	INTR_STAT_REG 0xb004

#define	RX_SOT_ERROR (1 << 0)

#define	RX_SOT_SYNC_ERROR (1 << 1)

#define	RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3)

#define	RX_LP_TX_SYNC_ERROR (1 << 4)

#define	RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5)

#define	RX_FALSE_CONTROL_ERROR (1 << 6)

#define	RX_ECC_SINGLE_BIT_ERROR (1 << 7)

#define	RX_ECC_MULTI_BIT_ERROR (1 << 8)

#define	RX_CHECKSUM_ERROR (1 << 9)

#define	RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10)

#define	RX_DSI_VC_ID_INVALID (1 << 11)

#define	TX_FALSE_CONTROL_ERROR (1 << 12)

#define	TX_ECC_SINGLE_BIT_ERROR (1 << 13)

#define	TX_ECC_MULTI_BIT_ERROR (1 << 14)

#define	TX_CHECKSUM_ERROR (1 << 15)

#define	TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16)

#define	TX_DSI_VC_ID_INVALID (1 << 17)

#define	HIGH_CONTENTION (1 << 18)

#define	LOW_CONTENTION (1 << 19)

#define	DPI_FIFO_UNDER_RUN (1 << 20)

#define	HS_TX_TIMEOUT (1 << 21)

#define	LP_RX_TIMEOUT (1 << 22)

#define	TURN_AROUND_ACK_TIMEOUT (1 << 23)

#define	ACK_WITH_NO_ERROR (1 << 24)

#define	HS_GENERIC_WR_FIFO_FULL (1 << 27)

#define	LP_GENERIC_WR_FIFO_FULL (1 << 28)

#define	SPL_PKT_SENT (1 << 30)

#define	INTR_EN_REG 0xb008

#define	DSI_FUNC_PRG_REG 0xb00c

#define	DPI_CHANNEL_NUMBER_POS 0x03

#define	DBI_CHANNEL_NUMBER_POS 0x05

#define	FMT_DPI_POS 0x07

#define	FMT_DBI_POS 0x0A

#define	DBI_DATA_WIDTH_POS 0x0D

#define	RGB_565_FMT 0x01 /* RGB 565 FORMAT */

#define	RGB_666_FMT 0x02 /* RGB 666 FORMAT */

#define	LRGB_666_FMT

#define	RGB_888_FMT 0x04 /* RGB 888 FORMAT */

#define	VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */

#define	VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */

#define	VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */

#define	VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */

#define	DBI_NOT_SUPPORTED

#define	DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */

#define	DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */

#define	DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */

#define	DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */

#define	DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */

#define	HS_TX_TIMEOUT_REG 0xb010

#define	LP_RX_TIMEOUT_REG 0xb014

#define	TURN_AROUND_TIMEOUT_REG 0xb018

#define	DEVICE_RESET_REG 0xb01C

#define	DPI_RESOLUTION_REG 0xb020

#define	RES_V_POS 0x10

#define	DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */

#define	HORIZ_SYNC_PAD_COUNT_REG 0xb028

#define	HORIZ_BACK_PORCH_COUNT_REG 0xb02C

#define	HORIZ_FRONT_PORCH_COUNT_REG 0xb030

#define	HORIZ_ACTIVE_AREA_COUNT_REG 0xb034

#define	VERT_SYNC_PAD_COUNT_REG 0xb038

#define	VERT_BACK_PORCH_COUNT_REG 0xb03c

#define	VERT_FRONT_PORCH_COUNT_REG 0xb040

#define	HIGH_LOW_SWITCH_COUNT_REG 0xb044

#define	DPI_CONTROL_REG 0xb048

#define	DPI_SHUT_DOWN (1 << 0)

#define	DPI_TURN_ON (1 << 1)

#define	DPI_COLOR_MODE_ON (1 << 2)

#define	DPI_COLOR_MODE_OFF (1 << 3)

#define	DPI_BACK_LIGHT_ON (1 << 4)

#define	DPI_BACK_LIGHT_OFF (1 << 5)

#define	DPI_LP (1 << 6)

#define	DPI_DATA_REG 0xb04c

#define	DPI_BACK_LIGHT_ON_DATA 0x07

#define	DPI_BACK_LIGHT_OFF_DATA 0x17

#define	INIT_COUNT_REG 0xb050

#define	MAX_RET_PAK_REG 0xb054

#define	VIDEO_FMT_REG 0xb058

#define	COMPLETE_LAST_PCKT (1 << 2)

#define	EOT_DISABLE_REG 0xb05c

#define	ENABLE_CLOCK_STOPPING (1 << 1)

#define	LP_BYTECLK_REG 0xb060

#define	LP_GEN_DATA_REG 0xb064

#define	HS_GEN_DATA_REG 0xb068

#define	LP_GEN_CTRL_REG 0xb06C

#define	HS_GEN_CTRL_REG 0xb070

#define	DCS_CHANNEL_NUMBER_POS 0x6

#define	MCS_COMMANDS_POS 0x8

#define	WORD_COUNTS_POS 0x8

#define	MCS_PARAMETER_POS 0x10

#define	GEN_FIFO_STAT_REG 0xb074

#define	HS_DATA_FIFO_FULL (1 << 0)

#define	HS_DATA_FIFO_HALF_EMPTY (1 << 1)

#define	HS_DATA_FIFO_EMPTY (1 << 2)

#define	LP_DATA_FIFO_FULL (1 << 8)

#define	LP_DATA_FIFO_HALF_EMPTY (1 << 9)

#define	LP_DATA_FIFO_EMPTY (1 << 10)

#define	HS_CTRL_FIFO_FULL (1 << 16)

#define	HS_CTRL_FIFO_HALF_EMPTY (1 << 17)

#define	HS_CTRL_FIFO_EMPTY (1 << 18)

#define	LP_CTRL_FIFO_FULL (1 << 24)

#define	LP_CTRL_FIFO_HALF_EMPTY (1 << 25)

#define	LP_CTRL_FIFO_EMPTY (1 << 26)

#define	DBI_FIFO_EMPTY (1 << 27)

#define	DPI_FIFO_EMPTY (1 << 28)

#define	HS_LS_DBI_ENABLE_REG 0xb078

#define	TXCLKESC_REG 0xb07c

#define	DPHY_PARAM_REG 0xb080

#define	DBI_BW_CTRL_REG 0xb084

#define	CLK_LANE_SWT_REG 0xb088

#define	MIPI_CONTROL_REG 0xb104

#define	MIPI_2X_CLOCK_BITS ((1 << 0) \| (1 << 1))

#define	MIPI_DATA_ADDRESS_REG 0xb108

#define	MIPI_DATA_LENGTH_REG 0xb10C

#define	MIPI_COMMAND_ADDRESS_REG 0xb110

#define	MIPI_COMMAND_LENGTH_REG 0xb114

#define	MIPI_READ_DATA_RETURN_REG0 0xb118

#define	MIPI_READ_DATA_RETURN_REG1 0xb11C

#define	MIPI_READ_DATA_RETURN_REG2 0xb120

#define	MIPI_READ_DATA_RETURN_REG3 0xb124

#define	MIPI_READ_DATA_RETURN_REG4 0xb128

#define	MIPI_READ_DATA_RETURN_REG5 0xb12C

#define	MIPI_READ_DATA_RETURN_REG6 0xb130

#define	MIPI_READ_DATA_RETURN_REG7 0xb134

#define	MIPI_READ_DATA_VALID_REG 0xb138

#define	soft_reset 0x01

#define	get_power_mode 0x0a

#define	get_address_mode 0x0b

#define	get_pixel_format 0x0c

#define	get_display_mode 0x0d

#define	get_signal_mode 0x0e

#define	get_diagnostic_result 0x0f

#define	enter_sleep_mode 0x10

#define	exit_sleep_mode 0x11

#define	enter_partial_mode 0x12

#define	enter_normal_mode 0x13

#define	exit_invert_mode 0x20

#define	enter_invert_mode 0x21

#define	set_gamma_curve 0x26

#define	set_display_off 0x28

#define	set_display_on 0x29

#define	set_column_address 0x2a

#define	set_page_addr 0x2b

#define	write_mem_start 0x2c

#define	set_partial_area 0x30

#define	set_scroll_area 0x33

#define	set_tear_off 0x34

#define	set_tear_on 0x35

#define	set_address_mode 0x36

#define	set_scroll_start 0x37

#define	exit_idle_mode 0x38

#define	enter_idle_mode 0x39

#define	set_pixel_format 0x3a

#define	DCS_PIXEL_FORMAT_3bpp 0x1

#define	DCS_PIXEL_FORMAT_8bpp 0x2

#define	DCS_PIXEL_FORMAT_12bpp 0x3

#define	DCS_PIXEL_FORMAT_16bpp 0x5

#define	DCS_PIXEL_FORMAT_18bpp 0x6

#define	DCS_PIXEL_FORMAT_24bpp 0x7

#define	write_mem_cont 0x3c

#define	set_tear_scanline 0x44

#define	get_scanline 0x45

#define	GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */

#define	GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */

#define	GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */

#define	GEN_READ_0 0x04 /* generic read, no parameters */

#define	GEN_READ_1 0x14 /* generic read, 1 parameters */

#define	GEN_READ_2 0x24 /* generic read, 2 parameters */

#define	GEN_LONG_WRITE 0x29 /* generic long write */

#define	MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */

#define	MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */

#define	MCS_READ 0x06 /* MCS read, no parameters */

#define	MCS_LONG_WRITE 0x39 /* MCS long write */

#define	write_display_profile 0x50

#define	write_display_brightness 0x51

#define	write_ctrl_display 0x53

#define	write_ctrl_cabc 0x55

#define	UI_IMAGE 0x01

#define	STILL_IMAGE 0x02

#define	MOVING_IMAGE 0x03

#define	write_hysteresis 0x57

#define	write_gamma_setting 0x58

#define	write_cabc_min_bright 0x5e

#define	write_kbbc_profile 0x60

#define	tmd_write_display_brightness 0x8c

#define	BRIGHT_CNTL_BLOCK_ON (1 << 5)

#define	AMBIENT_LIGHT_SENSE_ON (1 << 4)

#define	DISPLAY_DIMMING_ON (1 << 3)

#define	BACKLIGHT_ON (1 << 2)

#define	DISPLAY_BRIGHTNESS_AUTO (1 << 1)

#define	GAMMA_AUTO (1 << 0)

#define	DCS_PIXEL_FORMAT_3BPP 0x1

#define	DCS_PIXEL_FORMAT_8BPP 0x2

#define	DCS_PIXEL_FORMAT_12BPP 0x3

#define	DCS_PIXEL_FORMAT_16BPP 0x5

#define	DCS_PIXEL_FORMAT_18BPP 0x6

#define	DCS_PIXEL_FORMAT_24BPP 0x7

#define	addr_mode_data 0xfc

#define	diag_res_data 0x00

#define	disp_mode_data 0x23

#define	pxl_fmt_data 0x77

#define	pwr_mode_data 0x74

#define	sig_mode_data 0x00

#define	scanline_data1 0xff

#define	scanline_data2 0xff

#define	NON_BURST_MODE_SYNC_PULSE

#define	NON_BURST_MODE_SYNC_EVENTS

#define	BURST_MODE 0x03 /* Burst Mode */

#define	DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 / / 0x120 */

#define	DBI_DATA_BUFFER_SIZE

#define	DBI_CB_TIME_OUT 0xFFFF

#define	GEN_FB_TIME_OUT 2000

#define	SKU_83 0x01

#define	SKU_100 0x02

#define	SKU_100L 0x04

#define	SKU_BYPASS 0x08

#define	PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))

#define	SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)

#define	GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)

#define	_PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))

#define	SB_PCKT 0x02100 /* cedarview */

#define	SB_OPCODE_MASK PSB_MASK(31, 16)

#define	SB_OPCODE_SHIFT 16

#define	SB_OPCODE_READ 0

#define	SB_OPCODE_WRITE 1

#define	SB_DEST_MASK PSB_MASK(15, 8)

#define	SB_DEST_SHIFT 8

#define	SB_DEST_DPLL 0x88

#define	SB_BYTE_ENABLE_MASK PSB_MASK(7, 4)

#define	SB_BYTE_ENABLE_SHIFT 4

#define	SB_BUSY (1 << 0)

#define	DSPCLK_GATE_D 0x6200

#define	VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */

#define	DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)

#define	DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)

#define	DPUNIT_PIPEB_GATE_DISABLE (1 << 30)

#define	DPUNIT_PIPEA_GATE_DISABLE (1 << 25)

#define	DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)

#define	DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)

#define	RAMCLK_GATE_D 0x6210

#define	SB_DATA 0x02104 /* cedarview */

#define	SB_ADDR 0x02108 /* cedarview */

#define	DPIO_CFG 0x02110 /* cedarview */

#define	DPIO_MODE_SELECT_1 (1 << 3)

#define	DPIO_MODE_SELECT_0 (1 << 2)

#define	DPIO_SFR_BYPASS (1 << 1)

#define	DPIO_CMN_RESET_N (1 << 0)

#define	_SB_M_A 0x8008

#define	_SB_M_B 0x8028

#define	SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B)

#define	SB_M_DIVIDER_MASK (0xFF << 24)

#define	SB_M_DIVIDER_SHIFT 24

#define	_SB_N_VCO_A 0x8014

#define	_SB_N_VCO_B 0x8034

#define	SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)

#define	SB_N_VCO_SEL_MASK PSB_MASK(31, 30)

#define	SB_N_VCO_SEL_SHIFT 30

#define	SB_N_DIVIDER_MASK PSB_MASK(29, 26)

#define	SB_N_DIVIDER_SHIFT 26

#define	SB_N_CB_TUNE_MASK PSB_MASK(25, 24)

#define	SB_N_CB_TUNE_SHIFT 24

#define	SB_REF_DPLLA 0x8010

#define	SB_REF_DPLLB 0x8030

#define	REF_CLK_MASK (0x3 << 13)

#define	REF_CLK_CORE (0 << 13)

#define	REF_CLK_DPLL (1 << 13)

#define	REF_CLK_DPLLA (2 << 13)

#define	_SB_REF_A 0x8018

#define	_SB_REF_B 0x8038

#define	SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B)

#define	_SB_P_A 0x801c

#define	_SB_P_B 0x803c

#define	SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B)

#define	SB_P2_DIVIDER_MASK PSB_MASK(31, 30)

#define	SB_P2_DIVIDER_SHIFT 30

#define	SB_P2_10 0 /* HDMI, DP, DAC */

#define	SB_P2_5 1 /* DAC */

#define	SB_P2_14 2 /* LVDS single */

#define	SB_P2_7 3 /* LVDS double */

#define	SB_P1_DIVIDER_MASK PSB_MASK(15, 12)

#define	SB_P1_DIVIDER_SHIFT 12

#define	PSB_LANE0 0x120

#define	PSB_LANE1 0x220

#define	PSB_LANE2 0x2320

#define	PSB_LANE3 0x2420

#define	LANE_PLL_MASK (0x7 << 20)

#define	LANE_PLL_ENABLE (0x3 << 20)

#define	LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21))

#define	DP_B 0x64100

#define	DP_C 0x64200

#define	DP_PORT_EN (1 << 31)

#define	DP_PIPEB_SELECT (1 << 30)

#define	DP_PIPE_MASK (1 << 30)

#define	DP_LINK_TRAIN_PAT_1 (0 << 28)

#define	DP_LINK_TRAIN_PAT_2 (1 << 28)

#define	DP_LINK_TRAIN_PAT_IDLE (2 << 28)

#define	DP_LINK_TRAIN_OFF (3 << 28)

#define	DP_LINK_TRAIN_MASK (3 << 28)

#define	DP_LINK_TRAIN_SHIFT 28

#define	DP_VOLTAGE_0_4 (0 << 25)

#define	DP_VOLTAGE_0_6 (1 << 25)

#define	DP_VOLTAGE_0_8 (2 << 25)

#define	DP_VOLTAGE_1_2 (3 << 25)

#define	DP_VOLTAGE_MASK (7 << 25)

#define	DP_VOLTAGE_SHIFT 25

#define	DP_PRE_EMPHASIS_0 (0 << 22)

#define	DP_PRE_EMPHASIS_3_5 (1 << 22)

#define	DP_PRE_EMPHASIS_6 (2 << 22)

#define	DP_PRE_EMPHASIS_9_5 (3 << 22)

#define	DP_PRE_EMPHASIS_MASK (7 << 22)

#define	DP_PRE_EMPHASIS_SHIFT 22

#define	DP_PORT_WIDTH_1 (0 << 19)

#define	DP_PORT_WIDTH_2 (1 << 19)

#define	DP_PORT_WIDTH_4 (3 << 19)

#define	DP_PORT_WIDTH_MASK (7 << 19)

#define	DP_ENHANCED_FRAMING (1 << 18)

#define	DP_PORT_REVERSAL (1 << 15)

#define	DP_CLOCK_OUTPUT_ENABLE (1 << 13)

#define	DP_SCRAMBLING_DISABLE (1 << 12)

#define	DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)

#define	DP_COLOR_RANGE_16_235 (1 << 8)

#define	DP_AUDIO_OUTPUT_ENABLE (1 << 6)

#define	DP_SYNC_VS_HIGH (1 << 4)

#define	DP_SYNC_HS_HIGH (1 << 3)

#define	DP_DETECTED (1 << 2)

#define	DPB_AUX_CH_CTL 0x64110

#define	DPB_AUX_CH_DATA1 0x64114

#define	DPB_AUX_CH_DATA2 0x64118

#define	DPB_AUX_CH_DATA3 0x6411c

#define	DPB_AUX_CH_DATA4 0x64120

#define	DPB_AUX_CH_DATA5 0x64124

#define	DPC_AUX_CH_CTL 0x64210

#define	DPC_AUX_CH_DATA1 0x64214

#define	DPC_AUX_CH_DATA2 0x64218

#define	DPC_AUX_CH_DATA3 0x6421c

#define	DPC_AUX_CH_DATA4 0x64220

#define	DPC_AUX_CH_DATA5 0x64224

#define	DP_AUX_CH_CTL_SEND_BUSY (1 << 31)

#define	DP_AUX_CH_CTL_DONE (1 << 30)

#define	DP_AUX_CH_CTL_INTERRUPT (1 << 29)

#define	DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)

#define	DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)

#define	DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)

#define	DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)

#define	DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)

#define	DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)

#define	DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)

#define	DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)

#define	DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20

#define	DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)

#define	DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16

#define	DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)

#define	DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)

#define	DP_AUX_CH_CTL_SYNC_TEST (1 << 13)

#define	DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)

#define	DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)

#define	DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)

#define	DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0

#define	_PIPEA_GMCH_DATA_M 0x70050

#define	_PIPEB_GMCH_DATA_M 0x71050

#define	PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)

#define	PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25

#define	PIPE_GMCH_DATA_M_MASK (0xffffff)

#define	_PIPEA_GMCH_DATA_N 0x70054

#define	_PIPEB_GMCH_DATA_N 0x71054

#define	PIPE_GMCH_DATA_N_MASK (0xffffff)

#define	_PIPEA_DP_LINK_M 0x70060

#define	_PIPEB_DP_LINK_M 0x71060

#define	PIPEA_DP_LINK_M_MASK (0xffffff)

#define	_PIPEA_DP_LINK_N 0x70064

#define	_PIPEB_DP_LINK_N 0x71064

#define	PIPEA_DP_LINK_N_MASK (0xffffff)

#define	PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)

#define	PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)

#define	PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)

#define	PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)

#define	PIPE_BPC_MASK (7 << 5)

#define	PIPE_8BPC (0 << 5)

#define	PIPE_10BPC (1 << 5)

#define	PIPE_6BPC (2 << 5)

Macro Definition Documentation

#define _PIPE	(	pipe,
		a,
		b
	)	((a) + (pipe)*((b)-(a)))

Definition at line 1283 of file psb_intel_reg.h.

#define _PIPEA_DP_LINK_M 0x70060

Definition at line 1515 of file psb_intel_reg.h.

#define _PIPEA_DP_LINK_N 0x70064

Definition at line 1519 of file psb_intel_reg.h.

#define _PIPEA_GMCH_DATA_M 0x70050

Definition at line 1491 of file psb_intel_reg.h.

#define _PIPEA_GMCH_DATA_N 0x70054

Definition at line 1500 of file psb_intel_reg.h.

#define _PIPEB_DP_LINK_M 0x71060

Definition at line 1516 of file psb_intel_reg.h.

#define _PIPEB_DP_LINK_N 0x71064

Definition at line 1520 of file psb_intel_reg.h.

#define _PIPEB_GMCH_DATA_M 0x71050

Definition at line 1492 of file psb_intel_reg.h.

#define _PIPEB_GMCH_DATA_N 0x71054

Definition at line 1501 of file psb_intel_reg.h.

#define _SB_M_A 0x8008

Definition at line 1322 of file psb_intel_reg.h.

#define _SB_M_B 0x8028

Definition at line 1323 of file psb_intel_reg.h.

#define _SB_N_VCO_A 0x8014

Definition at line 1328 of file psb_intel_reg.h.

#define _SB_N_VCO_B 0x8034

Definition at line 1329 of file psb_intel_reg.h.

#define _SB_P_A 0x801c

Definition at line 1351 of file psb_intel_reg.h.

#define _SB_P_B 0x803c

Definition at line 1352 of file psb_intel_reg.h.

#define _SB_REF_A 0x8018

Definition at line 1347 of file psb_intel_reg.h.

#define _SB_REF_B 0x8038

Definition at line 1348 of file psb_intel_reg.h.

#define ACK_WITH_NO_ERROR (1 << 24)

Definition at line 905 of file psb_intel_reg.h.

#define addr_mode_data 0xfc

Definition at line 1251 of file psb_intel_reg.h.

#define ADPA 0x61100

Definition at line 349 of file psb_intel_reg.h.

#define ADPA_DAC_DISABLE 0

Definition at line 351 of file psb_intel_reg.h.

#define ADPA_DAC_ENABLE (1 << 31)

Definition at line 350 of file psb_intel_reg.h.

#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)

Definition at line 363 of file psb_intel_reg.h.

#define ADPA_HSYNC_ACTIVE_LOW 0

Definition at line 364 of file psb_intel_reg.h.

#define ADPA_HSYNC_CNTL_DISABLE (1 << 10)

Definition at line 359 of file psb_intel_reg.h.

#define ADPA_HSYNC_CNTL_ENABLE 0

Definition at line 360 of file psb_intel_reg.h.

#define ADPA_PIPE_A_SELECT 0

Definition at line 353 of file psb_intel_reg.h.

#define ADPA_PIPE_B_SELECT (1 << 30)

Definition at line 354 of file psb_intel_reg.h.

#define ADPA_PIPE_SELECT_MASK (1 << 30)

Definition at line 352 of file psb_intel_reg.h.

#define ADPA_SETS_HVPOLARITY 0

Definition at line 356 of file psb_intel_reg.h.

#define ADPA_USE_VGA_HVPOLARITY (1 << 15)

Definition at line 355 of file psb_intel_reg.h.

#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)

Definition at line 361 of file psb_intel_reg.h.

#define ADPA_VSYNC_ACTIVE_LOW 0

Definition at line 362 of file psb_intel_reg.h.

#define ADPA_VSYNC_CNTL_DISABLE (1 << 11)

Definition at line 357 of file psb_intel_reg.h.

#define ADPA_VSYNC_CNTL_ENABLE 0

Definition at line 358 of file psb_intel_reg.h.

#define AMBIENT_LIGHT_SENSE_ON (1 << 4)

Definition at line 1237 of file psb_intel_reg.h.

#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)

Definition at line 116 of file psb_intel_reg.h.

#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)

Definition at line 115 of file psb_intel_reg.h.

#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)

Definition at line 106 of file psb_intel_reg.h.

#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)

Definition at line 99 of file psb_intel_reg.h.

#define BACKLIGHT_ON (1 << 2)

Definition at line 1239 of file psb_intel_reg.h.

#define BCLRPAT_A 0x60020

Definition at line 139 of file psb_intel_reg.h.

#define BCLRPAT_B 0x61020

Definition at line 149 of file psb_intel_reg.h.

#define BCLRPAT_C 0x62020

Definition at line 159 of file psb_intel_reg.h.

#define BLC_PWM_CTL 0x61254

Definition at line 92 of file psb_intel_reg.h.

#define BLC_PWM_CTL2 0x61250

Definition at line 93 of file psb_intel_reg.h.

#define BLC_PWM_CTL2_C 0x62250

Definition at line 98 of file psb_intel_reg.h.

#define BLC_PWM_CTL_C 0x62254

Definition at line 97 of file psb_intel_reg.h.

#define BLM_LEGACY_MODE (1 << 16)

Definition at line 107 of file psb_intel_reg.h.

#define BRIGHT_CNTL_BLOCK_ON (1 << 5)

Definition at line 1236 of file psb_intel_reg.h.

#define BURST_MODE 0x03 /* Burst Mode */

Definition at line 1262 of file psb_intel_reg.h.

#define BUS_POSSESSION (1 << 3)

Definition at line 880 of file psb_intel_reg.h.

#define CLK_LANE_SWT_REG 0xb088

Definition at line 994 of file psb_intel_reg.h.

#define COMPLETE_LAST_PCKT (1 << 2)

Definition at line 963 of file psb_intel_reg.h.

#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)

Definition at line 387 of file psb_intel_reg.h.

#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)

Definition at line 388 of file psb_intel_reg.h.

#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)

Definition at line 389 of file psb_intel_reg.h.

#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)

Definition at line 395 of file psb_intel_reg.h.

#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)

Definition at line 396 of file psb_intel_reg.h.

#define CRT_HOTPLUG_DETECT_MASK 0x000000F8

Definition at line 399 of file psb_intel_reg.h.

#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)

Definition at line 397 of file psb_intel_reg.h.

#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)

Definition at line 398 of file psb_intel_reg.h.

#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)

Definition at line 385 of file psb_intel_reg.h.

#define CRT_HOTPLUG_INT_EN (1 << 9)

Definition at line 384 of file psb_intel_reg.h.

#define CRT_HOTPLUG_INT_STATUS (1 << 11)

Definition at line 402 of file psb_intel_reg.h.

#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)

Definition at line 405 of file psb_intel_reg.h.

#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)

Definition at line 404 of file psb_intel_reg.h.

#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)

Definition at line 406 of file psb_intel_reg.h.

#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)

Definition at line 407 of file psb_intel_reg.h.

#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)

Definition at line 390 of file psb_intel_reg.h.

#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)

Definition at line 391 of file psb_intel_reg.h.

#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)

Definition at line 392 of file psb_intel_reg.h.

#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)

Definition at line 393 of file psb_intel_reg.h.

#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)

Definition at line 394 of file psb_intel_reg.h.

#define CURABASE 0x70084

Definition at line 778 of file psb_intel_reg.h.

#define CURACNTR 0x70080

Definition at line 773 of file psb_intel_reg.h.

#define CURAPOS 0x70088

Definition at line 779 of file psb_intel_reg.h.

#define CURBBASE 0x700c4

Definition at line 785 of file psb_intel_reg.h.

#define CURBCNTR 0x700c0

Definition at line 784 of file psb_intel_reg.h.

#define CURBPOS 0x700c8

Definition at line 786 of file psb_intel_reg.h.

#define CURCBASE 0x700e4

Definition at line 788 of file psb_intel_reg.h.

#define CURCCNTR 0x700e0

Definition at line 787 of file psb_intel_reg.h.

#define CURCPOS 0x700e8

Definition at line 789 of file psb_intel_reg.h.

#define CURSOR_A_FIFO_WM_MASK 0x3F00

Definition at line 619 of file psb_intel_reg.h.

#define CURSOR_A_FIFO_WM_SHIFT 8

Definition at line 620 of file psb_intel_reg.h.

#define CURSOR_B_FIFO_WM1_SHIFT 8

Definition at line 628 of file psb_intel_reg.h.

#define CURSOR_B_FIFO_WM_MASK 0x003F0000

Definition at line 616 of file psb_intel_reg.h.

#define CURSOR_B_FIFO_WM_SHIFT 16

Definition at line 617 of file psb_intel_reg.h.

#define CURSOR_FIFO_SR_WM1_SHIFT 0

Definition at line 629 of file psb_intel_reg.h.

#define CURSOR_MODE_64_32B_AX 0x07

Definition at line 775 of file psb_intel_reg.h.

#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)

Definition at line 776 of file psb_intel_reg.h.

#define CURSOR_MODE_DISABLE 0x00

Definition at line 774 of file psb_intel_reg.h.

#define CURSOR_POS_MASK 0x007FF

Definition at line 780 of file psb_intel_reg.h.

#define CURSOR_POS_SIGN 0x8000

Definition at line 781 of file psb_intel_reg.h.

#define CURSOR_X_SHIFT 0

Definition at line 782 of file psb_intel_reg.h.

#define CURSOR_Y_SHIFT 16

Definition at line 783 of file psb_intel_reg.h.

#define DBI_BW_CTRL_REG 0xb084

Definition at line 993 of file psb_intel_reg.h.

#define DBI_CB_TIME_OUT 0xFFFF

Definition at line 1269 of file psb_intel_reg.h.

#define DBI_CHANNEL_NUMBER_POS 0x05

Definition at line 912 of file psb_intel_reg.h.

#define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */

Definition at line 1263 of file psb_intel_reg.h.

#define DBI_DATA_BUFFER_SIZE

Value:

0x120   /* Allocate at least
                         * 0x100 Byte with 32
                         * byte alignment
                         */

Definition at line 1268 of file psb_intel_reg.h.

#define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */

Definition at line 928 of file psb_intel_reg.h.

#define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */

Definition at line 930 of file psb_intel_reg.h.

#define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */

Definition at line 929 of file psb_intel_reg.h.

#define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */

Definition at line 931 of file psb_intel_reg.h.

#define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */

Definition at line 932 of file psb_intel_reg.h.

#define DBI_DATA_WIDTH_POS 0x0D

Definition at line 915 of file psb_intel_reg.h.

#define DBI_FIFO_EMPTY (1 << 27)

Definition at line 988 of file psb_intel_reg.h.

#define DBI_NOT_SUPPORTED

Value:

0x00    /* command mode
                             * is not supported
                             */

Definition at line 927 of file psb_intel_reg.h.

#define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */

Definition at line 940 of file psb_intel_reg.h.

#define DCS_CHANNEL_NUMBER_POS 0x6

Definition at line 971 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_12bpp 0x3

Definition at line 1176 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_12BPP 0x3

Definition at line 1246 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_16bpp 0x5

Definition at line 1177 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_16BPP 0x5

Definition at line 1247 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_18bpp 0x6

Definition at line 1178 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_18BPP 0x6

Definition at line 1248 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_24bpp 0x7

Definition at line 1179 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_24BPP 0x7

Definition at line 1249 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_3bpp 0x1

Definition at line 1174 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_3BPP 0x1

Definition at line 1244 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_8bpp 0x2

Definition at line 1175 of file psb_intel_reg.h.

#define DCS_PIXEL_FORMAT_8BPP 0x2

Definition at line 1245 of file psb_intel_reg.h.

#define DEVICE_READY_REG 0xb000

Definition at line 873 of file psb_intel_reg.h.

#define DEVICE_RESET_REG 0xb01C

Definition at line 937 of file psb_intel_reg.h.

#define diag_res_data 0x00

Definition at line 1252 of file psb_intel_reg.h.

#define disp_mode_data 0x23

Definition at line 1253 of file psb_intel_reg.h.

#define DISPLAY_BRIGHTNESS_AUTO (1 << 1)

Definition at line 1240 of file psb_intel_reg.h.

#define DISPLAY_DIMMING_ON (1 << 3)

Definition at line 1238 of file psb_intel_reg.h.

#define DISPLAY_PLANE_DISABLE 0

Definition at line 636 of file psb_intel_reg.h.

#define DISPLAY_PLANE_ENABLE (1 << 31)

Definition at line 635 of file psb_intel_reg.h.

#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)

Definition at line 282 of file psb_intel_reg.h.

#define DISPPLANE_15_16BPP (0x4 << 26)

Definition at line 641 of file psb_intel_reg.h.

#define DISPPLANE_16BPP (0x5 << 26)

Definition at line 642 of file psb_intel_reg.h.

#define DISPPLANE_32BPP (0x7 << 26)

Definition at line 644 of file psb_intel_reg.h.

#define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26)

Definition at line 643 of file psb_intel_reg.h.

#define DISPPLANE_8BPP (0x2 << 26)

Definition at line 640 of file psb_intel_reg.h.

#define DISPPLANE_ALPHA_TRANS_DISABLE 0

Definition at line 659 of file psb_intel_reg.h.

#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)

Definition at line 658 of file psb_intel_reg.h.

#define DISPPLANE_BOTTOM (4)

Definition at line 662 of file psb_intel_reg.h.

#define DISPPLANE_GAMMA_DISABLE 0

Definition at line 638 of file psb_intel_reg.h.

#define DISPPLANE_GAMMA_ENABLE (1 << 30)

Definition at line 637 of file psb_intel_reg.h.

#define DISPPLANE_LINE_DOUBLE (1 << 20)

Definition at line 653 of file psb_intel_reg.h.

#define DISPPLANE_NO_LINE_DOUBLE 0

Definition at line 654 of file psb_intel_reg.h.

#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)

Definition at line 639 of file psb_intel_reg.h.

#define DISPPLANE_SEL_PIPE_A 0

Definition at line 649 of file psb_intel_reg.h.

#define DISPPLANE_SEL_PIPE_B (1 << 24)

Definition at line 650 of file psb_intel_reg.h.

#define DISPPLANE_SEL_PIPE_MASK (1 << 24)

Definition at line 647 of file psb_intel_reg.h.

#define DISPPLANE_SEL_PIPE_POS 24

Definition at line 648 of file psb_intel_reg.h.

#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0

Definition at line 660 of file psb_intel_reg.h.

#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)

Definition at line 661 of file psb_intel_reg.h.

#define DISPPLANE_SRC_KEY_DISABLE 0

Definition at line 652 of file psb_intel_reg.h.

#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)

Definition at line 651 of file psb_intel_reg.h.

#define DISPPLANE_STEREO_DISABLE 0

Definition at line 646 of file psb_intel_reg.h.

#define DISPPLANE_STEREO_ENABLE (1 << 25)

Definition at line 645 of file psb_intel_reg.h.

#define DISPPLANE_STEREO_POLARITY_FIRST 0

Definition at line 655 of file psb_intel_reg.h.

#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)

Definition at line 656 of file psb_intel_reg.h.

#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)

Turn on the audio link

Definition at line 1427 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)

Definition at line 1469 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)

Definition at line 1474 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0

Definition at line 1475 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)

Definition at line 1472 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_DONE (1 << 30)

Definition at line 1456 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)

Definition at line 1457 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)

Definition at line 1470 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)

Definition at line 1465 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20

Definition at line 1466 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)

Definition at line 1467 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16

Definition at line 1468 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)

Definition at line 1473 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)

Definition at line 1464 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)

Definition at line 1455 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)

Definition at line 1471 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)

Definition at line 1462 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)

Definition at line 1459 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)

Definition at line 1460 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)

Definition at line 1461 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)

Definition at line 1458 of file psb_intel_reg.h.

#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)

Definition at line 1463 of file psb_intel_reg.h.

#define DP_B 0x64100

Definition at line 1372 of file psb_intel_reg.h.

#define DP_C 0x64200

Definition at line 1373 of file psb_intel_reg.h.

#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)

sends the clock on lane 15 of the PEG for debug

Definition at line 1418 of file psb_intel_reg.h.

#define DP_COLOR_RANGE_16_235 (1 << 8)

limit RGB values to avoid confusing TVs

Definition at line 1424 of file psb_intel_reg.h.

#define DP_DETECTED (1 << 2)

A fantasy

Definition at line 1434 of file psb_intel_reg.h.

#define DP_ENHANCED_FRAMING (1 << 18)

Definition at line 1412 of file psb_intel_reg.h.

#define DP_LINK_TRAIN_MASK (3 << 28)

Definition at line 1384 of file psb_intel_reg.h.

#define DP_LINK_TRAIN_OFF (3 << 28)

Definition at line 1383 of file psb_intel_reg.h.

#define DP_LINK_TRAIN_PAT_1 (0 << 28)

Definition at line 1380 of file psb_intel_reg.h.

#define DP_LINK_TRAIN_PAT_2 (1 << 28)

Definition at line 1381 of file psb_intel_reg.h.

#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)

Definition at line 1382 of file psb_intel_reg.h.

#define DP_LINK_TRAIN_SHIFT 28

Definition at line 1385 of file psb_intel_reg.h.

#define DP_PIPE_MASK (1 << 30)

Definition at line 1377 of file psb_intel_reg.h.

#define DP_PIPEB_SELECT (1 << 30)

Definition at line 1376 of file psb_intel_reg.h.

#define DP_PORT_EN (1 << 31)

Definition at line 1375 of file psb_intel_reg.h.

#define DP_PORT_REVERSAL (1 << 15)

locked once port is enabled

Definition at line 1415 of file psb_intel_reg.h.

#define DP_PORT_WIDTH_1 (0 << 19)

Definition at line 1406 of file psb_intel_reg.h.

#define DP_PORT_WIDTH_2 (1 << 19)

Definition at line 1407 of file psb_intel_reg.h.

#define DP_PORT_WIDTH_4 (3 << 19)

Definition at line 1408 of file psb_intel_reg.h.

#define DP_PORT_WIDTH_MASK (7 << 19)

Definition at line 1409 of file psb_intel_reg.h.

#define DP_PRE_EMPHASIS_0 (0 << 22)

Definition at line 1398 of file psb_intel_reg.h.

#define DP_PRE_EMPHASIS_3_5 (1 << 22)

Definition at line 1399 of file psb_intel_reg.h.

#define DP_PRE_EMPHASIS_6 (2 << 22)

Definition at line 1400 of file psb_intel_reg.h.

#define DP_PRE_EMPHASIS_9_5 (3 << 22)

Definition at line 1401 of file psb_intel_reg.h.

#define DP_PRE_EMPHASIS_MASK (7 << 22)

Definition at line 1402 of file psb_intel_reg.h.

#define DP_PRE_EMPHASIS_SHIFT 22

Definition at line 1403 of file psb_intel_reg.h.

#define DP_SCRAMBLING_DISABLE (1 << 12)

Definition at line 1420 of file psb_intel_reg.h.

#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)

Definition at line 1421 of file psb_intel_reg.h.

#define DP_SYNC_HS_HIGH (1 << 3)

Definition at line 1431 of file psb_intel_reg.h.

#define DP_SYNC_VS_HIGH (1 << 4)

vs and hs sync polarity

Definition at line 1430 of file psb_intel_reg.h.

#define DP_VOLTAGE_0_4 (0 << 25)

Definition at line 1388 of file psb_intel_reg.h.

#define DP_VOLTAGE_0_6 (1 << 25)

Definition at line 1389 of file psb_intel_reg.h.

#define DP_VOLTAGE_0_8 (2 << 25)

Definition at line 1390 of file psb_intel_reg.h.

#define DP_VOLTAGE_1_2 (3 << 25)

Definition at line 1391 of file psb_intel_reg.h.

#define DP_VOLTAGE_MASK (7 << 25)

Definition at line 1392 of file psb_intel_reg.h.

#define DP_VOLTAGE_SHIFT 25

Definition at line 1393 of file psb_intel_reg.h.

#define DPB_AUX_CH_CTL 0x64110

The aux channel provides a way to talk to the signal sink for DDC etc. Max packet size supported is 20 bytes in each direction, hence the 5 fixed data registers

Definition at line 1441 of file psb_intel_reg.h.

#define DPB_AUX_CH_DATA1 0x64114

Definition at line 1442 of file psb_intel_reg.h.

#define DPB_AUX_CH_DATA2 0x64118

Definition at line 1443 of file psb_intel_reg.h.

#define DPB_AUX_CH_DATA3 0x6411c

Definition at line 1444 of file psb_intel_reg.h.

#define DPB_AUX_CH_DATA4 0x64120

Definition at line 1445 of file psb_intel_reg.h.

#define DPB_AUX_CH_DATA5 0x64124

Definition at line 1446 of file psb_intel_reg.h.

#define DPC_AUX_CH_CTL 0x64210

Definition at line 1448 of file psb_intel_reg.h.

#define DPC_AUX_CH_DATA1 0x64214

Definition at line 1449 of file psb_intel_reg.h.

#define DPC_AUX_CH_DATA2 0x64218

Definition at line 1450 of file psb_intel_reg.h.

#define DPC_AUX_CH_DATA3 0x6421c

Definition at line 1451 of file psb_intel_reg.h.

#define DPC_AUX_CH_DATA4 0x64220

Definition at line 1452 of file psb_intel_reg.h.

#define DPC_AUX_CH_DATA5 0x64224

Definition at line 1453 of file psb_intel_reg.h.

#define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)

Definition at line 1305 of file psb_intel_reg.h.

#define DPHY_PARAM_REG 0xb080

Definition at line 992 of file psb_intel_reg.h.

#define DPI_BACK_LIGHT_OFF (1 << 5)

Definition at line 955 of file psb_intel_reg.h.

#define DPI_BACK_LIGHT_OFF_DATA 0x17

Definition at line 959 of file psb_intel_reg.h.

#define DPI_BACK_LIGHT_ON (1 << 4)

Definition at line 954 of file psb_intel_reg.h.

#define DPI_BACK_LIGHT_ON_DATA 0x07

Definition at line 958 of file psb_intel_reg.h.

#define DPI_CHANNEL_NUMBER_POS 0x03

Definition at line 911 of file psb_intel_reg.h.

#define DPI_COLOR_MODE_OFF (1 << 3)

Definition at line 953 of file psb_intel_reg.h.

#define DPI_COLOR_MODE_ON (1 << 2)

Definition at line 952 of file psb_intel_reg.h.

#define DPI_CONTROL_REG 0xb048

Definition at line 949 of file psb_intel_reg.h.

#define DPI_DATA_REG 0xb04c

Definition at line 957 of file psb_intel_reg.h.

#define DPI_FIFO_EMPTY (1 << 28)

Definition at line 989 of file psb_intel_reg.h.

#define DPI_FIFO_UNDER_RUN (1 << 20)

Definition at line 901 of file psb_intel_reg.h.

#define DPI_LP (1 << 6)

Definition at line 956 of file psb_intel_reg.h.

#define DPI_RESOLUTION_REG 0xb020

Definition at line 938 of file psb_intel_reg.h.

#define DPI_SHUT_DOWN (1 << 0)

Definition at line 950 of file psb_intel_reg.h.

#define DPI_TURN_ON (1 << 1)

Definition at line 951 of file psb_intel_reg.h.

#define DPIO_CFG 0x02110 /* cedarview */

Definition at line 1314 of file psb_intel_reg.h.

#define DPIO_CMN_RESET_N (1 << 0)

Definition at line 1319 of file psb_intel_reg.h.

#define DPIO_MODE_SELECT_0 (1 << 2)

Definition at line 1316 of file psb_intel_reg.h.

#define DPIO_MODE_SELECT_1 (1 << 3)

Definition at line 1315 of file psb_intel_reg.h.

#define DPIO_SFR_BYPASS (1 << 1)

Definition at line 1317 of file psb_intel_reg.h.

#define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)

Definition at line 1302 of file psb_intel_reg.h.

#define DPLL_A 0x06014

Definition at line 239 of file psb_intel_reg.h.

#define DPLL_A_MD 0x0601c

Definition at line 297 of file psb_intel_reg.h.

#define DPLL_B 0x06018

Definition at line 240 of file psb_intel_reg.h.

#define DPLL_B_MD 0x06020

Definition at line 299 of file psb_intel_reg.h.

#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */

Definition at line 248 of file psb_intel_reg.h.

#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */

Definition at line 249 of file psb_intel_reg.h.

#define DPLL_DVO_HIGH_SPEED (1 << 30)

Definition at line 242 of file psb_intel_reg.h.

#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000

Definition at line 260 of file psb_intel_reg.h.

#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000

Definition at line 265 of file psb_intel_reg.h.

#define DPLL_FPA01_P1_POST_DIV_SHIFT 16

Definition at line 266 of file psb_intel_reg.h.

#define DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000 /* i915 */

Definition at line 253 of file psb_intel_reg.h.

#define DPLL_LOCK (1 << 15) /* CDV */

Definition at line 254 of file psb_intel_reg.h.

#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000

Definition at line 305 of file psb_intel_reg.h.

#define DPLL_MD_UDI_DIVIDER_SHIFT 24

Definition at line 306 of file psb_intel_reg.h.

#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00

Definition at line 327 of file psb_intel_reg.h.

#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8

Definition at line 328 of file psb_intel_reg.h.

#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000

Definition at line 308 of file psb_intel_reg.h.

#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16

Definition at line 309 of file psb_intel_reg.h.

#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f

Definition at line 334 of file psb_intel_reg.h.

#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0

Definition at line 335 of file psb_intel_reg.h.

#define DPLL_MODE_MASK (3 << 26)

Definition at line 247 of file psb_intel_reg.h.

#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */

Definition at line 252 of file psb_intel_reg.h.

#define DPLL_SYNCLOCK_ENABLE (1 << 29)

Definition at line 243 of file psb_intel_reg.h.

#define DPLL_TEST 0x606c

Definition at line 337 of file psb_intel_reg.h.

#define DPLL_VCO_ENABLE (1 << 31)

Definition at line 241 of file psb_intel_reg.h.

#define DPLL_VGA_MODE_DIS (1 << 28)

Definition at line 244 of file psb_intel_reg.h.

#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)

Definition at line 347 of file psb_intel_reg.h.

#define DPLLA_MODE_LVDS (2 << 26) /* mrst */

Definition at line 806 of file psb_intel_reg.h.

#define DPLLA_TEST_M_BYPASS (1 << 2)

Definition at line 346 of file psb_intel_reg.h.

#define DPLLA_TEST_N_BYPASS (1 << 3)

Definition at line 345 of file psb_intel_reg.h.

#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)

Definition at line 344 of file psb_intel_reg.h.

#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */

Definition at line 250 of file psb_intel_reg.h.

#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */

Definition at line 251 of file psb_intel_reg.h.

#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */

Definition at line 245 of file psb_intel_reg.h.

#define DPLLB_MODE_LVDS (2 << 26) /* i915 */

Definition at line 246 of file psb_intel_reg.h.

#define DPLLB_TEST_M_BYPASS (1 << 18)

Definition at line 343 of file psb_intel_reg.h.

#define DPLLB_TEST_N_BYPASS (1 << 19)

Definition at line 342 of file psb_intel_reg.h.

#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)

Definition at line 338 of file psb_intel_reg.h.

#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)

Definition at line 339 of file psb_intel_reg.h.

#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)

Definition at line 340 of file psb_intel_reg.h.

#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)

Definition at line 341 of file psb_intel_reg.h.

#define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)

Definition at line 1306 of file psb_intel_reg.h.

#define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)

Definition at line 1301 of file psb_intel_reg.h.

#define DPST_YUV_LUMA_MODE 0

Definition at line 562 of file psb_intel_reg.h.

#define DPUNIT_PIPEA_GATE_DISABLE (1 << 25)

Definition at line 1304 of file psb_intel_reg.h.

#define DPUNIT_PIPEB_GATE_DISABLE (1 << 30)

Definition at line 1303 of file psb_intel_reg.h.

#define DSI_FUNC_PRG_REG 0xb00c

Definition at line 910 of file psb_intel_reg.h.

#define DSP_FIFO_SR_WM_MASK 0xFF800000

Definition at line 614 of file psb_intel_reg.h.

#define DSP_FIFO_SR_WM_SHIFT 23

Definition at line 615 of file psb_intel_reg.h.

#define DSP_PLANE_A_FIFO_WM1_SHIFT 16

Definition at line 627 of file psb_intel_reg.h.

#define DSP_PLANE_B_FIFO_WM1_SHIFT 24

Definition at line 626 of file psb_intel_reg.h.

#define DSP_PLANE_C_FIFO_WM_MASK 0x7F

Definition at line 621 of file psb_intel_reg.h.

#define DSP_PLANE_C_FIFO_WM_SHIFT 0

Definition at line 622 of file psb_intel_reg.h.

#define DSPABASE 0x70184

Definition at line 664 of file psb_intel_reg.h.

#define DSPACNTR 0x70180

Definition at line 632 of file psb_intel_reg.h.

#define DSPAKEYMASK 0x70198

Definition at line 678 of file psb_intel_reg.h.

#define DSPAKEYVAL 0x70194

Definition at line 677 of file psb_intel_reg.h.

#define DSPALINOFF 0x70184

Definition at line 665 of file psb_intel_reg.h.

#define DSPAPOS 0x7018C /* reserved */

Definition at line 680 of file psb_intel_reg.h.

#define DSPARB 0x70030

Definition at line 612 of file psb_intel_reg.h.

#define DSPASIZE 0x70190

Definition at line 681 of file psb_intel_reg.h.

#define DSPASTRIDE 0x70188

Definition at line 666 of file psb_intel_reg.h.

#define DSPASURF 0x7019C

Definition at line 687 of file psb_intel_reg.h.

#define DSPATILEOFF 0x701A4

Definition at line 688 of file psb_intel_reg.h.

#define DSPBADDR DSPBBASE

Definition at line 670 of file psb_intel_reg.h.

#define DSPBBASE 0x71184

Definition at line 668 of file psb_intel_reg.h.

#define DSPBCNTR 0x71180

Definition at line 633 of file psb_intel_reg.h.

#define DSPBLINOFF 0X71184

Definition at line 669 of file psb_intel_reg.h.

#define DSPBPOS 0x7118C

Definition at line 682 of file psb_intel_reg.h.

#define DSPBSIZE 0x71190

Definition at line 683 of file psb_intel_reg.h.

#define DSPBSTRIDE 0x71188

Definition at line 671 of file psb_intel_reg.h.

#define DSPBSURF 0x7119C

Definition at line 690 of file psb_intel_reg.h.

#define DSPBTILEOFF 0x711A4

Definition at line 691 of file psb_intel_reg.h.

#define DSPCBASE 0x72184

Definition at line 673 of file psb_intel_reg.h.

#define DSPCCNTR 0x72180

Definition at line 634 of file psb_intel_reg.h.

#define DSPCHICKENBIT 0x70400

Definition at line 631 of file psb_intel_reg.h.

#define DSPCKEYMAXVAL 0x721A0

Definition at line 695 of file psb_intel_reg.h.

#define DSPCKEYMINVAL 0x72194

Definition at line 696 of file psb_intel_reg.h.

#define DSPCKEYMSK 0x72198

Definition at line 697 of file psb_intel_reg.h.

#define DSPCLINOFF 0x72184

Definition at line 674 of file psb_intel_reg.h.

#define DSPCLK_GATE_D 0x6200

Definition at line 1299 of file psb_intel_reg.h.

#define DSPCPOS 0x7218C

Definition at line 684 of file psb_intel_reg.h.

#define DSPCSIZE 0x72190

Definition at line 685 of file psb_intel_reg.h.

#define DSPCSTRIDE 0x72188

Definition at line 675 of file psb_intel_reg.h.

#define DSPCSURF 0x7219C

Definition at line 693 of file psb_intel_reg.h.

#define DSPCTILEOFF 0x721A4

Definition at line 694 of file psb_intel_reg.h.

#define DSPFW1 0x70034

Definition at line 613 of file psb_intel_reg.h.

#define DSPFW2 0x70038

Definition at line 618 of file psb_intel_reg.h.

#define DSPFW3 0x7003c

Definition at line 623 of file psb_intel_reg.h.

#define DSPFW4 0x70050

Definition at line 624 of file psb_intel_reg.h.

#define DSPFW5 0x70054

Definition at line 625 of file psb_intel_reg.h.

#define DSPFW6 0x70058

Definition at line 630 of file psb_intel_reg.h.

#define EDP_BLC_ENABLE (1 << 2)

Definition at line 185 of file psb_intel_reg.h.

#define EDP_FORCE_VDD (1 << 3)

Definition at line 184 of file psb_intel_reg.h.

#define ENABLE_CLOCK_STOPPING (1 << 1)

Definition at line 965 of file psb_intel_reg.h.

#define enter_idle_mode 0x39

Definition at line 1159 of file psb_intel_reg.h.

#define enter_invert_mode 0x21

Definition at line 1076 of file psb_intel_reg.h.

#define enter_normal_mode 0x13

Definition at line 1065 of file psb_intel_reg.h.

#define enter_partial_mode 0x12

Definition at line 1059 of file psb_intel_reg.h.

#define enter_sleep_mode 0x10

Definition at line 1047 of file psb_intel_reg.h.

#define ENTERING_ULPS (2 << 1)

Definition at line 877 of file psb_intel_reg.h.

#define EOT_DISABLE_REG 0xb05c

Definition at line 964 of file psb_intel_reg.h.

#define exit_idle_mode 0x38

Definition at line 1155 of file psb_intel_reg.h.

#define exit_invert_mode 0x20

Definition at line 1070 of file psb_intel_reg.h.

#define exit_sleep_mode 0x11

Definition at line 1054 of file psb_intel_reg.h.

#define EXIT_ULPS_DEV_READY 0x3

Definition at line 875 of file psb_intel_reg.h.

#define EXITING_ULPS (1 << 1)

Definition at line 878 of file psb_intel_reg.h.

#define FMT_DBI_POS 0x0A

Definition at line 914 of file psb_intel_reg.h.

#define FMT_DPI_POS 0x07

Definition at line 913 of file psb_intel_reg.h.

#define FP_M1_DIV_MASK 0x00003f00

Definition at line 372 of file psb_intel_reg.h.

#define FP_M1_DIV_SHIFT 8

Definition at line 373 of file psb_intel_reg.h.

#define FP_M2_DIV_MASK 0x0000003f

Definition at line 374 of file psb_intel_reg.h.

#define FP_M2_DIV_SHIFT 0

Definition at line 375 of file psb_intel_reg.h.

#define FP_N_DIV_MASK 0x003f0000

Definition at line 370 of file psb_intel_reg.h.

#define FP_N_DIV_SHIFT 16

Definition at line 371 of file psb_intel_reg.h.

#define FPA0 0x06040

Definition at line 366 of file psb_intel_reg.h.

#define FPA1 0x06044

Definition at line 367 of file psb_intel_reg.h.

#define FPB0 0x06048

Definition at line 368 of file psb_intel_reg.h.

#define FPB1 0x0604c

Definition at line 369 of file psb_intel_reg.h.

#define FW_BLC_SELF 0x20e0

Definition at line 609 of file psb_intel_reg.h.

#define FW_BLC_SELF_EN (1<<15)

Definition at line 610 of file psb_intel_reg.h.

#define GAMMA_AUTO (1 << 0)

Definition at line 1241 of file psb_intel_reg.h.

#define GEN_FB_TIME_OUT 2000

Definition at line 1271 of file psb_intel_reg.h.

#define GEN_FIFO_STAT_REG 0xb074

Definition at line 975 of file psb_intel_reg.h.

#define GEN_LONG_WRITE 0x29 /* generic long write */

Definition at line 1211 of file psb_intel_reg.h.

#define GEN_READ_0 0x04 /* generic read, no parameters */

Definition at line 1208 of file psb_intel_reg.h.

#define GEN_READ_1 0x14 /* generic read, 1 parameters */

Definition at line 1209 of file psb_intel_reg.h.

#define GEN_READ_2 0x24 /* generic read, 2 parameters */

Definition at line 1210 of file psb_intel_reg.h.

#define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */

Definition at line 1205 of file psb_intel_reg.h.

#define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */

Definition at line 1206 of file psb_intel_reg.h.

#define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */

Definition at line 1207 of file psb_intel_reg.h.

#define get_address_mode 0x0b

Definition at line 1025 of file psb_intel_reg.h.

#define get_diagnostic_result 0x0f

Definition at line 1042 of file psb_intel_reg.h.

#define get_display_mode 0x0d

Definition at line 1034 of file psb_intel_reg.h.

#define GET_FIELD	(	word,
		field
	)	(((word) & field ## _MASK) >> field ## _SHIFT)

Definition at line 1281 of file psb_intel_reg.h.

#define get_pixel_format 0x0c

Definition at line 1029 of file psb_intel_reg.h.

#define get_power_mode 0x0a

Definition at line 1021 of file psb_intel_reg.h.

#define get_scanline 0x45

Definition at line 1194 of file psb_intel_reg.h.

#define get_signal_mode 0x0e

Definition at line 1038 of file psb_intel_reg.h.

#define GMBUS0 0x5100 /* clock/port select */

Definition at line 46 of file psb_intel_reg.h.

#define GMBUS1 0x5104 /* command/status */

Definition at line 61 of file psb_intel_reg.h.

#define GMBUS2 0x5108 /* status */

Definition at line 74 of file psb_intel_reg.h.

#define GMBUS3 0x510c /* data buffer bytes 3-0 */

Definition at line 82 of file psb_intel_reg.h.

#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */

Definition at line 83 of file psb_intel_reg.h.

#define GMBUS5 0x5120 /* byte index */

Definition at line 89 of file psb_intel_reg.h.

#define GMBUS_2BYTE_INDEX_EN (1<<31)

Definition at line 90 of file psb_intel_reg.h.

#define GMBUS_ACTIVE (1<<9)

Definition at line 81 of file psb_intel_reg.h.

#define GMBUS_BYTE_COUNT_SHIFT 16

Definition at line 69 of file psb_intel_reg.h.

#define GMBUS_CYCLE_INDEX (2<<25)

Definition at line 67 of file psb_intel_reg.h.

#define GMBUS_CYCLE_NONE (0<<25)

Definition at line 65 of file psb_intel_reg.h.

#define GMBUS_CYCLE_STOP (4<<25)

Definition at line 68 of file psb_intel_reg.h.

#define GMBUS_CYCLE_WAIT (1<<25)

Definition at line 66 of file psb_intel_reg.h.

#define GMBUS_ENT (1<<29) /* enable timeout */

Definition at line 64 of file psb_intel_reg.h.

#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */

Definition at line 51 of file psb_intel_reg.h.

#define GMBUS_HW_RDY (1<<11)

Definition at line 79 of file psb_intel_reg.h.

#define GMBUS_HW_RDY_EN (1<<0)

Definition at line 88 of file psb_intel_reg.h.

#define GMBUS_HW_WAIT_EN (1<<1)

Definition at line 87 of file psb_intel_reg.h.

#define GMBUS_HW_WAIT_PHASE (1<<14)

Definition at line 76 of file psb_intel_reg.h.

#define GMBUS_IDLE_EN (1<<2)

Definition at line 86 of file psb_intel_reg.h.

#define GMBUS_INT (1<<12)

Definition at line 78 of file psb_intel_reg.h.

#define GMBUS_INUSE (1<<15)

Definition at line 75 of file psb_intel_reg.h.

#define GMBUS_NAK_EN (1<<3)

Definition at line 85 of file psb_intel_reg.h.

#define GMBUS_NUM_PORTS 8

Definition at line 60 of file psb_intel_reg.h.

#define GMBUS_PORT_DISABLED 0

Definition at line 52 of file psb_intel_reg.h.

#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */

Definition at line 57 of file psb_intel_reg.h.

#define GMBUS_PORT_DPC 4 /* HDMIC */

Definition at line 56 of file psb_intel_reg.h.

#define GMBUS_PORT_DPD 7 /* HDMID */

Definition at line 59 of file psb_intel_reg.h.

#define GMBUS_PORT_PANEL 3

Definition at line 55 of file psb_intel_reg.h.

#define GMBUS_PORT_SSC 1

Definition at line 53 of file psb_intel_reg.h.

#define GMBUS_PORT_VGADDC 2

Definition at line 54 of file psb_intel_reg.h.

#define GMBUS_RATE_100KHZ (0<<8)

Definition at line 47 of file psb_intel_reg.h.

#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */

Definition at line 50 of file psb_intel_reg.h.

#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */

Definition at line 49 of file psb_intel_reg.h.

#define GMBUS_RATE_50KHZ (1<<8)

Definition at line 48 of file psb_intel_reg.h.

#define GMBUS_SATOER (1<<10)

Definition at line 80 of file psb_intel_reg.h.

#define GMBUS_SLAVE_ADDR_SHIFT 1

Definition at line 71 of file psb_intel_reg.h.

#define GMBUS_SLAVE_INDEX_SHIFT 8

Definition at line 70 of file psb_intel_reg.h.

#define GMBUS_SLAVE_READ (1<<0)

Definition at line 72 of file psb_intel_reg.h.

#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)

Definition at line 84 of file psb_intel_reg.h.

#define GMBUS_SLAVE_WRITE (0<<0)

Definition at line 73 of file psb_intel_reg.h.

#define GMBUS_STALL_TIMEOUT (1<<13)

Definition at line 77 of file psb_intel_reg.h.

#define GMBUS_SW_CLR_INT (1<<31)

Definition at line 62 of file psb_intel_reg.h.

#define GMBUS_SW_RDY (1<<30)

Definition at line 63 of file psb_intel_reg.h.

#define GPIO_CLOCK_DIR_IN (0 << 1)

Definition at line 32 of file psb_intel_reg.h.

#define GPIO_CLOCK_DIR_MASK (1 << 0)

Definition at line 31 of file psb_intel_reg.h.

#define GPIO_CLOCK_DIR_OUT (1 << 1)

Definition at line 33 of file psb_intel_reg.h.

#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)

Definition at line 37 of file psb_intel_reg.h.

#define GPIO_CLOCK_VAL_IN (1 << 4)

Definition at line 36 of file psb_intel_reg.h.

#define GPIO_CLOCK_VAL_MASK (1 << 2)

Definition at line 34 of file psb_intel_reg.h.

#define GPIO_CLOCK_VAL_OUT (1 << 3)

Definition at line 35 of file psb_intel_reg.h.

#define GPIO_DATA_DIR_IN (0 << 9)

Definition at line 39 of file psb_intel_reg.h.

#define GPIO_DATA_DIR_MASK (1 << 8)

Definition at line 38 of file psb_intel_reg.h.

#define GPIO_DATA_DIR_OUT (1 << 9)

Definition at line 40 of file psb_intel_reg.h.

#define GPIO_DATA_PULLUP_DISABLE (1 << 13)

Definition at line 44 of file psb_intel_reg.h.

#define GPIO_DATA_VAL_IN (1 << 12)

Definition at line 43 of file psb_intel_reg.h.

#define GPIO_DATA_VAL_MASK (1 << 10)

Definition at line 41 of file psb_intel_reg.h.

#define GPIO_DATA_VAL_OUT (1 << 11)

Definition at line 42 of file psb_intel_reg.h.

#define GPIOA 0x5010

Definition at line 23 of file psb_intel_reg.h.

#define GPIOB 0x5014

Definition at line 24 of file psb_intel_reg.h.

#define GPIOC 0x5018

Definition at line 25 of file psb_intel_reg.h.

#define GPIOD 0x501c

Definition at line 26 of file psb_intel_reg.h.

#define GPIOE 0x5020

Definition at line 27 of file psb_intel_reg.h.

#define GPIOF 0x5024

Definition at line 28 of file psb_intel_reg.h.

#define GPIOG 0x5028

Definition at line 29 of file psb_intel_reg.h.

#define GPIOH 0x502c

Definition at line 30 of file psb_intel_reg.h.

#define HBLANK_A 0x60004

Definition at line 133 of file psb_intel_reg.h.

#define HBLANK_B 0x61004

Definition at line 143 of file psb_intel_reg.h.

#define HBLANK_C 0x62004

Definition at line 153 of file psb_intel_reg.h.

#define HDMI_PHY_POWER_DOWN 0x7f

Definition at line 820 of file psb_intel_reg.h.

#define HDMIB_CONTROL 0x61140

Definition at line 821 of file psb_intel_reg.h.

#define HDMIB_HDCP_PORT (1 << 5)

Definition at line 825 of file psb_intel_reg.h.

#define HDMIB_HOTPLUG_INT_EN (1 << 29)

Definition at line 378 of file psb_intel_reg.h.

#define HDMIB_NULL_PACKET (1 << 9)

Definition at line 824 of file psb_intel_reg.h.

#define HDMIB_PIPE_B_SELECT (1 << 30)

Definition at line 823 of file psb_intel_reg.h.

#define HDMIB_PORT_EN (1 << 31)

Definition at line 822 of file psb_intel_reg.h.

#define HDMIC_HOTPLUG_INT_EN (1 << 28)

Definition at line 379 of file psb_intel_reg.h.

#define HDMID_HOTPLUG_INT_EN (1 << 27)

Definition at line 380 of file psb_intel_reg.h.

#define HDMIPHYMISCCTL 0x61134

Definition at line 819 of file psb_intel_reg.h.

#define HIGH_CONTENTION (1 << 18)

Definition at line 899 of file psb_intel_reg.h.

#define HIGH_LOW_SWITCH_COUNT_REG 0xb044

Definition at line 948 of file psb_intel_reg.h.

#define HISTOGRAM_BIN_DATA 0X61264

Definition at line 550 of file psb_intel_reg.h.

#define HISTOGRAM_INT_CONTROL 0x61268

Definition at line 549 of file psb_intel_reg.h.

#define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30)

Definition at line 561 of file psb_intel_reg.h.

#define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31)

Definition at line 554 of file psb_intel_reg.h.

#define HISTOGRAM_LOGIC_CONTROL 0x61260

Definition at line 551 of file psb_intel_reg.h.

#define HISTOGRAM_LOGIC_ENABLE (1UL << 31)

Definition at line 555 of file psb_intel_reg.h.

#define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034

Definition at line 944 of file psb_intel_reg.h.

#define HORIZ_AUTO_SCALE (1 << 5)

Definition at line 230 of file psb_intel_reg.h.

#define HORIZ_BACK_PORCH_COUNT_REG 0xb02C

Definition at line 942 of file psb_intel_reg.h.

#define HORIZ_FRONT_PORCH_COUNT_REG 0xb030

Definition at line 943 of file psb_intel_reg.h.

#define HORIZ_INTERP_BILINEAR (1 << 6)

Definition at line 228 of file psb_intel_reg.h.

#define HORIZ_INTERP_DISABLE (0 << 6)

Definition at line 227 of file psb_intel_reg.h.

#define HORIZ_INTERP_MASK (3 << 6)

Definition at line 229 of file psb_intel_reg.h.

#define HORIZ_SYNC_PAD_COUNT_REG 0xb028

Definition at line 941 of file psb_intel_reg.h.

#define HS_CTRL_FIFO_EMPTY (1 << 18)

Definition at line 984 of file psb_intel_reg.h.

#define HS_CTRL_FIFO_FULL (1 << 16)

Definition at line 982 of file psb_intel_reg.h.

#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)

Definition at line 983 of file psb_intel_reg.h.

#define HS_DATA_FIFO_EMPTY (1 << 2)

Definition at line 978 of file psb_intel_reg.h.

#define HS_DATA_FIFO_FULL (1 << 0)

Definition at line 976 of file psb_intel_reg.h.

#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)

Definition at line 977 of file psb_intel_reg.h.

#define HS_GEN_CTRL_REG 0xb070

Definition at line 970 of file psb_intel_reg.h.

#define HS_GEN_DATA_REG 0xb068

Definition at line 968 of file psb_intel_reg.h.

#define HS_GENERIC_WR_FIFO_FULL (1 << 27)

Definition at line 906 of file psb_intel_reg.h.

#define HS_LS_DBI_ENABLE_REG 0xb078

Definition at line 990 of file psb_intel_reg.h.

#define HS_TX_TIMEOUT (1 << 21)

Definition at line 902 of file psb_intel_reg.h.

#define HS_TX_TIMEOUT_REG 0xb010

Definition at line 934 of file psb_intel_reg.h.

#define HSYNC_A 0x60008

Definition at line 134 of file psb_intel_reg.h.

#define HSYNC_B 0x61008

Definition at line 144 of file psb_intel_reg.h.

#define HSYNC_C 0x62008

Definition at line 154 of file psb_intel_reg.h.

#define HTOTAL_A 0x60000

Definition at line 132 of file psb_intel_reg.h.

#define HTOTAL_B 0x61000

Definition at line 142 of file psb_intel_reg.h.

#define HTOTAL_C 0x62000

Definition at line 152 of file psb_intel_reg.h.

#define I855_CLOCK_100_133 (2 << 0)

Definition at line 128 of file psb_intel_reg.h.

#define I855_CLOCK_100_200 (1 << 0)

Definition at line 127 of file psb_intel_reg.h.

#define I855_CLOCK_133_200 (0 << 0)

Definition at line 126 of file psb_intel_reg.h.

#define I855_CLOCK_166_250 (3 << 0)

Definition at line 129 of file psb_intel_reg.h.

#define I855_CLOCK_CONTROL_MASK (3 << 0)

Definition at line 125 of file psb_intel_reg.h.

#define I855_HPLLCC 0xc0

Definition at line 124 of file psb_intel_reg.h.

#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)

Definition at line 120 of file psb_intel_reg.h.

#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)

Definition at line 121 of file psb_intel_reg.h.

#define I915_DISPLAY_CLOCK_MASK (7 << 4)

Definition at line 122 of file psb_intel_reg.h.

#define I915_GCFGC 0xf0

Definition at line 118 of file psb_intel_reg.h.

#define I915_LOW_FREQUENCY_ENABLE (1 << 7)

Definition at line 119 of file psb_intel_reg.h.

#define I965_PIPECONF_ACTIVE (1 << 30)

Definition at line 494 of file psb_intel_reg.h.

#define IER 0x020a0

Definition at line 794 of file psb_intel_reg.h.

#define IIR 0x020a4

Definition at line 795 of file psb_intel_reg.h.

#define IMR 0x020a8

Definition at line 796 of file psb_intel_reg.h.

#define INIT_COUNT_REG 0xb050

Definition at line 960 of file psb_intel_reg.h.

#define INTR_EN_REG 0xb008

Definition at line 909 of file psb_intel_reg.h.

#define INTR_STAT_REG 0xb004

Definition at line 881 of file psb_intel_reg.h.

#define ISR 0x020ac

Definition at line 797 of file psb_intel_reg.h.

#define LANE_PLL_ENABLE (0x3 << 20)

Definition at line 1369 of file psb_intel_reg.h.

#define LANE_PLL_MASK (0x7 << 20)

Definition at line 1368 of file psb_intel_reg.h.

#define LANE_PLL_PIPE ( p ) (((p) == 0) ? (1 << 21) : (0 << 21))

Definition at line 1370 of file psb_intel_reg.h.

#define LOW_CONTENTION (1 << 19)

Definition at line 900 of file psb_intel_reg.h.

#define LP_BYTECLK_REG 0xb060

Definition at line 966 of file psb_intel_reg.h.

#define LP_CTRL_FIFO_EMPTY (1 << 26)

Definition at line 987 of file psb_intel_reg.h.

#define LP_CTRL_FIFO_FULL (1 << 24)

Definition at line 985 of file psb_intel_reg.h.

#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)

Definition at line 986 of file psb_intel_reg.h.

#define LP_DATA_FIFO_EMPTY (1 << 10)

Definition at line 981 of file psb_intel_reg.h.

#define LP_DATA_FIFO_FULL (1 << 8)

Definition at line 979 of file psb_intel_reg.h.

#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)

Definition at line 980 of file psb_intel_reg.h.

#define LP_GEN_CTRL_REG 0xb06C

Definition at line 969 of file psb_intel_reg.h.

#define LP_GEN_DATA_REG 0xb064

Definition at line 967 of file psb_intel_reg.h.

#define LP_GENERIC_WR_FIFO_FULL (1 << 28)

Definition at line 907 of file psb_intel_reg.h.

#define LP_OUTPUT_HOLD (1 << 16)

Definition at line 874 of file psb_intel_reg.h.

#define LP_OUTPUT_HOLD_RELEASE 0x810000

Definition at line 876 of file psb_intel_reg.h.

#define LP_RX_TIMEOUT (1 << 22)

Definition at line 903 of file psb_intel_reg.h.

#define LP_RX_TIMEOUT_REG 0xb014

Definition at line 935 of file psb_intel_reg.h.

#define LRGB_666_FMT

Value:

0x03    /* RGB LOOSELY PACKED
                             * 666 FORMAT
                             */

Definition at line 920 of file psb_intel_reg.h.

#define LVDS 0x61180

Definition at line 446 of file psb_intel_reg.h.

#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)

Definition at line 463 of file psb_intel_reg.h.

#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)

Definition at line 462 of file psb_intel_reg.h.

#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)

Definition at line 464 of file psb_intel_reg.h.

#define LVDS_A3_POWER_DOWN (0 << 6)

Definition at line 471 of file psb_intel_reg.h.

#define LVDS_A3_POWER_MASK (3 << 6)

Definition at line 470 of file psb_intel_reg.h.

#define LVDS_A3_POWER_UP (3 << 6)

Definition at line 472 of file psb_intel_reg.h.

#define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6)

Definition at line 830 of file psb_intel_reg.h.

#define LVDS_B0B3_POWER_DOWN (0 << 2)

Definition at line 486 of file psb_intel_reg.h.

#define LVDS_B0B3_POWER_MASK (3 << 2)

Definition at line 485 of file psb_intel_reg.h.

#define LVDS_B0B3_POWER_UP (3 << 2)

Definition at line 487 of file psb_intel_reg.h.

#define LVDS_BORDER_EN (1 << 15)

Definition at line 456 of file psb_intel_reg.h.

#define LVDS_CLKB_POWER_DOWN (0 << 4)

Definition at line 478 of file psb_intel_reg.h.

#define LVDS_CLKB_POWER_MASK (3 << 4)

Definition at line 477 of file psb_intel_reg.h.

#define LVDS_CLKB_POWER_UP (3 << 4)

Definition at line 479 of file psb_intel_reg.h.

#define LVDS_PIPEB_SELECT (1 << 30)

Definition at line 453 of file psb_intel_reg.h.

#define LVDS_PORT_EN (1 << 31)

Definition at line 451 of file psb_intel_reg.h.

#define LVDSPP_OFF 0x6120c

Definition at line 192 of file psb_intel_reg.h.

#define LVDSPP_ON 0x61208

Definition at line 191 of file psb_intel_reg.h.

#define MAX_RET_PAK_REG 0xb054

Definition at line 961 of file psb_intel_reg.h.

#define MCS_COMMANDS_POS 0x8

Definition at line 972 of file psb_intel_reg.h.

#define MCS_LONG_WRITE 0x39 /* MCS long write */

Definition at line 1215 of file psb_intel_reg.h.

#define MCS_PARAMETER_POS 0x10

Definition at line 974 of file psb_intel_reg.h.

#define MCS_READ 0x06 /* MCS read, no parameters */

Definition at line 1214 of file psb_intel_reg.h.

#define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */

Definition at line 1212 of file psb_intel_reg.h.

#define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */

Definition at line 1213 of file psb_intel_reg.h.

#define MCURSOR_GAMMA_ENABLE (1 << 26)

Definition at line 777 of file psb_intel_reg.h.

#define MDFLD_DPLL_B 0x0f018

Definition at line 803 of file psb_intel_reg.h.

#define MDFLD_DPLL_DIV0 0x0f048

Definition at line 812 of file psb_intel_reg.h.

#define MDFLD_DPLL_DIV1 0x0f04c

Definition at line 813 of file psb_intel_reg.h.

#define MDFLD_DSPCBASE 0x7219c

Definition at line 862 of file psb_intel_reg.h.

#define MDFLD_INPUT_REF_SEL (1 << 14)

Definition at line 804 of file psb_intel_reg.h.

#define MDFLD_P1_MASK (0x1FF << 17)

Definition at line 809 of file psb_intel_reg.h.

#define MDFLD_PLL_LATCHEN (1 << 28)

Definition at line 807 of file psb_intel_reg.h.

#define MDFLD_PWR_GATE_EN (1 << 30)

Definition at line 808 of file psb_intel_reg.h.

#define MDFLD_VCO_SEL (1 << 16)

Definition at line 805 of file psb_intel_reg.h.

#define MIPI 0x61190

Definition at line 832 of file psb_intel_reg.h.

#define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1))

Definition at line 1000 of file psb_intel_reg.h.

#define MIPI_BORDER_EN (1 << 15)

Definition at line 838 of file psb_intel_reg.h.

#define MIPI_C 0x62190

Definition at line 833 of file psb_intel_reg.h.

#define MIPI_COMMAND_ADDRESS_REG 0xb110

Definition at line 1003 of file psb_intel_reg.h.

#define MIPI_COMMAND_LENGTH_REG 0xb114

Definition at line 1004 of file psb_intel_reg.h.

#define MIPI_CONTROL_REG 0xb104

Definition at line 999 of file psb_intel_reg.h.

#define MIPI_DATA_ADDRESS_REG 0xb108

Definition at line 1001 of file psb_intel_reg.h.

#define MIPI_DATA_LENGTH_REG 0xb10C

Definition at line 1002 of file psb_intel_reg.h.

#define MIPI_PORT_EN (1 << 31)

Definition at line 834 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG0 0xb118

Definition at line 1005 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG1 0xb11C

Definition at line 1006 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG2 0xb120

Definition at line 1007 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG3 0xb124

Definition at line 1008 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG4 0xb128

Definition at line 1009 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG5 0xb12C

Definition at line 1010 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG6 0xb130

Definition at line 1011 of file psb_intel_reg.h.

#define MIPI_READ_DATA_RETURN_REG7 0xb134

Definition at line 1012 of file psb_intel_reg.h.

#define MIPI_READ_DATA_VALID_REG 0xb138

Definition at line 1013 of file psb_intel_reg.h.

#define MIPI_TE_COUNT 0x61194

Definition at line 843 of file psb_intel_reg.h.

#define MIPIA_2LANE_MIPIC_2LANE 0x2

Definition at line 840 of file psb_intel_reg.h.

#define MIPIA_3LANE_MIPIC_1LANE 0x1

Definition at line 839 of file psb_intel_reg.h.

#define MIPIC_REG_OFFSET 0x800

Definition at line 871 of file psb_intel_reg.h.

#define MOVING_IMAGE 0x03

Definition at line 1224 of file psb_intel_reg.h.

#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)

Definition at line 854 of file psb_intel_reg.h.

#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16)

Definition at line 853 of file psb_intel_reg.h.

#define MRST_DPLL_A 0x0f014

Definition at line 802 of file psb_intel_reg.h.

#define MRST_DSPABASE 0x7019c

Definition at line 860 of file psb_intel_reg.h.

#define MRST_DSPBBASE 0x7119c

Definition at line 861 of file psb_intel_reg.h.

#define MRST_FPA0 0x0f040

Definition at line 810 of file psb_intel_reg.h.

#define MRST_FPA1 0x0f044

Definition at line 811 of file psb_intel_reg.h.

#define MRST_PANEL_24_DOT_1_FORMAT (1 << 24)

Definition at line 829 of file psb_intel_reg.h.

#define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25)

Definition at line 828 of file psb_intel_reg.h.

#define MRST_PERF_MODE 0x020f4

Definition at line 814 of file psb_intel_reg.h.

#define NON_BURST_MODE_SYNC_EVENTS

Value:

0x02    /* Non Burst Mode
                         * with Sync events
                         */

Definition at line 1261 of file psb_intel_reg.h.

#define NON_BURST_MODE_SYNC_PULSE

Value:

0x01    /* Non Burst Mode
                         * with Sync Pulse
                         */

Definition at line 1260 of file psb_intel_reg.h.

#define OV_C_OFFSET 0x08000

Definition at line 707 of file psb_intel_reg.h.

#define OV_DOVASTA 0x30008

Definition at line 709 of file psb_intel_reg.h.

#define OV_OGAMC0 0x30024

Definition at line 719 of file psb_intel_reg.h.

#define OV_OGAMC1 0x30020

Definition at line 718 of file psb_intel_reg.h.

#define OV_OGAMC2 0x3001C

Definition at line 717 of file psb_intel_reg.h.

#define OV_OGAMC3 0x30018

Definition at line 716 of file psb_intel_reg.h.

#define OV_OGAMC4 0x30014

Definition at line 715 of file psb_intel_reg.h.

#define OV_OGAMC5 0x30010

Definition at line 714 of file psb_intel_reg.h.

#define OV_OVADD 0x30000

Definition at line 708 of file psb_intel_reg.h.

#define OV_PIPE_A 0

Definition at line 712 of file psb_intel_reg.h.

#define OV_PIPE_C 1

Definition at line 713 of file psb_intel_reg.h.

#define OV_PIPE_SELECT ((1 << 6)|(1 << 7))

Definition at line 710 of file psb_intel_reg.h.

#define OV_PIPE_SELECT_POS 6

Definition at line 711 of file psb_intel_reg.h.

#define OVC_DOVCSTA 0x38008

Definition at line 721 of file psb_intel_reg.h.

#define OVC_OGAMC0 0x38024

Definition at line 727 of file psb_intel_reg.h.

#define OVC_OGAMC1 0x38020

Definition at line 726 of file psb_intel_reg.h.

#define OVC_OGAMC2 0x3801C

Definition at line 725 of file psb_intel_reg.h.

#define OVC_OGAMC3 0x38018

Definition at line 724 of file psb_intel_reg.h.

#define OVC_OGAMC4 0x38014

Definition at line 723 of file psb_intel_reg.h.

#define OVC_OGAMC5 0x38010

Definition at line 722 of file psb_intel_reg.h.

#define OVC_OVADD 0x38000

Definition at line 720 of file psb_intel_reg.h.

#define PALETTE_A 0x0a000

Definition at line 768 of file psb_intel_reg.h.

#define PALETTE_B 0x0a800

Definition at line 769 of file psb_intel_reg.h.

#define PALETTE_C 0x0ac00

Definition at line 770 of file psb_intel_reg.h.

#define PANEL_8TO6_DITHER_ENABLE (1 << 3)

Definition at line 231 of file psb_intel_reg.h.

#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)

Definition at line 208 of file psb_intel_reg.h.

#define PANEL_LIGHT_OFF_DELAY_SHIFT 0

Definition at line 209 of file psb_intel_reg.h.

#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)

Definition at line 202 of file psb_intel_reg.h.

#define PANEL_LIGHT_ON_DELAY_SHIFT 0

Definition at line 203 of file psb_intel_reg.h.

#define PANEL_PORT_SELECT_EDP (1 << 30)

Definition at line 199 of file psb_intel_reg.h.

#define PANEL_PORT_SELECT_LVDS (0 << 30)

Definition at line 198 of file psb_intel_reg.h.

#define PANEL_PORT_SELECT_MASK (3 << 30)

Definition at line 197 of file psb_intel_reg.h.

#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)

Definition at line 214 of file psb_intel_reg.h.

#define PANEL_POWER_CYCLE_DELAY_SHIFT 0

Definition at line 215 of file psb_intel_reg.h.

#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)

Definition at line 206 of file psb_intel_reg.h.

#define PANEL_POWER_DOWN_DELAY_SHIFT 16

Definition at line 207 of file psb_intel_reg.h.

#define PANEL_POWER_OFF (0 << 0)

Definition at line 187 of file psb_intel_reg.h.

#define PANEL_POWER_ON (1 << 0)

Definition at line 188 of file psb_intel_reg.h.

#define PANEL_POWER_RESET (1 << 1)

Definition at line 186 of file psb_intel_reg.h.

#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)

Definition at line 200 of file psb_intel_reg.h.

#define PANEL_POWER_UP_DELAY_SHIFT 16

Definition at line 201 of file psb_intel_reg.h.

#define PANEL_UNLOCK_MASK (0xffff << 16)

Definition at line 183 of file psb_intel_reg.h.

#define PANEL_UNLOCK_REGS (0xabcd << 16)

Definition at line 182 of file psb_intel_reg.h.

#define PASS_FROM_SPHY_TO_AFE (1 << 16)

Definition at line 837 of file psb_intel_reg.h.

#define PFIT_AUTO_RATIOS 0x61238

Definition at line 237 of file psb_intel_reg.h.

#define PFIT_CONTROL 0x61230

Definition at line 217 of file psb_intel_reg.h.

#define PFIT_ENABLE (1 << 31)

Definition at line 218 of file psb_intel_reg.h.

#define PFIT_HORIZ_SCALE_MASK 0x0000fff0

Definition at line 235 of file psb_intel_reg.h.

#define PFIT_PGM_RATIOS 0x61234

Definition at line 233 of file psb_intel_reg.h.

#define PFIT_PIPE_MASK (3 << 29)

Definition at line 219 of file psb_intel_reg.h.

#define PFIT_PIPE_SELECT (3 << 29)

Definition at line 849 of file psb_intel_reg.h.

#define PFIT_PIPE_SELECT_SHIFT (29)

Definition at line 850 of file psb_intel_reg.h.

#define PFIT_PIPE_SHIFT 29

Definition at line 220 of file psb_intel_reg.h.

#define PFIT_SCALING_MODE_LETTERBOX (3 << 26)

Definition at line 222 of file psb_intel_reg.h.

#define PFIT_SCALING_MODE_PILLARBOX (1 << 27)

Definition at line 221 of file psb_intel_reg.h.

#define PFIT_VERT_SCALE_MASK 0xfff00000

Definition at line 234 of file psb_intel_reg.h.

#define PIPE_10BPC (1 << 5)

Definition at line 1530 of file psb_intel_reg.h.

#define PIPE_6BPC (2 << 5)

Definition at line 1531 of file psb_intel_reg.h.

#define PIPE_8BPC (0 << 5)

Definition at line 1529 of file psb_intel_reg.h.

#define PIPE_BPC_MASK (7 << 5)

Definition at line 1528 of file psb_intel_reg.h.

#define PIPE_DP_LINK_M ( pipe ) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)

Definition at line 1525 of file psb_intel_reg.h.

#define PIPE_DP_LINK_N ( pipe ) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)

Definition at line 1526 of file psb_intel_reg.h.

#define PIPE_DPST_EVENT_ENABLE (1UL << 23)

Definition at line 540 of file psb_intel_reg.h.

#define PIPE_DPST_EVENT_STATUS (1UL << 7)

Definition at line 531 of file psb_intel_reg.h.

#define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))

Definition at line 547 of file psb_intel_reg.h.

#define PIPE_FIFO_UNDERRUN (1UL << 31)

Definition at line 544 of file psb_intel_reg.h.

#define PIPE_FRAME_HIGH_MASK 0x0000ffff

Definition at line 602 of file psb_intel_reg.h.

#define PIPE_FRAME_HIGH_SHIFT 0

Definition at line 603 of file psb_intel_reg.h.

#define PIPE_FRAME_LOW_MASK 0xff000000

Definition at line 604 of file psb_intel_reg.h.

#define PIPE_FRAME_LOW_SHIFT 24

Definition at line 605 of file psb_intel_reg.h.

#define PIPE_GMCH_DATA_M ( pipe ) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)

Definition at line 1523 of file psb_intel_reg.h.

#define PIPE_GMCH_DATA_M_MASK (0xffffff)

Definition at line 1498 of file psb_intel_reg.h.

#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)

Definition at line 1495 of file psb_intel_reg.h.

#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25

Definition at line 1496 of file psb_intel_reg.h.

#define PIPE_GMCH_DATA_N ( pipe ) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)

Definition at line 1524 of file psb_intel_reg.h.

#define PIPE_GMCH_DATA_N_MASK (0xffffff)

Definition at line 1502 of file psb_intel_reg.h.

#define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27)

Definition at line 543 of file psb_intel_reg.h.

#define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11)

Definition at line 535 of file psb_intel_reg.h.

#define PIPE_HDMI_AUDIO_INT_MASK

Value:

(PIPE_HDMI_AUDIO_UNDERRUN | \

PIPE_HDMI_AUDIO_BUFFER_DONE)

Definition at line 545 of file psb_intel_reg.h.

#define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26)

Definition at line 542 of file psb_intel_reg.h.

#define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10)

Definition at line 534 of file psb_intel_reg.h.

#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)

Definition at line 553 of file psb_intel_reg.h.

#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)

Definition at line 539 of file psb_intel_reg.h.

#define PIPE_PIXEL_MASK 0x00ffffff

Definition at line 606 of file psb_intel_reg.h.

#define PIPE_PIXEL_SHIFT 0

Definition at line 607 of file psb_intel_reg.h.

#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)

Definition at line 537 of file psb_intel_reg.h.

#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)

Definition at line 527 of file psb_intel_reg.h.

#define PIPE_TE_ENABLE (1UL << 22)

Definition at line 538 of file psb_intel_reg.h.

#define PIPE_TE_STATUS (1UL << 6)

Definition at line 530 of file psb_intel_reg.h.

#define PIPE_VBLANK_CLEAR (1 << 1)

Definition at line 528 of file psb_intel_reg.h.

#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)

Definition at line 536 of file psb_intel_reg.h.

#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)

Definition at line 526 of file psb_intel_reg.h.

#define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17))

Definition at line 548 of file psb_intel_reg.h.

#define PIPE_VBLANK_STATUS (1 << 1)

Definition at line 529 of file psb_intel_reg.h.

#define PIPE_VSYNC_CLEAR (1UL << 9)

Definition at line 532 of file psb_intel_reg.h.

#define PIPE_VSYNC_ENABL (1UL << 25)

Definition at line 541 of file psb_intel_reg.h.

#define PIPE_VSYNC_STATUS (1UL << 9)

Definition at line 533 of file psb_intel_reg.h.

#define PIPEA_DP_LINK_M_MASK (0xffffff)

Definition at line 1517 of file psb_intel_reg.h.

#define PIPEA_DP_LINK_N_MASK (0xffffff)

Definition at line 1521 of file psb_intel_reg.h.

#define PIPEACONF 0x70008

Definition at line 489 of file psb_intel_reg.h.

#define PIPEACONF_DISABLE 0

Definition at line 491 of file psb_intel_reg.h.

#define PIPEACONF_DOUBLE_WIDE (1 << 30)

Definition at line 492 of file psb_intel_reg.h.

#define PIPEACONF_DSR (1 << 26)

Definition at line 498 of file psb_intel_reg.h.

#define PIPEACONF_ENABLE (1 << 31)

Definition at line 490 of file psb_intel_reg.h.

#define PIPEACONF_GAMMA (1 << 24)

Definition at line 502 of file psb_intel_reg.h.

#define PIPEACONF_PALETTE 0

Definition at line 500 of file psb_intel_reg.h.

#define PIPEACONF_PIPE_LOCKED (1 << 25)

Definition at line 499 of file psb_intel_reg.h.

#define PIPEACONF_PIPE_STATE (1 << 30)

Definition at line 857 of file psb_intel_reg.h.

#define PIPEACONF_PIPE_UNLOCKED 0

Definition at line 497 of file psb_intel_reg.h.

#define PIPEACONF_SINGLE_WIDE 0

Definition at line 496 of file psb_intel_reg.h.

#define PIPEAFRAMEHIGH 0x70040

Definition at line 596 of file psb_intel_reg.h.

#define PIPEAFRAMEPIXEL 0x70044

Definition at line 597 of file psb_intel_reg.h.

#define PIPEASRC 0x6001c

Definition at line 138 of file psb_intel_reg.h.

#define PIPEASTAT 0x70024

Definition at line 523 of file psb_intel_reg.h.

#define PIPEBCONF 0x71008

Definition at line 509 of file psb_intel_reg.h.

#define PIPEBCONF_DISABLE 0

Definition at line 513 of file psb_intel_reg.h.

#define PIPEBCONF_DISABLE 0

Definition at line 513 of file psb_intel_reg.h.

#define PIPEBCONF_DOUBLE_WIDE (1 << 30)

Definition at line 512 of file psb_intel_reg.h.

#define PIPEBCONF_ENABLE (1 << 31)

Definition at line 510 of file psb_intel_reg.h.

#define PIPEBCONF_GAMMA (1 << 24)

Definition at line 514 of file psb_intel_reg.h.

#define PIPEBCONF_PALETTE 0

Definition at line 515 of file psb_intel_reg.h.

#define PIPEBFRAMEHIGH 0x71040

Definition at line 598 of file psb_intel_reg.h.

#define PIPEBFRAMEPIXEL 0x71044

Definition at line 599 of file psb_intel_reg.h.

#define PIPEBGCMAXBLUE 0x71018

Definition at line 521 of file psb_intel_reg.h.

#define PIPEBGCMAXGREEN 0x71014

Definition at line 520 of file psb_intel_reg.h.

#define PIPEBGCMAXRED 0x71010

Definition at line 519 of file psb_intel_reg.h.

#define PIPEBSRC 0x6101c

Definition at line 148 of file psb_intel_reg.h.

#define PIPEBSTAT 0x71024

Definition at line 524 of file psb_intel_reg.h.

#define PIPECCONF 0x72008

Definition at line 517 of file psb_intel_reg.h.

#define PIPECFRAMEHIGH 0x72040

Definition at line 600 of file psb_intel_reg.h.

#define PIPECFRAMEPIXEL 0x72044

Definition at line 601 of file psb_intel_reg.h.

#define PIPECONF_ACTIVE (1 << 30)

Definition at line 493 of file psb_intel_reg.h.

#define PIPECONF_CURSOR_OFF (1 << 18)

Definition at line 507 of file psb_intel_reg.h.

#define PIPECONF_DSIPLL_LOCK (1 << 29)

Definition at line 495 of file psb_intel_reg.h.

#define PIPECONF_FORCE_BORDER (1 << 25)

Definition at line 501 of file psb_intel_reg.h.

#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)

Definition at line 505 of file psb_intel_reg.h.

#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)

Definition at line 504 of file psb_intel_reg.h.

#define PIPECONF_PLANE_OFF (1 << 19)

Definition at line 506 of file psb_intel_reg.h.

#define PIPECONF_PROGRESSIVE (0 << 21)

Definition at line 503 of file psb_intel_reg.h.

#define PIPECSRC 0x6201c

Definition at line 158 of file psb_intel_reg.h.

#define PIPECSTAT 0x72024

Definition at line 525 of file psb_intel_reg.h.

#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)

Definition at line 281 of file psb_intel_reg.h.

#define PLL_LOAD_PULSE_PHASE_SHIFT 9

Definition at line 274 of file psb_intel_reg.h.

#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */

Definition at line 268 of file psb_intel_reg.h.

#define PLL_P2_DIVIDE_BY_4

Value:

(1 << 23) /* i830, required

* in DVO non-gang */

Definition at line 267 of file psb_intel_reg.h.

#define PLL_REF_INPUT_DREFCLK (0 << 13)

Definition at line 269 of file psb_intel_reg.h.

#define PLL_REF_INPUT_MASK (3 << 13)

Definition at line 273 of file psb_intel_reg.h.

#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */

Definition at line 270 of file psb_intel_reg.h.

#define PLL_REF_INPUT_TVCLKINBC

Value:

(2 << 13) /* SDVO

* TVCLKIN */

Definition at line 271 of file psb_intel_reg.h.

#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)

Definition at line 272 of file psb_intel_reg.h.

#define PORT_HOTPLUG_EN 0x61110

Definition at line 377 of file psb_intel_reg.h.

#define PORT_HOTPLUG_STAT 0x61114

Definition at line 401 of file psb_intel_reg.h.

#define POWER_DOWN_ON_RESET (1 << 1)

Definition at line 846 of file psb_intel_reg.h.

#define POWER_TARGET_ON (1 << 0)

Definition at line 181 of file psb_intel_reg.h.

#define PP_CONTROL 0x61204

Definition at line 180 of file psb_intel_reg.h.

#define PP_CYCLE 0x61210

Definition at line 193 of file psb_intel_reg.h.

#define PP_CYCLE_DELAY_ACTIVE (1 << 27)

Definition at line 176 of file psb_intel_reg.h.

#define PP_DIVISOR 0x61210 /* Cedartrail */

Definition at line 211 of file psb_intel_reg.h.

#define PP_OFF_DELAYS 0x6120c /* Cedartrail */

Definition at line 205 of file psb_intel_reg.h.

#define PP_ON (1 << 31)

Definition at line 163 of file psb_intel_reg.h.

#define PP_ON_DELAYS 0x61208 /* Cedartrail */

Definition at line 196 of file psb_intel_reg.h.

#define PP_READY (1 << 30)

Definition at line 171 of file psb_intel_reg.h.

#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)

Definition at line 212 of file psb_intel_reg.h.

#define PP_REFERENCE_DIVIDER_SHIFT 8

Definition at line 213 of file psb_intel_reg.h.

#define PP_SEQUENCE_MASK 0x30000000

Definition at line 175 of file psb_intel_reg.h.

#define PP_SEQUENCE_NONE (0 << 28)

Definition at line 172 of file psb_intel_reg.h.

#define PP_SEQUENCE_OFF (2 << 28)

Definition at line 174 of file psb_intel_reg.h.

#define PP_SEQUENCE_ON (1 << 28)

Definition at line 173 of file psb_intel_reg.h.

#define PP_SEQUENCE_STATE_MASK 0x0000000f

Definition at line 178 of file psb_intel_reg.h.

#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)

Definition at line 177 of file psb_intel_reg.h.

#define PP_STATUS 0x61200

Definition at line 162 of file psb_intel_reg.h.

#define PSB_LANE0 0x120

Definition at line 1363 of file psb_intel_reg.h.

#define PSB_LANE1 0x220

Definition at line 1364 of file psb_intel_reg.h.

#define PSB_LANE2 0x2320

Definition at line 1365 of file psb_intel_reg.h.

#define PSB_LANE3 0x2420

Definition at line 1366 of file psb_intel_reg.h.

#define PSB_MASK	(	high,
		low
	)	(((1<<((high)-(low)+1))-1)<<(low))

Definition at line 1279 of file psb_intel_reg.h.

#define PWM_CONTROL_LOGIC 0x61250

Definition at line 552 of file psb_intel_reg.h.

#define PWM_ENABLE (1 << 31)

Definition at line 94 of file psb_intel_reg.h.

#define PWM_LEGACY_MODE (1 << 30)

Definition at line 95 of file psb_intel_reg.h.

#define PWM_LOGIC_ENABLE (1UL << 31)

Definition at line 556 of file psb_intel_reg.h.

#define PWM_PHASEIN_ENABLE (1UL << 25)

Definition at line 557 of file psb_intel_reg.h.

#define PWM_PHASEIN_INC 0x0000001f

Definition at line 560 of file psb_intel_reg.h.

#define PWM_PHASEIN_INT_ENABLE (1UL << 24)

Definition at line 558 of file psb_intel_reg.h.

#define PWM_PHASEIN_VB_COUNT 0x00001f00

Definition at line 559 of file psb_intel_reg.h.

#define PWM_PIPE_B (1 << 29)

Definition at line 96 of file psb_intel_reg.h.

#define pwr_mode_data 0x74

Definition at line 1255 of file psb_intel_reg.h.

#define pxl_fmt_data 0x77

Definition at line 1254 of file psb_intel_reg.h.

#define RAMCLK_GATE_D 0x6210

Definition at line 1308 of file psb_intel_reg.h.

#define REF_CLK_CORE (0 << 13)

Definition at line 1342 of file psb_intel_reg.h.

#define REF_CLK_DPLL (1 << 13)

Definition at line 1343 of file psb_intel_reg.h.

#define REF_CLK_DPLLA (2 << 13)

Definition at line 1344 of file psb_intel_reg.h.

#define REF_CLK_MASK (0x3 << 13)

Definition at line 1341 of file psb_intel_reg.h.

#define RES_V_POS 0x10

Definition at line 939 of file psb_intel_reg.h.

#define RGB_565_FMT 0x01 /* RGB 565 FORMAT */

Definition at line 918 of file psb_intel_reg.h.

#define RGB_666_FMT 0x02 /* RGB 666 FORMAT */

Definition at line 919 of file psb_intel_reg.h.

#define RGB_888_FMT 0x04 /* RGB 888 FORMAT */

Definition at line 921 of file psb_intel_reg.h.

#define RX_CHECKSUM_ERROR (1 << 9)

Definition at line 890 of file psb_intel_reg.h.

#define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10)

Definition at line 891 of file psb_intel_reg.h.

#define RX_DSI_VC_ID_INVALID (1 << 11)

Definition at line 892 of file psb_intel_reg.h.

#define RX_ECC_MULTI_BIT_ERROR (1 << 8)

Definition at line 889 of file psb_intel_reg.h.

#define RX_ECC_SINGLE_BIT_ERROR (1 << 7)

Definition at line 888 of file psb_intel_reg.h.

#define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3)

Definition at line 884 of file psb_intel_reg.h.

#define RX_FALSE_CONTROL_ERROR (1 << 6)

Definition at line 887 of file psb_intel_reg.h.

#define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5)

Definition at line 886 of file psb_intel_reg.h.

#define RX_LP_TX_SYNC_ERROR (1 << 4)

Definition at line 885 of file psb_intel_reg.h.

#define RX_SOT_ERROR (1 << 0)

Definition at line 882 of file psb_intel_reg.h.

#define RX_SOT_SYNC_ERROR (1 << 1)

Definition at line 883 of file psb_intel_reg.h.

#define SB_ADDR 0x02108 /* cedarview */

Definition at line 1313 of file psb_intel_reg.h.

#define SB_BUSY (1 << 0)

Definition at line 1297 of file psb_intel_reg.h.

#define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4)

Definition at line 1295 of file psb_intel_reg.h.

#define SB_BYTE_ENABLE_SHIFT 4

Definition at line 1296 of file psb_intel_reg.h.

#define SB_DATA 0x02104 /* cedarview */

Definition at line 1311 of file psb_intel_reg.h.

#define SB_DEST_DPLL 0x88

Definition at line 1294 of file psb_intel_reg.h.

#define SB_DEST_MASK PSB_MASK(15, 8)

Definition at line 1292 of file psb_intel_reg.h.

#define SB_DEST_SHIFT 8

Definition at line 1293 of file psb_intel_reg.h.

#define SB_M ( pipe ) _PIPE(pipe, _SB_M_A, _SB_M_B)

Definition at line 1324 of file psb_intel_reg.h.

#define SB_M_DIVIDER_MASK (0xFF << 24)

Definition at line 1325 of file psb_intel_reg.h.

#define SB_M_DIVIDER_SHIFT 24

Definition at line 1326 of file psb_intel_reg.h.

#define SB_N_CB_TUNE_MASK PSB_MASK(25, 24)

Definition at line 1335 of file psb_intel_reg.h.

#define SB_N_CB_TUNE_SHIFT 24

Definition at line 1336 of file psb_intel_reg.h.

#define SB_N_DIVIDER_MASK PSB_MASK(29, 26)

Definition at line 1333 of file psb_intel_reg.h.

#define SB_N_DIVIDER_SHIFT 26

Definition at line 1334 of file psb_intel_reg.h.

#define SB_N_VCO ( pipe ) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)

Definition at line 1330 of file psb_intel_reg.h.

#define SB_N_VCO_SEL_MASK PSB_MASK(31, 30)

Definition at line 1331 of file psb_intel_reg.h.

#define SB_N_VCO_SEL_SHIFT 30

Definition at line 1332 of file psb_intel_reg.h.

#define SB_OPCODE_MASK PSB_MASK(31, 16)

Definition at line 1288 of file psb_intel_reg.h.

#define SB_OPCODE_READ 0

Definition at line 1290 of file psb_intel_reg.h.

#define SB_OPCODE_SHIFT 16

Definition at line 1289 of file psb_intel_reg.h.

#define SB_OPCODE_WRITE 1

Definition at line 1291 of file psb_intel_reg.h.

#define SB_P ( pipe ) _PIPE(pipe, _SB_P_A, _SB_P_B)

Definition at line 1353 of file psb_intel_reg.h.

#define SB_P1_DIVIDER_MASK PSB_MASK(15, 12)

Definition at line 1360 of file psb_intel_reg.h.

#define SB_P1_DIVIDER_SHIFT 12

Definition at line 1361 of file psb_intel_reg.h.

#define SB_P2_10 0 /* HDMI, DP, DAC */

Definition at line 1356 of file psb_intel_reg.h.

#define SB_P2_14 2 /* LVDS single */

Definition at line 1358 of file psb_intel_reg.h.

#define SB_P2_5 1 /* DAC */

Definition at line 1357 of file psb_intel_reg.h.

#define SB_P2_7 3 /* LVDS double */

Definition at line 1359 of file psb_intel_reg.h.

#define SB_P2_DIVIDER_MASK PSB_MASK(31, 30)

Definition at line 1354 of file psb_intel_reg.h.

#define SB_P2_DIVIDER_SHIFT 30

Definition at line 1355 of file psb_intel_reg.h.

#define SB_PCKT 0x02100 /* cedarview */

Definition at line 1287 of file psb_intel_reg.h.

#define SB_REF_DPLLA 0x8010

Definition at line 1339 of file psb_intel_reg.h.

#define SB_REF_DPLLB 0x8030

Definition at line 1340 of file psb_intel_reg.h.

#define SB_REF_SFR ( pipe ) _PIPE(pipe, _SB_REF_A, _SB_REF_B)

Definition at line 1349 of file psb_intel_reg.h.

#define scanline_data1 0xff

Definition at line 1258 of file psb_intel_reg.h.

#define scanline_data2 0xff

Definition at line 1259 of file psb_intel_reg.h.

#define SDVO_AUDIO_ENABLE (1 << 6)

Definition at line 418 of file psb_intel_reg.h.

#define SDVO_BORDER_ENABLE (1 << 7)

Definition at line 433 of file psb_intel_reg.h.

#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)

Definition at line 431 of file psb_intel_reg.h.

#define SDVO_COLOR_RANGE_16_235 (1 << 8)

Definition at line 417 of file psb_intel_reg.h.

#define SDVO_DETECTED (1 << 2)

Definition at line 435 of file psb_intel_reg.h.

#define SDVO_ENABLE (1 << 31)

Definition at line 413 of file psb_intel_reg.h.

#define SDVO_INTERRUPT_ENABLE (1 << 26)

Definition at line 416 of file psb_intel_reg.h.

#define SDVO_MULTIPLIER_MASK 0x000000ff

Definition at line 289 of file psb_intel_reg.h.

#define SDVO_MULTIPLIER_SHIFT_HIRES 4

Definition at line 290 of file psb_intel_reg.h.

#define SDVO_MULTIPLIER_SHIFT_VGA 0

Definition at line 291 of file psb_intel_reg.h.

#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)

Definition at line 430 of file psb_intel_reg.h.

#define SDVO_PHASE_SELECT_MASK (15 << 19)

Definition at line 429 of file psb_intel_reg.h.

#define SDVO_PIPE_B_SELECT (1 << 30)

Definition at line 414 of file psb_intel_reg.h.

#define SDVO_PORT_MULTIPLY_MASK (7 << 23)

915G/GM SDVO pixel multiplier.

Programmed value is multiplier - 1, up to 5x.

DPLL_MD_UDI_MULTIPLIER_MASK

Definition at line 427 of file psb_intel_reg.h.

#define SDVO_PORT_MULTIPLY_SHIFT 23

Definition at line 428 of file psb_intel_reg.h.

#define SDVO_STALL_SELECT (1 << 29)

Definition at line 415 of file psb_intel_reg.h.

#define SDVOB 0x61140

Definition at line 411 of file psb_intel_reg.h.

#define SDVOB_HOTPLUG_INT_EN (1 << 26)

Definition at line 381 of file psb_intel_reg.h.

#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)

Definition at line 409 of file psb_intel_reg.h.

#define SDVOB_PCIE_CONCURRENCY (1 << 3)

Definition at line 434 of file psb_intel_reg.h.

#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))

Definition at line 437 of file psb_intel_reg.h.

#define SDVOC 0x61160

Definition at line 412 of file psb_intel_reg.h.

#define SDVOC_GANG_MODE (1 << 16)

Definition at line 432 of file psb_intel_reg.h.

#define SDVOC_HOTPLUG_INT_EN (1 << 25)

Definition at line 382 of file psb_intel_reg.h.

#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)

Definition at line 408 of file psb_intel_reg.h.

#define SDVOC_PRESERVE_MASK (1 << 17)

Definition at line 438 of file psb_intel_reg.h.

#define SEL_FLOPPED_HSTX (1 << 23)

Definition at line 836 of file psb_intel_reg.h.

#define set_address_mode 0x36

Definition at line 1140 of file psb_intel_reg.h.

#define set_column_address 0x2a

Definition at line 1099 of file psb_intel_reg.h.

#define set_display_off 0x28

Definition at line 1087 of file psb_intel_reg.h.

#define set_display_on 0x29

Definition at line 1093 of file psb_intel_reg.h.

#define SET_FIELD	(	value,
		field
	)	(((value) << field ## _SHIFT) & field ## _MASK)

Definition at line 1280 of file psb_intel_reg.h.

#define set_gamma_curve 0x26

Definition at line 1082 of file psb_intel_reg.h.

#define set_page_addr 0x2b

Definition at line 1106 of file psb_intel_reg.h.

#define set_partial_area 0x30

Definition at line 1119 of file psb_intel_reg.h.

#define set_pixel_format 0x3a

Definition at line 1166 of file psb_intel_reg.h.

#define set_scroll_area 0x33

Definition at line 1126 of file psb_intel_reg.h.

#define set_scroll_start 0x37

Definition at line 1146 of file psb_intel_reg.h.

#define set_tear_off 0x34

Definition at line 1130 of file psb_intel_reg.h.

#define set_tear_on 0x35

Definition at line 1135 of file psb_intel_reg.h.

#define set_tear_scanline 0x44

Definition at line 1189 of file psb_intel_reg.h.

#define sig_mode_data 0x00

Definition at line 1256 of file psb_intel_reg.h.

#define SKU_100 0x02

Definition at line 1274 of file psb_intel_reg.h.

#define SKU_100L 0x04

Definition at line 1275 of file psb_intel_reg.h.

#define SKU_83 0x01

Definition at line 1273 of file psb_intel_reg.h.

#define SKU_BYPASS 0x08

Definition at line 1276 of file psb_intel_reg.h.

#define soft_reset 0x01

Definition at line 1016 of file psb_intel_reg.h.

#define SPL_PKT_SENT (1 << 30)

Definition at line 908 of file psb_intel_reg.h.

#define STILL_IMAGE 0x02

Definition at line 1223 of file psb_intel_reg.h.

#define SWF0 0x71410

Definition at line 733 of file psb_intel_reg.h.

#define SWF00 0x70410

Definition at line 744 of file psb_intel_reg.h.

#define SWF01 0x70414

Definition at line 745 of file psb_intel_reg.h.

#define SWF02 0x70418

Definition at line 746 of file psb_intel_reg.h.

#define SWF03 0x7041c

Definition at line 747 of file psb_intel_reg.h.

#define SWF04 0x70420

Definition at line 748 of file psb_intel_reg.h.

#define SWF05 0x70424

Definition at line 749 of file psb_intel_reg.h.

#define SWF06 0x70428

Definition at line 750 of file psb_intel_reg.h.

#define SWF1 0x71414

Definition at line 734 of file psb_intel_reg.h.

#define SWF10 SWF0

Definition at line 752 of file psb_intel_reg.h.

#define SWF11 SWF1

Definition at line 753 of file psb_intel_reg.h.

#define SWF12 SWF2

Definition at line 754 of file psb_intel_reg.h.

#define SWF13 SWF3

Definition at line 755 of file psb_intel_reg.h.

#define SWF14 SWF4

Definition at line 756 of file psb_intel_reg.h.

#define SWF15 SWF5

Definition at line 757 of file psb_intel_reg.h.

#define SWF16 SWF6

Definition at line 758 of file psb_intel_reg.h.

#define SWF2 0x71418

Definition at line 735 of file psb_intel_reg.h.

#define SWF3 0x7141c

Definition at line 736 of file psb_intel_reg.h.

#define SWF30 0x72414

Definition at line 760 of file psb_intel_reg.h.

#define SWF31 0x72418

Definition at line 761 of file psb_intel_reg.h.

#define SWF32 0x7241c

Definition at line 762 of file psb_intel_reg.h.

#define SWF4 0x71420

Definition at line 737 of file psb_intel_reg.h.

#define SWF5 0x71424

Definition at line 738 of file psb_intel_reg.h.

#define SWF6 0x71428

Definition at line 739 of file psb_intel_reg.h.

#define TE_TRIGGER_DSI_PROTOCOL (1 << 2)

Definition at line 841 of file psb_intel_reg.h.

#define TE_TRIGGER_GPIO_PIN (1 << 3)

Definition at line 842 of file psb_intel_reg.h.

#define tmd_write_display_brightness 0x8c

Definition at line 1230 of file psb_intel_reg.h.

#define TURN_AROUND_ACK_TIMEOUT (1 << 23)

Definition at line 904 of file psb_intel_reg.h.

#define TURN_AROUND_TIMEOUT_REG 0xb018

Definition at line 936 of file psb_intel_reg.h.

#define TV_HOTPLUG_INT_EN (1 << 18)

Definition at line 383 of file psb_intel_reg.h.

#define TV_HOTPLUG_INT_STATUS (1 << 10)

Definition at line 403 of file psb_intel_reg.h.

#define TX_CHECKSUM_ERROR (1 << 15)

Definition at line 896 of file psb_intel_reg.h.

#define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16)

Definition at line 897 of file psb_intel_reg.h.

#define TX_DSI_VC_ID_INVALID (1 << 17)

Definition at line 898 of file psb_intel_reg.h.

#define TX_ECC_MULTI_BIT_ERROR (1 << 14)

Definition at line 895 of file psb_intel_reg.h.

#define TX_ECC_SINGLE_BIT_ERROR (1 << 13)

Definition at line 894 of file psb_intel_reg.h.

#define TX_FALSE_CONTROL_ERROR (1 << 12)

Definition at line 893 of file psb_intel_reg.h.

#define TXCLKESC_REG 0xb07c

Definition at line 991 of file psb_intel_reg.h.

#define UI_IMAGE 0x01

Definition at line 1222 of file psb_intel_reg.h.

#define ULPS_MASK (3 << 1)

Definition at line 879 of file psb_intel_reg.h.

#define VBLANK_A 0x60010

Definition at line 136 of file psb_intel_reg.h.

#define VBLANK_B 0x61010

Definition at line 146 of file psb_intel_reg.h.

#define VBLANK_C 0x62010

Definition at line 156 of file psb_intel_reg.h.

#define VERT_AUTO_SCALE (1 << 9)

Definition at line 226 of file psb_intel_reg.h.

#define VERT_BACK_PORCH_COUNT_REG 0xb03c

Definition at line 946 of file psb_intel_reg.h.

#define VERT_FRONT_PORCH_COUNT_REG 0xb040

Definition at line 947 of file psb_intel_reg.h.

#define VERT_INTERP_BILINEAR (1 << 10)

Definition at line 224 of file psb_intel_reg.h.

#define VERT_INTERP_DISABLE (0 << 10)

Definition at line 223 of file psb_intel_reg.h.

#define VERT_INTERP_MASK (3 << 10)

Definition at line 225 of file psb_intel_reg.h.

#define VERT_SYNC_PAD_COUNT_REG 0xb038

Definition at line 945 of file psb_intel_reg.h.

#define VGA_2X_MODE (1 << 30)

Definition at line 701 of file psb_intel_reg.h.

#define VGA_DISP_DISABLE (1 << 31)

Definition at line 700 of file psb_intel_reg.h.

#define VGA_PIPE_B_SELECT (1 << 29)

Definition at line 702 of file psb_intel_reg.h.

#define VGACNTRL 0x71400

Definition at line 699 of file psb_intel_reg.h.

#define VIDEO_FMT_REG 0xb058

Definition at line 962 of file psb_intel_reg.h.

#define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */

Definition at line 922 of file psb_intel_reg.h.

#define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */

Definition at line 923 of file psb_intel_reg.h.

#define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */

Definition at line 924 of file psb_intel_reg.h.

#define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */

Definition at line 925 of file psb_intel_reg.h.

#define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */

Definition at line 1300 of file psb_intel_reg.h.

#define VSYNC_A 0x60014

Definition at line 137 of file psb_intel_reg.h.

#define VSYNC_B 0x61014

Definition at line 147 of file psb_intel_reg.h.

#define VSYNC_C 0x62014

Definition at line 157 of file psb_intel_reg.h.

#define VSYNCSHIFT_A 0x60028

Definition at line 140 of file psb_intel_reg.h.

#define VSYNCSHIFT_B 0x61028

Definition at line 150 of file psb_intel_reg.h.

#define VSYNCSHIFT_C 0x62028

Definition at line 160 of file psb_intel_reg.h.

#define VTOTAL_A 0x6000c

Definition at line 135 of file psb_intel_reg.h.

#define VTOTAL_B 0x6100c

Definition at line 145 of file psb_intel_reg.h.

#define VTOTAL_C 0x6200c

Definition at line 155 of file psb_intel_reg.h.

#define WORD_COUNTS_POS 0x8

Definition at line 973 of file psb_intel_reg.h.

#define write_cabc_min_bright 0x5e

Definition at line 1227 of file psb_intel_reg.h.

#define write_ctrl_cabc 0x55

Definition at line 1221 of file psb_intel_reg.h.

#define write_ctrl_display 0x53

Definition at line 1220 of file psb_intel_reg.h.

#define write_display_brightness 0x51

Definition at line 1219 of file psb_intel_reg.h.

#define write_display_profile 0x50

Definition at line 1218 of file psb_intel_reg.h.

#define write_gamma_setting 0x58

Definition at line 1226 of file psb_intel_reg.h.

#define write_hysteresis 0x57

Definition at line 1225 of file psb_intel_reg.h.

#define write_kbbc_profile 0x60

Definition at line 1228 of file psb_intel_reg.h.

#define write_mem_cont 0x3c

Definition at line 1181 of file psb_intel_reg.h.

#define write_mem_start 0x2c

Definition at line 1113 of file psb_intel_reg.h.

Data Structures

Macros

Macro Definition Documentation