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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/pxa2xx_ssp.h>Go to the source code of this file.
Data Structures | |
| struct | pxa2xx_spi_master |
| struct | pxa2xx_spi_chip |
Macros | |
| #define | PXA2XX_CS_ASSERT (0x01) |
| #define | PXA2XX_CS_DEASSERT (0x02) |
| #define | DCSR(n) (n) |
| #define | DSADR(n) (n) |
| #define | DTADR(n) (n) |
| #define | DCMD(n) (n) |
| #define | DRCMR(n) (n) |
| #define | DCSR_RUN (1 << 31) /* Run Bit */ |
| #define | DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */ |
| #define | DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */ |
| #define | DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ |
| #define | DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ |
| #define | DCSR_ENDINTR (1 << 2) /* End Interrupt */ |
| #define | DCSR_STARTINTR (1 << 1) /* Start Interrupt */ |
| #define | DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */ |
| #define | DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */ |
| #define | DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ |
| #define | DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ |
| #define | DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ |
| #define | DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ |
| #define | DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ |
| #define | DCSR_EORINTR (1 << 9) /* The end of Receive */ |
| #define | DRCMR_MAPVLD (1 << 7) /* Map Valid */ |
| #define | DRCMR_CHLNUM 0x1f /* mask for Channel Number */ |
| #define | DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */ |
| #define | DDADR_STOP (1 << 0) /* Stop */ |
| #define | DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ |
| #define | DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ |
| #define | DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ |
| #define | DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ |
| #define | DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ |
| #define | DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ |
| #define | DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ |
| #define | DCMD_BURST8 (1 << 16) /* 8 byte burst */ |
| #define | DCMD_BURST16 (2 << 16) /* 16 byte burst */ |
| #define | DCMD_BURST32 (3 << 16) /* 32 byte burst */ |
| #define | DCMD_WIDTH1 (1 << 14) /* 1 byte width */ |
| #define | DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ |
| #define | DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ |
| #define | DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
Enumerations | |
| enum | pxa_dma_prio { DMA_PRIO_HIGH = 0, DMA_PRIO_MEDIUM = 1, DMA_PRIO_LOW = 2, DMA_PRIO_HIGH = 0, DMA_PRIO_MEDIUM = 1, DMA_PRIO_LOW = 2 } |
Definition at line 65 of file pxa2xx_spi.h.
| #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ |
Definition at line 99 of file pxa2xx_spi.h.
| #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ |
Definition at line 100 of file pxa2xx_spi.h.
| #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ |
Definition at line 98 of file pxa2xx_spi.h.
| #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ |
Definition at line 97 of file pxa2xx_spi.h.
| #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ |
Definition at line 96 of file pxa2xx_spi.h.
Definition at line 93 of file pxa2xx_spi.h.
Definition at line 94 of file pxa2xx_spi.h.
| #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ |
Definition at line 91 of file pxa2xx_spi.h.
| #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ |
Definition at line 92 of file pxa2xx_spi.h.
| #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
Definition at line 104 of file pxa2xx_spi.h.
| #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ |
Definition at line 95 of file pxa2xx_spi.h.
Definition at line 101 of file pxa2xx_spi.h.
Definition at line 102 of file pxa2xx_spi.h.
Definition at line 103 of file pxa2xx_spi.h.
Definition at line 62 of file pxa2xx_spi.h.
| #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */ |
Definition at line 75 of file pxa2xx_spi.h.
| #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ |
Definition at line 81 of file pxa2xx_spi.h.
Definition at line 82 of file pxa2xx_spi.h.
| #define DCSR_ENDINTR (1 << 2) /* End Interrupt */ |
Definition at line 73 of file pxa2xx_spi.h.
Definition at line 83 of file pxa2xx_spi.h.
| #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */ |
Definition at line 77 of file pxa2xx_spi.h.
| #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ |
Definition at line 78 of file pxa2xx_spi.h.
| #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ |
Definition at line 79 of file pxa2xx_spi.h.
| #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */ |
Definition at line 69 of file pxa2xx_spi.h.
Definition at line 71 of file pxa2xx_spi.h.
| #define DCSR_RUN (1 << 31) /* Run Bit */ |
Definition at line 68 of file pxa2xx_spi.h.
| #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ |
Definition at line 80 of file pxa2xx_spi.h.
| #define DCSR_STARTINTR (1 << 1) /* Start Interrupt */ |
Definition at line 74 of file pxa2xx_spi.h.
| #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */ |
Definition at line 70 of file pxa2xx_spi.h.
| #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ |
Definition at line 72 of file pxa2xx_spi.h.
| #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */ |
Definition at line 88 of file pxa2xx_spi.h.
| #define DDADR_STOP (1 << 0) /* Stop */ |
Definition at line 89 of file pxa2xx_spi.h.
Definition at line 66 of file pxa2xx_spi.h.
| #define DRCMR_CHLNUM 0x1f /* mask for Channel Number */ |
Definition at line 86 of file pxa2xx_spi.h.
| #define DRCMR_MAPVLD (1 << 7) /* Map Valid */ |
Definition at line 85 of file pxa2xx_spi.h.
Definition at line 63 of file pxa2xx_spi.h.
Definition at line 64 of file pxa2xx_spi.h.
| #define PXA2XX_CS_ASSERT (0x01) |
Definition at line 23 of file pxa2xx_spi.h.
| #define PXA2XX_CS_DEASSERT (0x02) |
Definition at line 24 of file pxa2xx_spi.h.
| enum pxa_dma_prio |
Definition at line 111 of file pxa2xx_spi.h.
1.8.2