#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/tlv.h>
#include <sound/info.h>
#include "ice1712.h"
#include "envy24ht.h"
#include <sound/ak4113.h>
#include "quartet.h"
Go to the source code of this file.
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| #define | AK4113_ADDR 0x26 /* S/PDIF receiver */ |
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| #define | AK4620_ADDR 0x02 /* ADC/DAC */ |
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| #define | GPIO_D0 (1<<0) |
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| #define | GPIO_D1_JACKDTC0 (1<<1) |
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| #define | GPIO_D2_JACKDTC1 (1<<2) |
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| #define | GPIO_D3 (1<<3) |
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| #define | GPIO_D4_SPI_CDTO (1<<4) |
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| #define | GPIO_D5_SPI_CCLK (1<<5) |
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| #define | GPIO_D6_CD (1<<6) |
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| #define | GPIO_D7_DD (1<<7) |
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| #define | GPIO_CPLD_CSN (1<<8) |
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| #define | GPIO_CPLD_RW (1<<9) |
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| #define | GPIO_SPI_CSN0 (1<<10) |
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| #define | GPIO_SPI_CSN1 (1<<11) |
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| #define | GPIO_EX_GPIOE (1<<12) |
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| #define | GPIO_SCR (1<<13) |
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| #define | GPIO_MCR (1<<14) |
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| #define | GPIO_SPI_ALL |
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| #define | GPIO_DATA_MASK |
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| #define | SCR_RELAY GPIO_D0 |
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| #define | SCR_PHP_V GPIO_D1_JACKDTC0 |
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| #define | SCR_MUTE GPIO_D2_JACKDTC1 |
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| #define | SCR_PHP GPIO_D3 |
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| #define | SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO |
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| #define | SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK |
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| #define | SCR_AIN34_SEL GPIO_D6_CD |
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| #define | SCR_CODEC_PDN GPIO_D7_DD |
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| #define | SCR_AIN12_LINE (0) |
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| #define | SCR_AIN12_MIC (SCR_AIN12_SEL0) |
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| #define | SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0) |
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| #define | MCR_IN12_MON12 GPIO_D0 |
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| #define | MCR_IN12_MON34 GPIO_D1_JACKDTC0 |
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| #define | MCR_IN34_MON12 GPIO_D2_JACKDTC1 |
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| #define | MCR_IN34_MON34 GPIO_D3 |
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| #define | MCR_OUT34_MON12 GPIO_D4_SPI_CDTO |
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| #define | MCR_OUT12_MON34 GPIO_D5_SPI_CCLK |
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| #define | CPLD_CKS0 GPIO_D0 |
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| #define | CPLD_CKS1 GPIO_D1_JACKDTC0 |
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| #define | CPLD_CKS2 GPIO_D2_JACKDTC1 |
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| #define | CPLD_SYNC_SEL GPIO_D3 |
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| #define | CPLD_WORD_SEL GPIO_D4_SPI_CDTO |
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| #define | CPLD_COAX_OUT GPIO_D5_SPI_CCLK |
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| #define | CPLD_IN12_SEL GPIO_D6_CD |
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| #define | CPLD_IN34_SEL GPIO_D7_DD |
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| #define | CPLD_CKS_44100HZ (0) |
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| #define | CPLD_CKS_48000HZ (CPLD_CKS0) |
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| #define | CPLD_CKS_88200HZ (CPLD_CKS1) |
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| #define | CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0) |
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| #define | CPLD_CKS_176400HZ (CPLD_CKS2) |
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| #define | CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0) |
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| #define | CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2) |
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| #define | CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL) |
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| #define | CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL) |
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| #define | CPLD_EXT_WORDCLOCK_256FS |
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| #define | EXT_SPDIF_TYPE 0 |
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| #define | EXT_WORDCLOCK_1FS_TYPE 1 |
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| #define | EXT_WORDCLOCK_256FS_TYPE 2 |
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| #define | AK4620_DFS0 (1<<0) |
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| #define | AK4620_DFS1 (1<<1) |
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| #define | AK4620_CKS0 (1<<2) |
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| #define | AK4620_CKS1 (1<<3) |
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| #define | AK4620_DFS_REG 0x02 |
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| #define | AK4620_DEEMVOL_REG 0x03 |
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| #define | AK4620_SMUTE (1<<7) |
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| #define | AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch } |
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| #define | PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume" |
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| #define | PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume" |
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| #define | PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume" |
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| #define | PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume" |
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| #define | PRIV_SW(xid, xbit, xreg) |
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| #define | PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) |
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| #define | qtet_sw_info snd_ctl_boolean_mono_info |
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| #define | QTET_CONTROL(xname, xtype, xpriv) |
| |
| #define AK4113_ADDR 0x26 /* S/PDIF receiver */ |
| #define AK4620_ADDR 0x02 /* ADC/DAC */ |
| #define AK4620_CKS0 (1<<2) |
| #define AK4620_CKS1 (1<<3) |
| #define AK4620_DEEMVOL_REG 0x03 |
| #define AK4620_DFS0 (1<<0) |
| #define AK4620_DFS1 (1<<1) |
| #define AK4620_DFS_REG 0x02 |
| #define AK4620_SMUTE (1<<7) |
| #define CPLD_CKS_44100HZ (0) |
| #define CPLD_EXT_WORDCLOCK_256FS |
| #define EXT_WORDCLOCK_1FS_TYPE 1 |
| #define EXT_WORDCLOCK_256FS_TYPE 2 |
| #define GPIO_CPLD_CSN (1<<8) |
| #define GPIO_CPLD_RW (1<<9) |
| #define GPIO_D1_JACKDTC0 (1<<1) |
| #define GPIO_D2_JACKDTC1 (1<<2) |
| #define GPIO_D4_SPI_CDTO (1<<4) |
| #define GPIO_D5_SPI_CCLK (1<<5) |
| #define GPIO_D6_CD (1<<6) |
| #define GPIO_D7_DD (1<<7) |
| #define GPIO_EX_GPIOE (1<<12) |
| #define GPIO_SPI_CSN0 (1<<10) |
| #define GPIO_SPI_CSN1 (1<<11) |
| #define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume" |
| #define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume" |
| #define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume" |
| #define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume" |
| #define PRIV_ENUM2 |
( |
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xid, |
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xbit, |
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xreg, |
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xtext1, |
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xtext2 |
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) |
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Value:
.set_register = set_##xreg,\
.get_register = get_##xreg,\
.texts = {xtext1, xtext2} }
Definition at line 684 of file quartet.c.
| #define PRIV_SW |
( |
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xid, |
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xbit, |
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xreg |
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) |
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Value:
.set_register = set_##xreg,\
.get_register = get_##xreg, }
Definition at line 679 of file quartet.c.
| #define QTET_CONTROL |
( |
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xname, |
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xtype, |
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xpriv |
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Value:
.name = xname,\
.info = qtet_##xtype##_info,\
.get = qtet_sw_get,\
.put = qtet_sw_put,\
.private_value = xpriv }
Definition at line 753 of file quartet.c.
| #define SCR_AIN12_LINE (0) |
- Enumerator:
| IN12_SEL |
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| IN34_SEL |
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| AIN34_SEL |
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| COAX_OUT |
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| IN12_MON12 |
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| IN12_MON34 |
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| IN34_MON12 |
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| IN34_MON34 |
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| OUT12_MON34 |
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| OUT34_MON12 |
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Definition at line 53 of file quartet.c.
1.8.2