29 #include <linux/slab.h>
70 #define AK4113_ADDR 0x26
73 #define AK4620_ADDR 0x02
81 #define GPIO_D0 (1<<0)
83 #define GPIO_D1_JACKDTC0 (1<<1)
85 #define GPIO_D2_JACKDTC1 (1<<2)
87 #define GPIO_D3 (1<<3)
89 #define GPIO_D4_SPI_CDTO (1<<4)
91 #define GPIO_D5_SPI_CCLK (1<<5)
93 #define GPIO_D6_CD (1<<6)
95 #define GPIO_D7_DD (1<<7)
97 #define GPIO_CPLD_CSN (1<<8)
99 #define GPIO_CPLD_RW (1<<9)
101 #define GPIO_SPI_CSN0 (1<<10)
103 #define GPIO_SPI_CSN1 (1<<11)
106 #define GPIO_EX_GPIOE (1<<12)
109 #define GPIO_SCR (1<<13)
112 #define GPIO_MCR (1<<14)
114 #define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
115 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
117 #define GPIO_DATA_MASK (GPIO_D0 | GPIO_D1_JACKDTC0 | \
118 GPIO_D2_JACKDTC1 | GPIO_D3 | \
119 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
120 GPIO_D6_CD | GPIO_D7_DD)
124 #define SCR_RELAY GPIO_D0
126 #define SCR_PHP_V GPIO_D1_JACKDTC0
128 #define SCR_MUTE GPIO_D2_JACKDTC1
130 #define SCR_PHP GPIO_D3
132 #define SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO
133 #define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK
135 #define SCR_AIN34_SEL GPIO_D6_CD
137 #define SCR_CODEC_PDN GPIO_D7_DD
139 #define SCR_AIN12_LINE (0)
140 #define SCR_AIN12_MIC (SCR_AIN12_SEL0)
141 #define SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
145 #define MCR_IN12_MON12 GPIO_D0
147 #define MCR_IN12_MON34 GPIO_D1_JACKDTC0
149 #define MCR_IN34_MON12 GPIO_D2_JACKDTC1
151 #define MCR_IN34_MON34 GPIO_D3
153 #define MCR_OUT34_MON12 GPIO_D4_SPI_CDTO
155 #define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK
159 #define CPLD_CKS0 GPIO_D0
160 #define CPLD_CKS1 GPIO_D1_JACKDTC0
161 #define CPLD_CKS2 GPIO_D2_JACKDTC1
163 #define CPLD_SYNC_SEL GPIO_D3
165 #define CPLD_WORD_SEL GPIO_D4_SPI_CDTO
167 #define CPLD_COAX_OUT GPIO_D5_SPI_CCLK
169 #define CPLD_IN12_SEL GPIO_D6_CD
171 #define CPLD_IN34_SEL GPIO_D7_DD
174 #define CPLD_CKS_44100HZ (0)
175 #define CPLD_CKS_48000HZ (CPLD_CKS0)
176 #define CPLD_CKS_88200HZ (CPLD_CKS1)
177 #define CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0)
178 #define CPLD_CKS_176400HZ (CPLD_CKS2)
179 #define CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0)
181 #define CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
185 #define CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL)
187 #define CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL)
189 #define CPLD_EXT_WORDCLOCK_256FS (CPLD_CKS1 | CPLD_WORD_SEL |\
192 #define EXT_SPDIF_TYPE 0
193 #define EXT_WORDCLOCK_1FS_TYPE 1
194 #define EXT_WORDCLOCK_256FS_TYPE 2
196 #define AK4620_DFS0 (1<<0)
197 #define AK4620_DFS1 (1<<1)
198 #define AK4620_CKS0 (1<<2)
199 #define AK4620_CKS1 (1<<3)
201 #define AK4620_DFS_REG 0x02
204 #define AK4620_DEEMVOL_REG 0x03
205 #define AK4620_SMUTE (1<<7)
215 for (i = 0; i < 4; ++
i) {
216 for (j = 0; j < 8; ++
j) {
217 if (value & (1 << (31-(i*8 + j))))
235 static unsigned int qtet_rates[] = {
237 96000, 176400, 192000,
240 static unsigned int cks_vals[] = {
258 static unsigned char qtet_ak4113_read(
void *private_data,
unsigned char reg)
273 unsigned char addr,
unsigned char data)
275 unsigned int tmp, orig_dir;
277 unsigned int addrdata;
284 orig_dir = ice->
gpio.get_dir(ice);
289 tmp = ice->
gpio.get_data(ice);
292 ice->
gpio.set_data(ice, tmp);
300 ice->
gpio.set_data(ice, tmp);
304 addrdata = (
AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
305 addrdata = (addrdata << 8) | data;
306 for (idx = 15; idx >= 0; idx--) {
309 ice->
gpio.set_data(ice, tmp);
312 if (addrdata & (1 << idx))
316 ice->
gpio.set_data(ice, tmp);
320 ice->
gpio.set_data(ice, tmp);
325 ice->
gpio.set_data(ice, tmp);
329 ice->
gpio.set_mask(ice, 0xffffff);
331 ice->
gpio.set_dir(ice, orig_dir);
334 static void qtet_akm_set_regs(
struct snd_akm4xxx *ak,
unsigned char addr,
339 for (chip = 0; chip < ak->
num_chips; chip++) {
352 static void qtet_akm_set_rate_val(
struct snd_akm4xxx *ak,
unsigned int rate)
354 unsigned char ak4620_dfs;
363 else if (rate > 54000)
373 #define AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch }
375 #define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume"
376 #define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume"
377 #define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume"
378 #define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume"
397 .write = qtet_akm_write,
398 .set_rate_val = qtet_akm_set_rate_val,
400 .dac_info = qtet_dac,
401 .adc_info = qtet_adc,
418 ice->
gpio.set_dir(ice, tmp);
420 ice->
gpio.set_mask(ice, ~(tmp));
422 tmp = ice->
gpio.get_data(ice);
425 ice->
gpio.set_data(ice, tmp);
429 ice->
gpio.set_data(ice, tmp);
433 ice->
gpio.set_data(ice, tmp);
437 ice->
gpio.set_data(ice, tmp);
442 ice->
gpio.set_data(ice, tmp);
444 ice->
gpio.set_mask(ice, 0xffffff);
446 ice->
gpio.set_dir(ice, 0x00ff00);
450 static unsigned int get_scr(
struct snd_ice1712 *ice)
456 static unsigned int get_mcr(
struct snd_ice1712 *ice)
462 static unsigned int get_cpld(
struct snd_ice1712 *ice)
468 static void set_scr(
struct snd_ice1712 *ice,
unsigned int val)
475 static void set_mcr(
struct snd_ice1712 *ice,
unsigned int val)
482 static void set_cpld(
struct snd_ice1712 *ice,
unsigned int val)
488 #ifdef CONFIG_PROC_FS
495 snd_iprintf(buffer,
"SCR: %s\n", get_binary(bin_buffer,
497 snd_iprintf(buffer,
"MCR: %s\n", get_binary(bin_buffer,
499 snd_iprintf(buffer,
"CPLD: %s\n", get_binary(bin_buffer,
506 if (!snd_card_proc_new(ice->
card,
"quartet", &entry))
507 snd_info_set_text_ops(entry, ice, proc_regs_read);
519 ucontrol->
value.integer.value[0] = (
val) ? 0 : 1;
527 unsigned int old,
new, smute;
529 if (ucontrol->
value.integer.value[0]) {
542 set_scr(ice, (get_scr(ice) & ~
SCR_MUTE) |
new);
551 static int qtet_ain12_enum_info(
struct snd_kcontrol *kcontrol,
554 static char *texts[3] = {
"Line In 1/2",
"Mic",
"Mic + Low-cut"};
568 static int qtet_ain12_sw_get(
struct snd_kcontrol *kcontrol,
593 static int qtet_ain12_sw_put(
struct snd_kcontrol *kcontrol,
597 unsigned int old,
new,
tmp, masked_old;
598 old =
new = get_scr(ice);
600 tmp = ucontrol->
value.integer.value[0];
604 if (tmp != masked_old) {
644 ucontrol->
value.integer.value[0] = val ? 1 : 0;
652 unsigned int old,
new;
653 old =
new = get_scr(ice);
654 if (ucontrol->
value.integer.value[0]
663 }
else if (!ucontrol->
value.integer.value[0] && (old & SCR_PHP_V)) {
667 new = old & ~SCR_PHP_V;
679 #define PRIV_SW(xid, xbit, xreg) [xid] = {.bit = xbit,\
680 .set_register = set_##xreg,\
681 .get_register = get_##xreg, }
684 #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\
685 .set_register = set_##xreg,\
686 .get_register = get_##xreg,\
687 .texts = {xtext1, xtext2} }
702 static int qtet_enum_info(
struct snd_kcontrol *kcontrol,
726 ucontrol->
value.integer.value[0] =
727 (
private.get_register(ice) &
private.bit) ? 1 : 0;
737 unsigned int old,
new;
738 old =
private.get_register(ice);
739 if (ucontrol->
value.integer.value[0])
740 new = old |
private.bit;
742 new = old & ~private.
bit;
744 private.set_register(ice,
new);
751 #define qtet_sw_info snd_ctl_boolean_mono_info
753 #define QTET_CONTROL(xname, xtype, xpriv) \
754 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
756 .info = qtet_##xtype##_info,\
759 .private_value = xpriv }
764 .name =
"Master Playback Switch",
766 .get = qtet_mute_get,
767 .put = qtet_mute_put,
772 .name =
"Phantom Power",
780 .name =
"Analog In 1/2 Capture Switch",
781 .info = qtet_ain12_enum_info,
782 .get = qtet_ain12_sw_get,
783 .put = qtet_ain12_sw_put,
798 static char *slave_vols[] __devinitdata = {
821 for (; *
list; list++) {
824 snd_ctl_add_slave(master, slave);
836 for (i = 0; i <
ARRAY_SIZE(qtet_controls); i++) {
845 qtet_master_db_scale);
848 add_slaves(ice->
card, vmaster, slave_vols);
860 static inline int qtet_is_spdif_master(
struct snd_ice1712 *ice)
866 static unsigned int qtet_get_rate(
struct snd_ice1712 *ice)
873 if (cks_vals[i] == result)
874 return qtet_rates[
i];
878 static int get_cks_val(
int rate)
882 if (qtet_rates[i] == rate)
888 static void qtet_set_rate(
struct snd_ice1712 *ice,
unsigned int rate)
904 static inline unsigned char qtet_set_mclk(
struct snd_ice1712 *ice,
914 unsigned int old,
new;
916 old =
new = get_cpld(ice);
939 static int qtet_get_spdif_master_type(
struct snd_ice1712 *ice)
970 static void qtet_ak4113_change(
struct ak4113 *
ak4113,
unsigned char c0,
981 qtet_akm_set_rate_val(ice->
akm, rate);
989 static void qtet_spdif_in_open(
struct snd_ice1712 *ice,
1001 if (rate >= runtime->
hw.rate_min && rate <= runtime->
hw.rate_max) {
1002 runtime->
hw.rate_min =
rate;
1003 runtime->
hw.rate_max =
rate;
1012 static const unsigned char ak4113_init_vals[] = {
1086 spec->
ak4113->change_callback = qtet_ak4113_change;
1087 spec->
ak4113->change_callback_private = ice;
1090 spec->
ak4113->check_flags = 0;
1094 qtet_set_rate(ice, 44100);
1098 static unsigned char qtet_eeprom[] __devinitdata = {
1122 .name =
"Infrasonic Quartet",
1124 .chip_init = qtet_init,
1125 .build_controls = qtet_add_controls,
1126 .eeprom_size =
sizeof(qtet_eeprom),