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r8190P_rtl8256.c
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1 /******************************************************************************
2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3  *
4  * This program is distributed in the hope that it will be useful, but WITHOUT
5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7  * more details.
8  *
9  * You should have received a copy of the GNU General Public License along with
10  * this program; if not, write to the Free Software Foundation, Inc.,
11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12  *
13  * The full GNU General Public License is included in this distribution in the
14  * file called LICENSE.
15  *
16  * Contact Information:
17  * wlanfae <[email protected]>
18 ******************************************************************************/
19 
20 #include "rtl_core.h"
21 #include "r8192E_phyreg.h"
22 #include "r8192E_phy.h"
23 #include "r8190P_rtl8256.h"
24 
25 void PHY_SetRF8256Bandwidth(struct net_device *dev,
26  enum ht_channel_width Bandwidth)
27 {
28  u8 eRFPath;
29  struct r8192_priv *priv = rtllib_priv(dev);
30 
31  for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
32  if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
33  continue;
34 
35  switch (Bandwidth) {
36  case HT_CHANNEL_WIDTH_20:
37  if (priv->card_8192_version == VERSION_8190_BD ||
38  priv->card_8192_version == VERSION_8190_BE) {
39  rtl8192_phy_SetRFReg(dev,
40  (enum rf90_radio_path)eRFPath,
41  0x0b, bMask12Bits, 0x100);
42  rtl8192_phy_SetRFReg(dev,
43  (enum rf90_radio_path)eRFPath,
44  0x2c, bMask12Bits, 0x3d7);
45  rtl8192_phy_SetRFReg(dev,
46  (enum rf90_radio_path)eRFPath,
47  0x0e, bMask12Bits, 0x021);
48 
49  } else {
50  RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): "
51  "unknown hardware version\n");
52  }
53 
54  break;
55  case HT_CHANNEL_WIDTH_20_40:
56  if (priv->card_8192_version == VERSION_8190_BD ||
57  priv->card_8192_version == VERSION_8190_BE) {
58  rtl8192_phy_SetRFReg(dev,
59  (enum rf90_radio_path)eRFPath,
60  0x0b, bMask12Bits, 0x300);
61  rtl8192_phy_SetRFReg(dev,
62  (enum rf90_radio_path)eRFPath,
63  0x2c, bMask12Bits, 0x3ff);
64  rtl8192_phy_SetRFReg(dev,
65  (enum rf90_radio_path)eRFPath,
66  0x0e, bMask12Bits, 0x0e1);
67 
68  } else {
69  RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): "
70  "unknown hardware version\n");
71  }
72 
73 
74  break;
75  default:
76  RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown "
77  "Bandwidth: %#X\n", Bandwidth);
78  break;
79 
80  }
81  }
82  return;
83 }
84 
85 bool PHY_RF8256_Config(struct net_device *dev)
86 {
87  struct r8192_priv *priv = rtllib_priv(dev);
88  bool rtStatus = true;
89  priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
90  rtStatus = phy_RF8256_Config_ParaFile(dev);
91 
92  return rtStatus;
93 }
94 
95 bool phy_RF8256_Config_ParaFile(struct net_device *dev)
96 {
97  u32 u4RegValue = 0;
98  u8 eRFPath;
99  bool rtStatus = true;
100  struct bb_reg_definition *pPhyReg;
101  struct r8192_priv *priv = rtllib_priv(dev);
102  u32 RegOffSetToBeCheck = 0x3;
103  u32 RegValueToBeCheck = 0x7f1;
104  u32 RF3_Final_Value = 0;
105  u8 ConstRetryTimes = 5, RetryTimes = 5;
106  u8 ret = 0;
107 
108  for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
109  eRFPath < priv->NumTotalRFPath; eRFPath++) {
110  if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
111  continue;
112 
113  pPhyReg = &priv->PHYRegDef[eRFPath];
114 
115 
116  switch (eRFPath) {
117  case RF90_PATH_A:
118  case RF90_PATH_C:
119  u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
120  bRFSI_RFENV);
121  break;
122  case RF90_PATH_B:
123  case RF90_PATH_D:
124  u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
125  bRFSI_RFENV<<16);
126  break;
127  }
128 
129  rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
130 
131  rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
132 
133  rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,
134  b3WireAddressLength, 0x0);
135  rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,
136  b3WireDataLength, 0x0);
137 
138  rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0,
139  bMask12Bits, 0xbf);
140 
141  rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF,
142  (enum rf90_radio_path)eRFPath);
143  if (rtStatus != true) {
144  RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check "
145  "Radio[%d] Fail!!\n", eRFPath);
146  goto phy_RF8256_Config_ParaFile_Fail;
147  }
148 
149  RetryTimes = ConstRetryTimes;
150  RF3_Final_Value = 0;
151  switch (eRFPath) {
152  case RF90_PATH_A:
153  while (RF3_Final_Value != RegValueToBeCheck &&
154  RetryTimes != 0) {
155  ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
156  (enum rf90_radio_path)eRFPath);
157  RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
158  (enum rf90_radio_path)eRFPath,
159  RegOffSetToBeCheck,
160  bMask12Bits);
161  RT_TRACE(COMP_RF, "RF %d %d register final "
162  "value: %x\n", eRFPath,
163  RegOffSetToBeCheck, RF3_Final_Value);
164  RetryTimes--;
165  }
166  break;
167  case RF90_PATH_B:
168  while (RF3_Final_Value != RegValueToBeCheck &&
169  RetryTimes != 0) {
170  ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
171  (enum rf90_radio_path)eRFPath);
172  RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
173  (enum rf90_radio_path)eRFPath,
174  RegOffSetToBeCheck,
175  bMask12Bits);
176  RT_TRACE(COMP_RF, "RF %d %d register final "
177  "value: %x\n", eRFPath,
178  RegOffSetToBeCheck, RF3_Final_Value);
179  RetryTimes--;
180  }
181  break;
182  case RF90_PATH_C:
183  while (RF3_Final_Value != RegValueToBeCheck &&
184  RetryTimes != 0) {
185  ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
186  (enum rf90_radio_path)eRFPath);
187  RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
188  (enum rf90_radio_path)eRFPath,
189  RegOffSetToBeCheck,
190  bMask12Bits);
191  RT_TRACE(COMP_RF, "RF %d %d register final "
192  "value: %x\n", eRFPath,
193  RegOffSetToBeCheck, RF3_Final_Value);
194  RetryTimes--;
195  }
196  break;
197  case RF90_PATH_D:
198  while (RF3_Final_Value != RegValueToBeCheck &&
199  RetryTimes != 0) {
200  ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
201  (enum rf90_radio_path)eRFPath);
202  RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
203  (enum rf90_radio_path)eRFPath,
204  RegOffSetToBeCheck, bMask12Bits);
205  RT_TRACE(COMP_RF, "RF %d %d register final "
206  "value: %x\n", eRFPath,
207  RegOffSetToBeCheck, RF3_Final_Value);
208  RetryTimes--;
209  }
210  break;
211  }
212 
213  switch (eRFPath) {
214  case RF90_PATH_A:
215  case RF90_PATH_C:
216  rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
217  u4RegValue);
218  break;
219  case RF90_PATH_B:
220  case RF90_PATH_D:
221  rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16,
222  u4RegValue);
223  break;
224  }
225 
226  if (ret) {
227  RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():"
228  "Radio[%d] Fail!!", eRFPath);
229  goto phy_RF8256_Config_ParaFile_Fail;
230  }
231 
232  }
233 
234  RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
235  return true;
236 
237 phy_RF8256_Config_ParaFile_Fail:
238  RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
239  return false;
240 }
241 
242 void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
243 {
244  u32 TxAGC = 0;
245  struct r8192_priv *priv = rtllib_priv(dev);
246 
247  TxAGC = powerlevel;
248  if (priv->bDynamicTxLowPower == true) {
249  if (priv->CustomerID == RT_CID_819x_Netcore)
250  TxAGC = 0x22;
251  else
252  TxAGC += priv->CckPwEnl;
253  }
254  if (TxAGC > 0x24)
255  TxAGC = 0x24;
256  rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
257 }
258 
259 
260 void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
261 {
262  struct r8192_priv *priv = rtllib_priv(dev);
263  u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
264  u8 index = 0;
265  u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
266  u8 byte0, byte1, byte2, byte3;
267 
268  powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
269  powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
270  (powerBase0 << 8) | powerBase0;
271  powerBase1 = powerlevel;
272  powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) |
273  (powerBase1 << 8) | powerBase1;
274 
275  for (index = 0; index < 6; index++) {
276  writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] +
277  ((index < 2) ? powerBase0 : powerBase1));
278  byte0 = (u8)(writeVal & 0x7f);
279  byte1 = (u8)((writeVal & 0x7f00)>>8);
280  byte2 = (u8)((writeVal & 0x7f0000)>>16);
281  byte3 = (u8)((writeVal & 0x7f000000)>>24);
282  if (byte0 > 0x24)
283  byte0 = 0x24;
284  if (byte1 > 0x24)
285  byte1 = 0x24;
286  if (byte2 > 0x24)
287  byte2 = 0x24;
288  if (byte3 > 0x24)
289  byte3 = 0x24;
290 
291  if (index == 3) {
292  writeVal_tmp = (byte3 << 24) | (byte2 << 16) |
293  (byte1 << 8) | byte0;
294  priv->Pwr_Track = writeVal_tmp;
295  }
296 
297  if (priv->bDynamicTxHighPower == true)
298  writeVal = 0x03030303;
299  else
300  writeVal = (byte3 << 24) | (byte2 << 16) |
301  (byte1 << 8) | byte0;
302  rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
303  }
304 
305  return;
306 }
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