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#define | MPU401_HW_RIPTIDE MPU401_HW_MPU401 |
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#define | OPL3_HW_RIPTIDE OPL3_HW_OPL3 |
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#define | PCI_EXT_CapId 0x40 |
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#define | PCI_EXT_NextCapPrt 0x41 |
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#define | PCI_EXT_PWMC 0x42 |
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#define | PCI_EXT_PWSCR 0x44 |
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#define | PCI_EXT_Data00 0x46 |
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#define | PCI_EXT_PMSCR_BSE 0x47 |
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#define | PCI_EXT_SB_Base 0x48 |
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#define | PCI_EXT_FM_Base 0x4a |
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#define | PCI_EXT_MPU_Base 0x4C |
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#define | PCI_EXT_Game_Base 0x4E |
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#define | PCI_EXT_Legacy_Mask 0x50 |
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#define | PCI_EXT_AsicRev 0x52 |
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#define | PCI_EXT_Reserved3 0x53 |
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#define | LEGACY_ENABLE_ALL 0x8000 /* legacy device options */ |
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#define | LEGACY_ENABLE_SB 0x4000 |
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#define | LEGACY_ENABLE_FM 0x2000 |
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#define | LEGACY_ENABLE_MPU_INT 0x1000 |
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#define | LEGACY_ENABLE_MPU 0x0800 |
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#define | LEGACY_ENABLE_GAMEPORT 0x0400 |
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#define | MAX_WRITE_RETRY 10 /* cmd interface limits */ |
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#define | MAX_ERROR_COUNT 10 |
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#define | CMDIF_TIMEOUT 50000 |
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#define | RESET_TRIES 5 |
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#define | READ_PORT_ULONG(p) inl((unsigned long)&(p)) |
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#define | WRITE_PORT_ULONG(p, x) outl(x,(unsigned long)&(p)) |
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#define | READ_AUDIO_CONTROL(p) READ_PORT_ULONG(p->audio_control) |
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#define | WRITE_AUDIO_CONTROL(p, x) WRITE_PORT_ULONG(p->audio_control,x) |
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#define | UMASK_AUDIO_CONTROL(p, x) WRITE_PORT_ULONG(p->audio_control,READ_PORT_ULONG(p->audio_control)|x) |
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#define | MASK_AUDIO_CONTROL(p, x) WRITE_PORT_ULONG(p->audio_control,READ_PORT_ULONG(p->audio_control)&x) |
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#define | READ_AUDIO_STATUS(p) READ_PORT_ULONG(p->audio_status) |
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#define | SET_GRESET(p) UMASK_AUDIO_CONTROL(p,0x0001) /* global reset switch */ |
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#define | UNSET_GRESET(p) MASK_AUDIO_CONTROL(p,~0x0001) |
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#define | SET_AIE(p) UMASK_AUDIO_CONTROL(p,0x0004) /* interrupt enable */ |
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#define | UNSET_AIE(p) MASK_AUDIO_CONTROL(p,~0x0004) |
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#define | SET_AIACK(p) UMASK_AUDIO_CONTROL(p,0x0008) /* interrupt acknowledge */ |
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#define | UNSET_AIACKT(p) MASKAUDIO_CONTROL(p,~0x0008) |
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#define | SET_ECMDAE(p) UMASK_AUDIO_CONTROL(p,0x0010) |
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#define | UNSET_ECMDAE(p) MASK_AUDIO_CONTROL(p,~0x0010) |
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#define | SET_ECMDBE(p) UMASK_AUDIO_CONTROL(p,0x0020) |
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#define | UNSET_ECMDBE(p) MASK_AUDIO_CONTROL(p,~0x0020) |
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#define | SET_EDATAF(p) UMASK_AUDIO_CONTROL(p,0x0040) |
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#define | UNSET_EDATAF(p) MASK_AUDIO_CONTROL(p,~0x0040) |
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#define | SET_EDATBF(p) UMASK_AUDIO_CONTROL(p,0x0080) |
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#define | UNSET_EDATBF(p) MASK_AUDIO_CONTROL(p,~0x0080) |
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#define | SET_ESBIRQON(p) UMASK_AUDIO_CONTROL(p,0x0100) |
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#define | UNSET_ESBIRQON(p) MASK_AUDIO_CONTROL(p,~0x0100) |
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#define | SET_EMPUIRQ(p) UMASK_AUDIO_CONTROL(p,0x0200) |
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#define | UNSET_EMPUIRQ(p) MASK_AUDIO_CONTROL(p,~0x0200) |
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#define | IS_CMDE(a) (READ_PORT_ULONG(a->stat)&0x1) /* cmd empty */ |
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#define | IS_DATF(a) (READ_PORT_ULONG(a->stat)&0x2) /* data filled */ |
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#define | IS_READY(p) (READ_AUDIO_STATUS(p)&0x0001) |
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#define | IS_DLREADY(p) (READ_AUDIO_STATUS(p)&0x0002) |
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#define | IS_DLERR(p) (READ_AUDIO_STATUS(p)&0x0004) |
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#define | IS_GERR(p) (READ_AUDIO_STATUS(p)&0x0008) /* error ! */ |
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#define | IS_CMDAEIRQ(p) (READ_AUDIO_STATUS(p)&0x0010) |
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#define | IS_CMDBEIRQ(p) (READ_AUDIO_STATUS(p)&0x0020) |
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#define | IS_DATAFIRQ(p) (READ_AUDIO_STATUS(p)&0x0040) |
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#define | IS_DATBFIRQ(p) (READ_AUDIO_STATUS(p)&0x0080) |
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#define | IS_EOBIRQ(p) (READ_AUDIO_STATUS(p)&0x0100) /* interrupt status */ |
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#define | IS_EOSIRQ(p) (READ_AUDIO_STATUS(p)&0x0200) |
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#define | IS_EOCIRQ(p) (READ_AUDIO_STATUS(p)&0x0400) |
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#define | IS_UNSLIRQ(p) (READ_AUDIO_STATUS(p)&0x0800) |
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#define | IS_SBIRQ(p) (READ_AUDIO_STATUS(p)&0x1000) |
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#define | IS_MPUIRQ(p) (READ_AUDIO_STATUS(p)&0x2000) |
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#define | RESP 0x00000001 /* command flags */ |
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#define | PARM 0x00000002 |
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#define | CMDA 0x00000004 |
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#define | CMDB 0x00000008 |
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#define | NILL 0x00000000 |
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#define | LONG0(a) ((u32)a) /* shifts and masks */ |
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#define | BYTE0(a) (LONG0(a)&0xff) |
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#define | BYTE1(a) (BYTE0(a)<<8) |
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#define | BYTE2(a) (BYTE0(a)<<16) |
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#define | BYTE3(a) (BYTE0(a)<<24) |
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#define | WORD0(a) (LONG0(a)&0xffff) |
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#define | WORD1(a) (WORD0(a)<<8) |
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#define | WORD2(a) (WORD0(a)<<16) |
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#define | TRINIB0(a) (LONG0(a)&0xffffff) |
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#define | TRINIB1(a) (TRINIB0(a)<<8) |
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#define | RET(a) ((union cmdret *)(a)) |
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#define | SEND_GETV(p, b) sendcmd(p,RESP,GETV,0,RET(b)) /* get version */ |
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#define | SEND_GETC(p, b, c) sendcmd(p,PARM|RESP,GETC,c,RET(b)) |
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#define | SEND_GUNS(p, b) sendcmd(p,RESP,GUNS,0,RET(b)) |
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#define | SEND_SCID(p, b) sendcmd(p,RESP,SCID,0,RET(b)) |
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#define | SEND_RMEM(p, b, c, d) sendcmd(p,PARM|RESP,RMEM|BYTE1(b),LONG0(c),RET(d)) /* memory access for firmware write */ |
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#define | SEND_SMEM(p, b, c) sendcmd(p,PARM,SMEM|BYTE1(b),LONG0(c),RET(0)) /* memory access for firmware write */ |
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#define | SEND_WMEM(p, b, c) sendcmd(p,PARM,WMEM|BYTE1(b),LONG0(c),RET(0)) /* memory access for firmware write */ |
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#define | SEND_SDTM(p, b, c) sendcmd(p,PARM|RESP,SDTM|TRINIB1(b),0,RET(c)) /* memory access for firmware write */ |
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#define | SEND_GOTO(p, b) sendcmd(p,PARM,GOTO,LONG0(b),RET(0)) /* memory access for firmware write */ |
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#define | SEND_SETDPLL(p) sendcmd(p,0,ARM_SETDPLL,0,RET(0)) |
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#define | SEND_SSTR(p, b, c) sendcmd(p,PARM,SSTR|BYTE3(b),LONG0(c),RET(0)) /* start stream */ |
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#define | SEND_PSTR(p, b) sendcmd(p,PARM,PSTR,BYTE3(b),RET(0)) /* pause stream */ |
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#define | SEND_KSTR(p, b) sendcmd(p,PARM,KSTR,BYTE3(b),RET(0)) /* stop stream */ |
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#define | SEND_KDMA(p) sendcmd(p,0,KDMA,0,RET(0)) /* stop all dma */ |
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#define | SEND_GPOS(p, b, c, d) sendcmd(p,PARM|RESP,GPOS,BYTE3(c)|BYTE2(b),RET(d)) /* get position in dma */ |
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#define | SEND_SETF(p, b, c, d, e, f, g) sendcmd(p,PARM,SETF|WORD1(b)|BYTE3(c),d|BYTE1(e)|BYTE2(f)|BYTE3(g),RET(0)) /* set sample format at mixer */ |
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#define | SEND_GSTS(p, b, c, d) sendcmd(p,PARM|RESP,GSTS,BYTE3(c)|BYTE2(b),RET(d)) |
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#define | SEND_NGPOS(p, b, c, d) sendcmd(p,PARM|RESP,NGPOS,BYTE3(c)|BYTE2(b),RET(d)) |
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#define | SEND_PSEL(p, b, c) sendcmd(p,PARM,PSEL,BYTE2(b)|BYTE3(c),RET(0)) /* activate lbus path */ |
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#define | SEND_PCLR(p, b, c) sendcmd(p,PARM,PCLR,BYTE2(b)|BYTE3(c),RET(0)) /* deactivate lbus path */ |
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#define | SEND_PLST(p, b) sendcmd(p,PARM,PLST,BYTE3(b),RET(0)) |
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#define | SEND_RSSV(p, b, c, d) sendcmd(p,PARM|RESP,RSSV,BYTE2(b)|BYTE3(c),RET(d)) |
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#define | SEND_LSEL(p, b, c, d, e, f, g, h) sendcmd(p,PARM,LSEL|BYTE1(b)|BYTE2(c)|BYTE3(d),BYTE0(e)|BYTE1(f)|BYTE2(g)|BYTE3(h),RET(0)) /* select paths for internal connections */ |
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#define | SEND_SSRC(p, b, c, d, e) sendcmd(p,PARM,SSRC|BYTE1(b)|WORD2(c),WORD0(d)|WORD2(e),RET(0)) /* configure source */ |
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#define | SEND_SLST(p, b) sendcmd(p,PARM,SLST,BYTE3(b),RET(0)) |
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#define | SEND_RSRC(p, b, c) sendcmd(p,RESP,RSRC|BYTE1(b),0,RET(c)) /* read source config */ |
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#define | SEND_SSRB(p, b, c) sendcmd(p,PARM,SSRB|BYTE1(b),WORD2(c),RET(0)) |
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#define | SEND_SDGV(p, b, c, d, e) sendcmd(p,PARM,SDGV|BYTE2(b)|BYTE3(c),WORD0(d)|WORD2(e),RET(0)) /* set digital mixer */ |
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#define | SEND_RDGV(p, b, c, d) sendcmd(p,PARM|RESP,RDGV|BYTE2(b)|BYTE3(c),0,RET(d)) /* read digital mixer */ |
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#define | SEND_DLST(p, b) sendcmd(p,PARM,DLST,BYTE3(b),RET(0)) |
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#define | SEND_SACR(p, b, c) sendcmd(p,PARM,SACR,WORD0(b)|WORD2(c),RET(0)) /* set AC97 register */ |
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#define | SEND_RACR(p, b, c) sendcmd(p,PARM|RESP,RACR,WORD2(b),RET(c)) /* get AC97 register */ |
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#define | SEND_ALST(p, b) sendcmd(p,PARM,ALST,BYTE3(b),RET(0)) |
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#define | SEND_TXAC(p, b, c, d, e, f) sendcmd(p,PARM,TXAC|BYTE1(b)|WORD2(c),WORD0(d)|BYTE2(e)|BYTE3(f),RET(0)) |
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#define | SEND_RXAC(p, b, c, d) sendcmd(p,PARM|RESP,RXAC,BYTE2(b)|BYTE3(c),RET(d)) |
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#define | SEND_SI2S(p, b) sendcmd(p,PARM,SI2S,WORD2(b),RET(0)) |
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#define | EOB_STATUS 0x80000000 /* status flags : block boundary */ |
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#define | EOS_STATUS 0x40000000 /* : stoppped */ |
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#define | EOC_STATUS 0x20000000 /* : stream end */ |
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#define | ERR_STATUS 0x10000000 |
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#define | EMPTY_STATUS 0x08000000 |
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#define | IEOB_ENABLE 0x1 /* enable interrupts for status notification above */ |
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#define | IEOS_ENABLE 0x2 |
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#define | IEOC_ENABLE 0x4 |
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#define | RDONCE 0x8 |
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#define | DESC_MAX_MASK 0xff |
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#define | ST_PLAY 0x1 /* stream states */ |
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#define | ST_STOP 0x2 |
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#define | ST_PAUSE 0x4 |
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#define | I2S_INTDEC 3 /* config for I2S link */ |
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#define | I2S_MERGER 0 |
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#define | I2S_SPLITTER 0 |
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#define | I2S_MIXER 7 |
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#define | I2S_RATE 44100 |
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#define | MODEM_INTDEC 4 /* config for modem link */ |
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#define | MODEM_MERGER 3 |
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#define | MODEM_SPLITTER 0 |
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#define | MODEM_MIXER 11 |
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#define | FM_INTDEC 3 /* config for FM/OPL3 link */ |
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#define | FM_MERGER 0 |
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#define | FM_SPLITTER 0 |
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#define | FM_MIXER 9 |
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#define | SPLIT_PATH 0x80 /* path splitting flag */ |
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#define | get_pcmhwdev(substream) (struct pcmhw *)(substream->runtime->private_data) |
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#define | PLAYBACK_SUBSTREAMS 3 |
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#define | CMDRET_ZERO (union cmdret){{(u32)0, (u32) 0}} |
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#define | FIRMWARE_VERSIONS 1 |
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#define | RIPTIDE_PM_OPS NULL |
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