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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/types.h>#include <linux/mm.h>#include <linux/spinlock.h>#include <linux/slab.h>#include <linux/export.h>#include <linux/init.h>#include <linux/interrupt.h>#include <linux/of.h>#include <linux/of_device.h>#include <asm/page.h>#include <asm/io.h>#include <asm/upa.h>#include <asm/cache.h>#include <asm/dma.h>#include <asm/irq.h>#include <asm/prom.h>#include <asm/oplib.h>#include <asm/starfire.h>#include "iommu_common.h"Go to the source code of this file.
Macros | |
| #define | MAP_BASE ((u32)0xc0000000) |
| #define | SYSIO_IOMMUREG_BASE 0x2400UL |
| #define | IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ |
| #define | IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */ |
| #define | IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */ |
| #define | IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */ |
| #define | IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */ |
| #define | IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */ |
| #define | IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */ |
| #define | IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */ |
| #define | IOMMU_DRAM_VALID (1UL << 30UL) |
| #define | SYSIO_STRBUFREG_BASE 0x2800UL |
| #define | STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */ |
| #define | STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */ |
| #define | STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */ |
| #define | STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */ |
| #define | STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */ |
| #define | STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */ |
| #define | STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */ |
| #define | STRBUF_TAG_VALID 0x02UL |
| #define | SYSIO_IMAP_SLOT0 0x2c00UL |
| #define | SYSIO_IMAP_SLOT1 0x2c08UL |
| #define | SYSIO_IMAP_SLOT2 0x2c10UL |
| #define | SYSIO_IMAP_SLOT3 0x2c18UL |
| #define | SYSIO_IMAP_SCSI 0x3000UL |
| #define | SYSIO_IMAP_ETH 0x3008UL |
| #define | SYSIO_IMAP_BPP 0x3010UL |
| #define | SYSIO_IMAP_AUDIO 0x3018UL |
| #define | SYSIO_IMAP_PFAIL 0x3020UL |
| #define | SYSIO_IMAP_KMS 0x3028UL |
| #define | SYSIO_IMAP_FLPY 0x3030UL |
| #define | SYSIO_IMAP_SHW 0x3038UL |
| #define | SYSIO_IMAP_KBD 0x3040UL |
| #define | SYSIO_IMAP_MS 0x3048UL |
| #define | SYSIO_IMAP_SER 0x3050UL |
| #define | SYSIO_IMAP_TIM0 0x3060UL |
| #define | SYSIO_IMAP_TIM1 0x3068UL |
| #define | SYSIO_IMAP_UE 0x3070UL |
| #define | SYSIO_IMAP_CE 0x3078UL |
| #define | SYSIO_IMAP_SBERR 0x3080UL |
| #define | SYSIO_IMAP_PMGMT 0x3088UL |
| #define | SYSIO_IMAP_GFX 0x3090UL |
| #define | SYSIO_IMAP_EUPA 0x3098UL |
| #define | bogon ((unsigned long) -1) |
| #define | NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets) |
| #define | SYSIO_ICLR_UNUSED0 0x3400UL |
| #define | SYSIO_ICLR_SLOT0 0x3408UL |
| #define | SYSIO_ICLR_SLOT1 0x3448UL |
| #define | SYSIO_ICLR_SLOT2 0x3488UL |
| #define | SYSIO_ICLR_SLOT3 0x34c8UL |
| #define | SYSIO_UE_AFSR 0x0030UL |
| #define | SYSIO_UE_AFAR 0x0038UL |
| #define | SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ |
| #define | SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ |
| #define | SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ |
| #define | SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| #define | SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ |
| #define | SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ |
| #define | SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
| #define | SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */ |
| #define | SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ |
| #define | SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ |
| #define | SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ |
| #define | SYSIO_CE_AFSR 0x0040UL |
| #define | SYSIO_CE_AFAR 0x0048UL |
| #define | SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ |
| #define | SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ |
| #define | SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ |
| #define | SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */ |
| #define | SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ |
| #define | SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ |
| #define | SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ |
| #define | SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ |
| #define | SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */ |
| #define | SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ |
| #define | SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ |
| #define | SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ |
| #define | SYSIO_SBUS_AFSR 0x2010UL |
| #define | SYSIO_SBUS_AFAR 0x2018UL |
| #define | SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */ |
| #define | SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */ |
| #define | SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */ |
| #define | SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */ |
| #define | SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */ |
| #define | SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */ |
| #define | SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
| #define | SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */ |
| #define | SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */ |
| #define | SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */ |
| #define | SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */ |
| #define | SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */ |
| #define | ECC_CONTROL 0x0020UL |
| #define | SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */ |
| #define | SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */ |
| #define | SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */ |
| #define | SYSIO_UE_INO 0x34 |
| #define | SYSIO_CE_INO 0x35 |
| #define | SYSIO_SBUSERR_INO 0x36 |
Functions | |
| void | sbus_set_sbus64 (struct device *dev, int bursts) |
| EXPORT_SYMBOL (sbus_set_sbus64) | |
| subsys_initcall (sbus_init) | |
| #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ |
| #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */ |
| #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */ |
| #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */ |
| #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */ |
| #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */ |
| #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */ |
| #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */ |
| #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets) |
| #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */ |
| #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */ |
| #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */ |
| #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */ |
| #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */ |
| #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */ |
| #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */ |
| #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ |
| #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ |
| #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ |
| #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ |
| #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ |
| #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ |
| #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ |
| #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ |
| #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ |
| #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ |
| #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */ |
| #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */ |
| #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */ |
| #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */ |
| #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */ |
| #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */ |
| #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */ |
| #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */ |
| #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */ |
| #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
| #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */ |
| #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */ |
| #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */ |
| #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */ |
| #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */ |
| #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */ |
| #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */ |
| #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ |
| #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ |
| #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ |
| #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ |
| #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
| #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ |
| #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ |
| #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ |
| #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ |
| #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| EXPORT_SYMBOL | ( | sbus_set_sbus64 | ) |
| subsys_initcall | ( | sbus_init | ) |
1.8.2