7 #include <linux/kernel.h>
8 #include <linux/types.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
21 #include <asm/cache.h>
25 #include <asm/oplib.h>
30 #define MAP_BASE ((u32)0xc0000000)
33 #define SYSIO_IOMMUREG_BASE 0x2400UL
34 #define IOMMU_CONTROL (0x2400UL - 0x2400UL)
35 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL)
36 #define IOMMU_FLUSH (0x2410UL - 0x2400UL)
37 #define IOMMU_VADIAG (0x4400UL - 0x2400UL)
38 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL)
39 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL)
40 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL)
41 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL)
43 #define IOMMU_DRAM_VALID (1UL << 30UL)
46 #define SYSIO_STRBUFREG_BASE 0x2800UL
47 #define STRBUF_CONTROL (0x2800UL - 0x2800UL)
48 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL)
49 #define STRBUF_FSYNC (0x2810UL - 0x2800UL)
50 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL)
51 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL)
52 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL)
53 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL)
55 #define STRBUF_TAG_VALID 0x02UL
63 unsigned long cfg_reg;
70 op->
dev.of_node->full_name);
103 val = upa_readq(cfg_reg);
104 if (val & (1
UL << 14
UL)) {
109 val |= (1
UL << 14
UL);
119 upa_writeq(val, cfg_reg);
127 #define SYSIO_IMAP_SLOT0 0x2c00UL
128 #define SYSIO_IMAP_SLOT1 0x2c08UL
129 #define SYSIO_IMAP_SLOT2 0x2c10UL
130 #define SYSIO_IMAP_SLOT3 0x2c18UL
131 #define SYSIO_IMAP_SCSI 0x3000UL
132 #define SYSIO_IMAP_ETH 0x3008UL
133 #define SYSIO_IMAP_BPP 0x3010UL
134 #define SYSIO_IMAP_AUDIO 0x3018UL
135 #define SYSIO_IMAP_PFAIL 0x3020UL
136 #define SYSIO_IMAP_KMS 0x3028UL
137 #define SYSIO_IMAP_FLPY 0x3030UL
138 #define SYSIO_IMAP_SHW 0x3038UL
139 #define SYSIO_IMAP_KBD 0x3040UL
140 #define SYSIO_IMAP_MS 0x3048UL
141 #define SYSIO_IMAP_SER 0x3050UL
142 #define SYSIO_IMAP_TIM0 0x3060UL
143 #define SYSIO_IMAP_TIM1 0x3068UL
144 #define SYSIO_IMAP_UE 0x3070UL
145 #define SYSIO_IMAP_CE 0x3078UL
146 #define SYSIO_IMAP_SBERR 0x3080UL
147 #define SYSIO_IMAP_PMGMT 0x3088UL
148 #define SYSIO_IMAP_GFX 0x3090UL
149 #define SYSIO_IMAP_EUPA 0x3098UL
151 #define bogon ((unsigned long) -1)
152 static unsigned long sysio_irq_offsets[] = {
192 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
197 #define SYSIO_ICLR_UNUSED0 0x3400UL
198 #define SYSIO_ICLR_SLOT0 0x3408UL
199 #define SYSIO_ICLR_SLOT1 0x3448UL
200 #define SYSIO_ICLR_SLOT2 0x3488UL
201 #define SYSIO_ICLR_SLOT3 0x34c8UL
202 static unsigned long sysio_imap_to_iclr(
unsigned long imap)
212 unsigned long imap, iclr;
215 imap = sysio_irq_offsets[
ino];
216 if (imap == ((
unsigned long)-1)) {
217 prom_printf(
"get_irq_translations: Bad SYSIO INO[%x]\n",
228 iclr = sysio_imap_to_iclr(imap);
230 int sbus_slot = (ino & 0x18)>>3;
232 sbus_level = ino & 0x7;
250 iclr += ((
unsigned long)sbus_level - 1
UL) * 8
UL;
252 return build_irq(sbus_level, iclr, imap);
256 #define SYSIO_UE_AFSR 0x0030UL
257 #define SYSIO_UE_AFAR 0x0038UL
258 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL
259 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL
260 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL
261 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL
262 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL
263 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL
264 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL
265 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL
266 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL
267 #define SYSIO_UEAFSR_MID 0x000003e000000000UL
268 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL
272 struct iommu *iommu = op->
dev.archdata.iommu;
274 unsigned long afsr_reg, afar_reg;
276 int reported, portid;
282 afsr = upa_readq(afsr_reg);
283 afar = upa_readq(afar_reg);
289 upa_writeq(error_bits, afsr_reg);
294 printk(
"SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
301 "DVMA Write" :
"???")))));
302 printk(
"SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
307 printk(
"SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
308 printk(
"SYSIO[%x]: Secondary UE errors [", portid);
329 #define SYSIO_CE_AFSR 0x0040UL
330 #define SYSIO_CE_AFAR 0x0048UL
331 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL
332 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL
333 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL
334 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL
335 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL
336 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL
337 #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL
338 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL
339 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL
340 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL
341 #define SYSIO_CEAFSR_MID 0x000003e000000000UL
342 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL
346 struct iommu *iommu = op->
dev.archdata.iommu;
348 unsigned long afsr_reg, afar_reg;
350 int reported, portid;
356 afsr = upa_readq(afsr_reg);
357 afar = upa_readq(afar_reg);
363 upa_writeq(error_bits, afsr_reg);
367 printk(
"SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
374 "DVMA Write" :
"???")))));
379 printk(
"SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
385 printk(
"SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
387 printk(
"SYSIO[%x]: Secondary CE errors [", portid);
408 #define SYSIO_SBUS_AFSR 0x2010UL
409 #define SYSIO_SBUS_AFAR 0x2018UL
410 #define SYSIO_SBAFSR_PLE 0x8000000000000000UL
411 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL
412 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL
413 #define SYSIO_SBAFSR_SLE 0x1000000000000000UL
414 #define SYSIO_SBAFSR_STO 0x0800000000000000UL
415 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL
416 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL
417 #define SYSIO_SBAFSR_RD 0x0000800000000000UL
418 #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL
419 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL
420 #define SYSIO_SBAFSR_MID 0x000003e000000000UL
421 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL
425 struct iommu *iommu = op->
dev.archdata.iommu;
426 unsigned long afsr_reg, afar_reg, reg_base;
428 int reported, portid;
434 afsr = upa_readq(afsr_reg);
435 afar = upa_readq(afar_reg);
441 upa_writeq(error_bits, afsr_reg);
446 printk(
"SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
453 "Error Ack" :
"???")))),
455 printk(
"SYSIO[%x]: size[%lx] MID[%lx]\n",
459 printk(
"SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
460 printk(
"SYSIO[%x]: Secondary SBUS errors [", portid);
464 printk(
"(Late PIO Error)");
483 #define ECC_CONTROL 0x0020UL
484 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL
485 #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL
486 #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL
488 #define SYSIO_UE_INO 0x34
489 #define SYSIO_CE_INO 0x35
490 #define SYSIO_SBUSERR_INO 0x36
494 struct iommu *iommu = op->
dev.archdata.iommu;
504 "SYSIO_UE", op) < 0) {
505 prom_printf(
"SYSIO[%x]: Cannot register UE interrupt.\n",
512 "SYSIO_CE", op) < 0) {
513 prom_printf(
"SYSIO[%x]: Cannot register CE interrupt.\n",
520 "SYSIO_SBERR", op) < 0) {
521 prom_printf(
"SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
544 unsigned long regs, reg_base;
551 "control registers.\n");
558 goto fatal_memory_error;
559 strbuf = kzalloc(
sizeof(*strbuf),
GFP_ATOMIC);
561 goto fatal_memory_error;
563 op->
dev.archdata.iommu = iommu;
564 op->
dev.archdata.stc = strbuf;
565 op->
dev.archdata.numa_node = -1;
599 goto fatal_memory_error;
602 control = ((7UL << 16
UL) |
611 for (i = 0; i < 16; i++) {
612 unsigned long dram,
tag;
617 dram += (
unsigned long)i * 8UL;
618 tag += (
unsigned long)i * 8UL;
628 control = (1UL << 1
UL) | (1UL << 0UL);
632 for (i = 0; i < 16; i++) {
633 unsigned long ptag, ltag;
639 ptag += (
unsigned long)i * 8UL;
640 ltag += (
unsigned long)i * 8UL;
642 upa_writeq(0UL, ptag);
643 upa_writeq(0UL, ltag);
655 sysio_register_error_handlers(op);
659 prom_printf(
"sbus_iommu_init: Fatal memory allocation error.\n");
666 for_each_node_by_name(dp,
"sbus") {