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sdhci-s3c.c
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1 /* linux/drivers/mmc/host/sdhci-s3c.c
2  *
3  * Copyright 2008 Openmoko Inc.
4  * Copyright 2008 Simtec Electronics
5  * Ben Dooks <[email protected]>
6  * http://armlinux.simtec.co.uk/
7  *
8  * SDHCI (HSMMC) support for Samsung SoC
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_gpio.h>
25 #include <linux/pm.h>
26 #include <linux/pm_runtime.h>
27 
28 #include <linux/mmc/host.h>
29 
30 #include <plat/sdhci.h>
31 #include <plat/regs-sdhci.h>
32 
33 #include "sdhci.h"
34 
35 #define MAX_BUS_CLK (4)
36 
37 /* Number of gpio's used is max data bus width + command and clock lines */
38 #define NUM_GPIOS(x) (x + 2)
39 
51 struct sdhci_s3c {
52  struct sdhci_host *host;
54  struct resource *ioarea;
56  unsigned int cur_clk;
59  int *gpios;
60 
61  struct clk *clk_io;
63 };
64 
74  unsigned int sdhci_quirks;
75 };
76 
77 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
78 {
79  return sdhci_priv(host);
80 }
81 
86 static u32 get_curclk(u32 ctrl2)
87 {
90 
91  return ctrl2;
92 }
93 
94 static void sdhci_s3c_check_sclk(struct sdhci_host *host)
95 {
96  struct sdhci_s3c *ourhost = to_s3c(host);
98 
99  if (get_curclk(tmp) != ourhost->cur_clk) {
100  dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
101 
103  tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
104  writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2);
105  }
106 }
107 
114 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
115 {
116  struct sdhci_s3c *ourhost = to_s3c(host);
117  struct clk *busclk;
118  unsigned int rate, max;
119  int clk;
120 
121  /* note, a reset will reset the clock source */
122 
123  sdhci_s3c_check_sclk(host);
124 
125  for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
126  busclk = ourhost->clk_bus[clk];
127  if (!busclk)
128  continue;
129 
130  rate = clk_get_rate(busclk);
131  if (rate > max)
132  max = rate;
133  }
134 
135  return max;
136 }
137 
144 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
145  unsigned int src,
146  unsigned int wanted)
147 {
148  unsigned long rate;
149  struct clk *clksrc = ourhost->clk_bus[src];
150  int div;
151 
152  if (!clksrc)
153  return UINT_MAX;
154 
155  /*
156  * If controller uses a non-standard clock division, find the best clock
157  * speed possible with selected clock source and skip the division.
158  */
159  if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
160  rate = clk_round_rate(clksrc, wanted);
161  return wanted - rate;
162  }
163 
164  rate = clk_get_rate(clksrc);
165 
166  for (div = 1; div < 256; div *= 2) {
167  if ((rate / div) <= wanted)
168  break;
169  }
170 
171  dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
172  src, rate, wanted, rate / div);
173 
174  return wanted - (rate / div);
175 }
176 
185 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
186 {
187  struct sdhci_s3c *ourhost = to_s3c(host);
188  unsigned int best = UINT_MAX;
189  unsigned int delta;
190  int best_src = 0;
191  int src;
192  u32 ctrl;
193 
194  /* don't bother if the clock is going off. */
195  if (clock == 0)
196  return;
197 
198  for (src = 0; src < MAX_BUS_CLK; src++) {
199  delta = sdhci_s3c_consider_clock(ourhost, src, clock);
200  if (delta < best) {
201  best = delta;
202  best_src = src;
203  }
204  }
205 
206  dev_dbg(&ourhost->pdev->dev,
207  "selected source %d, clock %d, delta %d\n",
208  best_src, clock, best);
209 
210  /* select the new clock source */
211  if (ourhost->cur_clk != best_src) {
212  struct clk *clk = ourhost->clk_bus[best_src];
213 
214  clk_prepare_enable(clk);
215  clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
216 
217  /* turn clock off to card before changing clock source */
218  writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
219 
220  ourhost->cur_clk = best_src;
221  host->max_clk = clk_get_rate(clk);
222 
223  ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
225  ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
226  writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
227  }
228 
229  /* reprogram default hardware configuration */
232 
233  ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
239  writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
240 
241  /* reconfigure the controller for new clock rate */
243  if (clock < 25 * 1000000)
245  writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
246 }
247 
257 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
258 {
259  struct sdhci_s3c *ourhost = to_s3c(host);
260  unsigned int delta, min = UINT_MAX;
261  int src;
262 
263  for (src = 0; src < MAX_BUS_CLK; src++) {
264  delta = sdhci_s3c_consider_clock(ourhost, src, 0);
265  if (delta == UINT_MAX)
266  continue;
267  /* delta is a negative value in this case */
268  if (-delta < min)
269  min = -delta;
270  }
271  return min;
272 }
273 
274 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
275 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
276 {
277  struct sdhci_s3c *ourhost = to_s3c(host);
278 
279  return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
280 }
281 
282 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
283 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
284 {
285  struct sdhci_s3c *ourhost = to_s3c(host);
286 
287  /*
288  * initial clock can be in the frequency range of
289  * 100KHz-400KHz, so we set it as max value.
290  */
291  return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
292 }
293 
294 /* sdhci_cmu_set_clock - callback on clock change.*/
295 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
296 {
297  struct sdhci_s3c *ourhost = to_s3c(host);
298  struct device *dev = &ourhost->pdev->dev;
299  unsigned long timeout;
300  u16 clk = 0;
301 
302  /* don't bother if the clock is going off */
303  if (clock == 0)
304  return;
305 
306  sdhci_s3c_set_clock(host, clock);
307 
308  clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
309 
310  host->clock = clock;
311 
312  clk = SDHCI_CLOCK_INT_EN;
313  sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
314 
315  /* Wait max 20 ms */
316  timeout = 20;
317  while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
319  if (timeout == 0) {
320  dev_err(dev, "%s: Internal clock never stabilised.\n",
321  mmc_hostname(host->mmc));
322  return;
323  }
324  timeout--;
325  mdelay(1);
326  }
327 
328  clk |= SDHCI_CLOCK_CARD_EN;
329  sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
330 }
331 
340 static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width)
341 {
342  u8 ctrl;
343 
344  ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
345 
346  switch (width) {
347  case MMC_BUS_WIDTH_8:
348  ctrl |= SDHCI_CTRL_8BITBUS;
349  ctrl &= ~SDHCI_CTRL_4BITBUS;
350  break;
351  case MMC_BUS_WIDTH_4:
352  ctrl |= SDHCI_CTRL_4BITBUS;
353  ctrl &= ~SDHCI_CTRL_8BITBUS;
354  break;
355  default:
356  ctrl &= ~SDHCI_CTRL_4BITBUS;
357  ctrl &= ~SDHCI_CTRL_8BITBUS;
358  break;
359  }
360 
361  sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
362 
363  return 0;
364 }
365 
366 static struct sdhci_ops sdhci_s3c_ops = {
367  .get_max_clock = sdhci_s3c_get_max_clk,
368  .set_clock = sdhci_s3c_set_clock,
369  .get_min_clock = sdhci_s3c_get_min_clock,
370  .platform_8bit_width = sdhci_s3c_platform_8bit_width,
371 };
372 
373 static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
374 {
375  struct sdhci_host *host = platform_get_drvdata(dev);
376  struct sdhci_s3c *sc = sdhci_priv(host);
377  unsigned long flags;
378 
379  if (host) {
380  spin_lock_irqsave(&host->lock, flags);
381  if (state) {
382  dev_dbg(&dev->dev, "card inserted.\n");
383 #ifdef CONFIG_PM_RUNTIME
384  clk_prepare_enable(sc->clk_io);
385 #endif
386  host->flags &= ~SDHCI_DEVICE_DEAD;
388  } else {
389  dev_dbg(&dev->dev, "card removed.\n");
390  host->flags |= SDHCI_DEVICE_DEAD;
392 #ifdef CONFIG_PM_RUNTIME
393  clk_disable_unprepare(sc->clk_io);
394 #endif
395  }
396  tasklet_schedule(&host->card_tasklet);
397  spin_unlock_irqrestore(&host->lock, flags);
398  }
399 }
400 
401 static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
402 {
403  struct sdhci_s3c *sc = dev_id;
404  int status = gpio_get_value(sc->ext_cd_gpio);
405  if (sc->pdata->ext_cd_gpio_invert)
406  status = !status;
407  sdhci_s3c_notify_change(sc->pdev, status);
408  return IRQ_HANDLED;
409 }
410 
411 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
412 {
413  struct s3c_sdhci_platdata *pdata = sc->pdata;
414  struct device *dev = &sc->pdev->dev;
415 
416  if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
417  sc->ext_cd_gpio = pdata->ext_cd_gpio;
418  sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
419  if (sc->ext_cd_irq &&
421  sdhci_s3c_gpio_card_detect_thread,
424  IRQF_ONESHOT,
425  dev_name(dev), sc) == 0) {
426  int status = gpio_get_value(sc->ext_cd_gpio);
427  if (pdata->ext_cd_gpio_invert)
428  status = !status;
429  sdhci_s3c_notify_change(sc->pdev, status);
430  } else {
431  dev_warn(dev, "cannot request irq for card detect\n");
432  sc->ext_cd_irq = 0;
433  }
434  } else {
435  dev_err(dev, "cannot request gpio for card detect\n");
436  }
437 }
438 
439 #ifdef CONFIG_OF
440 static int __devinit sdhci_s3c_parse_dt(struct device *dev,
441  struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
442 {
443  struct device_node *node = dev->of_node;
444  struct sdhci_s3c *ourhost = to_s3c(host);
445  u32 max_width;
446  int gpio, cnt, ret;
447 
448  /* if the bus-width property is not specified, assume width as 1 */
449  if (of_property_read_u32(node, "bus-width", &max_width))
450  max_width = 1;
451  pdata->max_width = max_width;
452 
453  ourhost->gpios = devm_kzalloc(dev, NUM_GPIOS(pdata->max_width) *
454  sizeof(int), GFP_KERNEL);
455  if (!ourhost->gpios)
456  return -ENOMEM;
457 
458  /* get the card detection method */
459  if (of_get_property(node, "broken-cd", 0)) {
460  pdata->cd_type = S3C_SDHCI_CD_NONE;
461  goto setup_bus;
462  }
463 
464  if (of_get_property(node, "non-removable", 0)) {
466  goto setup_bus;
467  }
468 
469  gpio = of_get_named_gpio(node, "cd-gpios", 0);
470  if (gpio_is_valid(gpio)) {
471  pdata->cd_type = S3C_SDHCI_CD_GPIO;
472  goto found_cd;
473  } else if (gpio != -ENOENT) {
474  dev_err(dev, "invalid card detect gpio specified\n");
475  return -EINVAL;
476  }
477 
478  gpio = of_get_named_gpio(node, "samsung,cd-pinmux-gpio", 0);
479  if (gpio_is_valid(gpio)) {
481  goto found_cd;
482  } else if (gpio != -ENOENT) {
483  dev_err(dev, "invalid card detect gpio specified\n");
484  return -EINVAL;
485  }
486 
487  dev_info(dev, "assuming no card detect line available\n");
488  pdata->cd_type = S3C_SDHCI_CD_NONE;
489 
490  found_cd:
491  if (pdata->cd_type == S3C_SDHCI_CD_GPIO) {
492  pdata->ext_cd_gpio = gpio;
493  ourhost->ext_cd_gpio = -1;
494  if (of_get_property(node, "cd-inverted", NULL))
495  pdata->ext_cd_gpio_invert = 1;
496  } else if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
497  ret = gpio_request(gpio, "sdhci-cd");
498  if (ret) {
499  dev_err(dev, "card detect gpio request failed\n");
500  return -EINVAL;
501  }
502  ourhost->ext_cd_gpio = gpio;
503  }
504 
505  setup_bus:
506  /* get the gpios for command, clock and data lines */
507  for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) {
508  gpio = of_get_gpio(node, cnt);
509  if (!gpio_is_valid(gpio)) {
510  dev_err(dev, "invalid gpio[%d]\n", cnt);
511  goto err_free_dt_cd_gpio;
512  }
513  ourhost->gpios[cnt] = gpio;
514  }
515 
516  for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) {
517  ret = gpio_request(ourhost->gpios[cnt], "sdhci-gpio");
518  if (ret) {
519  dev_err(dev, "gpio[%d] request failed\n", cnt);
520  goto err_free_dt_gpios;
521  }
522  }
523 
524  return 0;
525 
526  err_free_dt_gpios:
527  while (--cnt >= 0)
528  gpio_free(ourhost->gpios[cnt]);
529  err_free_dt_cd_gpio:
530  if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL)
531  gpio_free(ourhost->ext_cd_gpio);
532  return -EINVAL;
533 }
534 #else
535 static int __devinit sdhci_s3c_parse_dt(struct device *dev,
536  struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
537 {
538  return -EINVAL;
539 }
540 #endif
541 
542 static const struct of_device_id sdhci_s3c_dt_match[];
543 
544 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
545  struct platform_device *pdev)
546 {
547 #ifdef CONFIG_OF
548  if (pdev->dev.of_node) {
549  const struct of_device_id *match;
550  match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
551  return (struct sdhci_s3c_drv_data *)match->data;
552  }
553 #endif
554  return (struct sdhci_s3c_drv_data *)
555  platform_get_device_id(pdev)->driver_data;
556 }
557 
558 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
559 {
560  struct s3c_sdhci_platdata *pdata;
562  struct device *dev = &pdev->dev;
563  struct sdhci_host *host;
564  struct sdhci_s3c *sc;
565  struct resource *res;
566  int ret, irq, ptr, clks;
567 
568  if (!pdev->dev.platform_data && !pdev->dev.of_node) {
569  dev_err(dev, "no device data specified\n");
570  return -ENOENT;
571  }
572 
573  irq = platform_get_irq(pdev, 0);
574  if (irq < 0) {
575  dev_err(dev, "no irq specified\n");
576  return irq;
577  }
578 
579  host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
580  if (IS_ERR(host)) {
581  dev_err(dev, "sdhci_alloc_host() failed\n");
582  return PTR_ERR(host);
583  }
584  sc = sdhci_priv(host);
585 
586  pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
587  if (!pdata) {
588  ret = -ENOMEM;
589  goto err_pdata;
590  }
591 
592  if (pdev->dev.of_node) {
593  ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
594  if (ret)
595  goto err_pdata;
596  } else {
597  memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
598  sc->ext_cd_gpio = -1; /* invalid gpio number */
599  }
600 
601  drv_data = sdhci_s3c_get_driver_data(pdev);
602 
603  sc->host = host;
604  sc->pdev = pdev;
605  sc->pdata = pdata;
606 
607  platform_set_drvdata(pdev, host);
608 
609  sc->clk_io = clk_get(dev, "hsmmc");
610  if (IS_ERR(sc->clk_io)) {
611  dev_err(dev, "failed to get io clock\n");
612  ret = PTR_ERR(sc->clk_io);
613  goto err_io_clk;
614  }
615 
616  /* enable the local io clock and keep it running for the moment. */
617  clk_prepare_enable(sc->clk_io);
618 
619  for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
620  struct clk *clk;
621  char name[14];
622 
623  snprintf(name, 14, "mmc_busclk.%d", ptr);
624  clk = clk_get(dev, name);
625  if (IS_ERR(clk))
626  continue;
627 
628  clks++;
629  sc->clk_bus[ptr] = clk;
630 
631  /*
632  * save current clock index to know which clock bus
633  * is used later in overriding functions.
634  */
635  sc->cur_clk = ptr;
636 
637  dev_info(dev, "clock source %d: %s (%ld Hz)\n",
638  ptr, name, clk_get_rate(clk));
639  }
640 
641  if (clks == 0) {
642  dev_err(dev, "failed to find any bus clocks\n");
643  ret = -ENOENT;
644  goto err_no_busclks;
645  }
646 
647 #ifndef CONFIG_PM_RUNTIME
648  clk_prepare_enable(sc->clk_bus[sc->cur_clk]);
649 #endif
650 
651  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652  host->ioaddr = devm_request_and_ioremap(&pdev->dev, res);
653  if (!host->ioaddr) {
654  dev_err(dev, "failed to map registers\n");
655  ret = -ENXIO;
656  goto err_req_regs;
657  }
658 
659  /* Ensure we have minimal gpio selected CMD/CLK/Detect */
660  if (pdata->cfg_gpio)
661  pdata->cfg_gpio(pdev, pdata->max_width);
662 
663  host->hw_name = "samsung-hsmmc";
664  host->ops = &sdhci_s3c_ops;
665  host->quirks = 0;
666  host->irq = irq;
667 
668  /* Setup quirks for the controller */
671  if (drv_data)
672  host->quirks |= drv_data->sdhci_quirks;
673 
674 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
675 
676  /* we currently see overruns on errors, so disable the SDMA
677  * support as well. */
679 
680 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
681 
682  /* It seems we do not get an DATA transfer complete on non-busy
683  * transfers, not sure if this is a problem with this specific
684  * SDHCI block, or a missing configuration that needs to be set. */
686 
687  /* This host supports the Auto CMD12 */
689 
690  /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
692 
693  if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
696 
697  if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
698  host->mmc->caps = MMC_CAP_NONREMOVABLE;
699 
700  switch (pdata->max_width) {
701  case 8:
702  host->mmc->caps |= MMC_CAP_8_BIT_DATA;
703  case 4:
704  host->mmc->caps |= MMC_CAP_4_BIT_DATA;
705  break;
706  }
707 
708  if (pdata->pm_caps)
709  host->mmc->pm_caps |= pdata->pm_caps;
710 
713 
714  /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
716 
717  /*
718  * If controller does not have internal clock divider,
719  * we can use overriding functions instead of default.
720  */
722  sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
723  sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
724  sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
725  }
726 
727  /* It supports additional host capabilities if needed */
728  if (pdata->host_caps)
729  host->mmc->caps |= pdata->host_caps;
730 
731  if (pdata->host_caps2)
732  host->mmc->caps2 |= pdata->host_caps2;
733 
734  pm_runtime_enable(&pdev->dev);
736  pm_runtime_use_autosuspend(&pdev->dev);
737  pm_suspend_ignore_children(&pdev->dev, 1);
738 
739  ret = sdhci_add_host(host);
740  if (ret) {
741  dev_err(dev, "sdhci_add_host() failed\n");
742  pm_runtime_forbid(&pdev->dev);
743  pm_runtime_get_noresume(&pdev->dev);
744  goto err_req_regs;
745  }
746 
747  /* The following two methods of card detection might call
748  sdhci_s3c_notify_change() immediately, so they can be called
749  only after sdhci_add_host(). Setup errors are ignored. */
750  if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
751  pdata->ext_cd_init(&sdhci_s3c_notify_change);
752  if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
753  gpio_is_valid(pdata->ext_cd_gpio))
754  sdhci_s3c_setup_card_detect_gpio(sc);
755 
756 #ifdef CONFIG_PM_RUNTIME
757  if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
758  clk_disable_unprepare(sc->clk_io);
759 #endif
760  return 0;
761 
762  err_req_regs:
763 #ifndef CONFIG_PM_RUNTIME
764  clk_disable_unprepare(sc->clk_bus[sc->cur_clk]);
765 #endif
766  for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
767  if (sc->clk_bus[ptr]) {
768  clk_put(sc->clk_bus[ptr]);
769  }
770  }
771 
772  err_no_busclks:
773  clk_disable_unprepare(sc->clk_io);
774  clk_put(sc->clk_io);
775 
776  err_io_clk:
777  for (ptr = 0; ptr < NUM_GPIOS(sc->pdata->max_width); ptr++)
778  gpio_free(sc->gpios[ptr]);
779  if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL)
780  gpio_free(sc->ext_cd_gpio);
781 
782  err_pdata:
783  sdhci_free_host(host);
784 
785  return ret;
786 }
787 
788 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
789 {
790  struct sdhci_host *host = platform_get_drvdata(pdev);
791  struct sdhci_s3c *sc = sdhci_priv(host);
792  struct s3c_sdhci_platdata *pdata = sc->pdata;
793  int ptr;
794 
795  if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
796  pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
797 
798  if (sc->ext_cd_irq)
799  free_irq(sc->ext_cd_irq, sc);
800 
801  if (gpio_is_valid(sc->ext_cd_gpio))
802  gpio_free(sc->ext_cd_gpio);
803 
804 #ifdef CONFIG_PM_RUNTIME
805  if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
806  clk_prepare_enable(sc->clk_io);
807 #endif
808  sdhci_remove_host(host, 1);
809 
810  pm_runtime_dont_use_autosuspend(&pdev->dev);
811  pm_runtime_disable(&pdev->dev);
812 
813 #ifndef CONFIG_PM_RUNTIME
814  clk_disable_unprepare(sc->clk_bus[sc->cur_clk]);
815 #endif
816  for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
817  if (sc->clk_bus[ptr]) {
818  clk_put(sc->clk_bus[ptr]);
819  }
820  }
821  clk_disable_unprepare(sc->clk_io);
822  clk_put(sc->clk_io);
823 
824  if (pdev->dev.of_node) {
825  for (ptr = 0; ptr < NUM_GPIOS(sc->pdata->max_width); ptr++)
826  gpio_free(sc->gpios[ptr]);
827  }
828 
829  sdhci_free_host(host);
830  platform_set_drvdata(pdev, NULL);
831 
832  return 0;
833 }
834 
835 #ifdef CONFIG_PM_SLEEP
836 static int sdhci_s3c_suspend(struct device *dev)
837 {
838  struct sdhci_host *host = dev_get_drvdata(dev);
839 
840  return sdhci_suspend_host(host);
841 }
842 
843 static int sdhci_s3c_resume(struct device *dev)
844 {
845  struct sdhci_host *host = dev_get_drvdata(dev);
846 
847  return sdhci_resume_host(host);
848 }
849 #endif
850 
851 #ifdef CONFIG_PM_RUNTIME
852 static int sdhci_s3c_runtime_suspend(struct device *dev)
853 {
854  struct sdhci_host *host = dev_get_drvdata(dev);
855  struct sdhci_s3c *ourhost = to_s3c(host);
856  struct clk *busclk = ourhost->clk_io;
857  int ret;
858 
859  ret = sdhci_runtime_suspend_host(host);
860 
861  clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
862  clk_disable_unprepare(busclk);
863  return ret;
864 }
865 
866 static int sdhci_s3c_runtime_resume(struct device *dev)
867 {
868  struct sdhci_host *host = dev_get_drvdata(dev);
869  struct sdhci_s3c *ourhost = to_s3c(host);
870  struct clk *busclk = ourhost->clk_io;
871  int ret;
872 
873  clk_prepare_enable(busclk);
874  clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
875  ret = sdhci_runtime_resume_host(host);
876  return ret;
877 }
878 #endif
879 
880 #ifdef CONFIG_PM
881 static const struct dev_pm_ops sdhci_s3c_pmops = {
882  SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
883  SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
884  NULL)
885 };
886 
887 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
888 
889 #else
890 #define SDHCI_S3C_PMOPS NULL
891 #endif
892 
893 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
894 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
896 };
897 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
898 #else
899 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
900 #endif
901 
902 static struct platform_device_id sdhci_s3c_driver_ids[] = {
903  {
904  .name = "s3c-sdhci",
905  .driver_data = (kernel_ulong_t)NULL,
906  }, {
907  .name = "exynos4-sdhci",
908  .driver_data = EXYNOS4_SDHCI_DRV_DATA,
909  },
910  { }
911 };
912 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
913 
914 #ifdef CONFIG_OF
915 static const struct of_device_id sdhci_s3c_dt_match[] = {
916  { .compatible = "samsung,s3c6410-sdhci", },
917  { .compatible = "samsung,exynos4210-sdhci",
918  .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
919  {},
920 };
921 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
922 #endif
923 
924 static struct platform_driver sdhci_s3c_driver = {
925  .probe = sdhci_s3c_probe,
926  .remove = __devexit_p(sdhci_s3c_remove),
927  .id_table = sdhci_s3c_driver_ids,
928  .driver = {
929  .owner = THIS_MODULE,
930  .name = "s3c-sdhci",
931  .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
932  .pm = SDHCI_S3C_PMOPS,
933  },
934 };
935 
936 module_platform_driver(sdhci_s3c_driver);
937 
938 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
939 MODULE_AUTHOR("Ben Dooks, <[email protected]>");
940 MODULE_LICENSE("GPL v2");
941 MODULE_ALIAS("platform:s3c-sdhci");