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#define | MMC_BUSMODE_OPENDRAIN 1 |
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#define | MMC_BUSMODE_PUSHPULL 2 |
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#define | MMC_CS_DONTCARE 0 |
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#define | MMC_CS_HIGH 1 |
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#define | MMC_CS_LOW 2 |
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#define | MMC_POWER_OFF 0 |
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#define | MMC_POWER_UP 1 |
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#define | MMC_POWER_ON 2 |
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#define | MMC_BUS_WIDTH_1 0 |
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#define | MMC_BUS_WIDTH_4 2 |
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#define | MMC_BUS_WIDTH_8 3 |
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#define | MMC_TIMING_LEGACY 0 |
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#define | MMC_TIMING_MMC_HS 1 |
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#define | MMC_TIMING_SD_HS 2 |
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#define | MMC_TIMING_UHS_SDR12 MMC_TIMING_LEGACY |
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#define | MMC_TIMING_UHS_SDR25 MMC_TIMING_SD_HS |
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#define | MMC_TIMING_UHS_SDR50 3 |
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#define | MMC_TIMING_UHS_SDR104 4 |
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#define | MMC_TIMING_UHS_DDR50 5 |
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#define | MMC_TIMING_MMC_HS200 6 |
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#define | MMC_SDR_MODE 0 |
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#define | MMC_1_2V_DDR_MODE 1 |
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#define | MMC_1_8V_DDR_MODE 2 |
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#define | MMC_1_2V_SDR_MODE 3 |
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#define | MMC_1_8V_SDR_MODE 4 |
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#define | MMC_SIGNAL_VOLTAGE_330 0 |
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#define | MMC_SIGNAL_VOLTAGE_180 1 |
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#define | MMC_SIGNAL_VOLTAGE_120 2 |
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#define | MMC_SET_DRIVER_TYPE_B 0 |
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#define | MMC_SET_DRIVER_TYPE_A 1 |
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#define | MMC_SET_DRIVER_TYPE_C 2 |
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#define | MMC_SET_DRIVER_TYPE_D 3 |
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#define | MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
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#define | MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ |
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#define | MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ |
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#define | MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ |
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#define | MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ |
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#define | MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ |
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#define | MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ |
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#define | MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ |
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#define | MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ |
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#define | MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ |
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#define | MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ |
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#define | MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ |
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#define | MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ |
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#define | MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ |
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#define | MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ |
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#define | MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ |
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#define | MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ |
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#define | MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ |
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#define | MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ |
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#define | MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ |
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#define | MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ |
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#define | MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ |
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#define | MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ |
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#define | MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ |
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#define | MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ |
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#define | MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ |
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#define | MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ |
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#define | MMC_CAP_1_8V_DDR (1 << 11) /* can support */ |
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#define | MMC_CAP_1_2V_DDR (1 << 12) /* can support */ |
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#define | MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ |
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#define | MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ |
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#define | MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ |
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#define | MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ |
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#define | MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ |
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#define | MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ |
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#define | MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ |
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#define | MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ |
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#define | MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ |
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#define | MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ |
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#define | MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ |
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#define | MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ |
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#define | MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ |
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#define | MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */ |
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#define | MMC_CAP2_POWEROFF_NOTIFY (1 << 2) /* Notify poweroff supported */ |
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#define | MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */ |
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#define | MMC_CAP2_NO_SLEEP_CMD (1 << 4) /* Don't allow sleep command */ |
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#define | MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ |
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#define | MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ |
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#define | MMC_CAP2_HS200 |
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#define | MMC_CAP2_BROKEN_VOLTAGE (1 << 7) /* Use the broken voltage */ |
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#define | MMC_CAP2_DETECT_ON_ERR (1 << 8) /* On I/O err check card removal */ |
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#define | MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ |
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#define | MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ |
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#define | MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ |
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#define | mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) |
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#define | mmc_dev(x) ((x)->parent) |
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#define | mmc_classdev(x) (&(x)->class_dev) |
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#define | mmc_hostname(x) (dev_name(&(x)->class_dev)) |
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