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setup-bus.c
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1 /*
2  * drivers/pci/setup-bus.c
3  *
4  * Extruded from code written by
5  * Dave Rusling ([email protected])
6  * David Mosberger ([email protected])
7  * David Miller ([email protected])
8  *
9  * Support routines for initializing a PCI subsystem.
10  */
11 
12 /*
13  * Nov 2000, Ivan Kokshaysky <[email protected]>
14  * PCI-PCI bridges cleanup, sorted resource allocation.
15  * Feb 2002, Ivan Kokshaysky <[email protected]>
16  * Converted to allocation in 3 passes, which gives
17  * tighter packing. Prefetchable range support.
18  */
19 
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28 #include <asm-generic/pci-bridge.h>
29 #include "pci.h"
30 
31 unsigned int pci_flags;
32 
34  struct list_head list;
35  struct resource *res;
36  struct pci_dev *dev;
41  unsigned long flags;
42 };
43 
44 static void free_list(struct list_head *head)
45 {
46  struct pci_dev_resource *dev_res, *tmp;
47 
48  list_for_each_entry_safe(dev_res, tmp, head, list) {
49  list_del(&dev_res->list);
50  kfree(dev_res);
51  }
52 }
53 
63 static int add_to_list(struct list_head *head,
64  struct pci_dev *dev, struct resource *res,
66 {
67  struct pci_dev_resource *tmp;
68 
69  tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70  if (!tmp) {
71  pr_warning("add_to_list: kmalloc() failed!\n");
72  return -ENOMEM;
73  }
74 
75  tmp->res = res;
76  tmp->dev = dev;
77  tmp->start = res->start;
78  tmp->end = res->end;
79  tmp->flags = res->flags;
80  tmp->add_size = add_size;
81  tmp->min_align = min_align;
82 
83  list_add(&tmp->list, head);
84 
85  return 0;
86 }
87 
88 static void remove_from_list(struct list_head *head,
89  struct resource *res)
90 {
91  struct pci_dev_resource *dev_res, *tmp;
92 
93  list_for_each_entry_safe(dev_res, tmp, head, list) {
94  if (dev_res->res == res) {
95  list_del(&dev_res->list);
96  kfree(dev_res);
97  break;
98  }
99  }
100 }
101 
102 static resource_size_t get_res_add_size(struct list_head *head,
103  struct resource *res)
104 {
105  struct pci_dev_resource *dev_res;
106 
107  list_for_each_entry(dev_res, head, list) {
108  if (dev_res->res == res) {
109  int idx = res - &dev_res->dev->resource[0];
110 
111  dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112  "res[%d]=%pR get_res_add_size add_size %llx\n",
113  idx, dev_res->res,
114  (unsigned long long)dev_res->add_size);
115 
116  return dev_res->add_size;
117  }
118  }
119 
120  return 0;
121 }
122 
123 /* Sort resources by alignment */
124 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
125 {
126  int i;
127 
128  for (i = 0; i < PCI_NUM_RESOURCES; i++) {
129  struct resource *r;
130  struct pci_dev_resource *dev_res, *tmp;
131  resource_size_t r_align;
132  struct list_head *n;
133 
134  r = &dev->resource[i];
135 
136  if (r->flags & IORESOURCE_PCI_FIXED)
137  continue;
138 
139  if (!(r->flags) || r->parent)
140  continue;
141 
142  r_align = pci_resource_alignment(dev, r);
143  if (!r_align) {
144  dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
145  i, r);
146  continue;
147  }
148 
149  tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
150  if (!tmp)
151  panic("pdev_sort_resources(): "
152  "kmalloc() failed!\n");
153  tmp->res = r;
154  tmp->dev = dev;
155 
156  /* fallback is smallest one or list is empty*/
157  n = head;
158  list_for_each_entry(dev_res, head, list) {
160 
161  align = pci_resource_alignment(dev_res->dev,
162  dev_res->res);
163 
164  if (r_align > align) {
165  n = &dev_res->list;
166  break;
167  }
168  }
169  /* Insert it just before n*/
170  list_add_tail(&tmp->list, n);
171  }
172 }
173 
174 static void __dev_sort_resources(struct pci_dev *dev,
175  struct list_head *head)
176 {
177  u16 class = dev->class >> 8;
178 
179  /* Don't touch classless devices or host bridges or ioapics. */
180  if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
181  return;
182 
183  /* Don't touch ioapic devices already enabled by firmware */
184  if (class == PCI_CLASS_SYSTEM_PIC) {
185  u16 command;
186  pci_read_config_word(dev, PCI_COMMAND, &command);
187  if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
188  return;
189  }
190 
191  pdev_sort_resources(dev, head);
192 }
193 
194 static inline void reset_resource(struct resource *res)
195 {
196  res->start = 0;
197  res->end = 0;
198  res->flags = 0;
199 }
200 
213 static void reassign_resources_sorted(struct list_head *realloc_head,
214  struct list_head *head)
215 {
216  struct resource *res;
217  struct pci_dev_resource *add_res, *tmp;
218  struct pci_dev_resource *dev_res;
220  int idx;
221 
222  list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223  bool found_match = false;
224 
225  res = add_res->res;
226  /* skip resource that has been reset */
227  if (!res->flags)
228  goto out;
229 
230  /* skip this resource if not found in head list */
231  list_for_each_entry(dev_res, head, list) {
232  if (dev_res->res == res) {
233  found_match = true;
234  break;
235  }
236  }
237  if (!found_match)/* just skip */
238  continue;
239 
240  idx = res - &add_res->dev->resource[0];
241  add_size = add_res->add_size;
242  if (!resource_size(res)) {
243  res->start = add_res->start;
244  res->end = res->start + add_size - 1;
245  if (pci_assign_resource(add_res->dev, idx))
246  reset_resource(res);
247  } else {
248  resource_size_t align = add_res->min_align;
249  res->flags |= add_res->flags &
251  if (pci_reassign_resource(add_res->dev, idx,
252  add_size, align))
253  dev_printk(KERN_DEBUG, &add_res->dev->dev,
254  "failed to add %llx res[%d]=%pR\n",
255  (unsigned long long)add_size,
256  idx, res);
257  }
258 out:
259  list_del(&add_res->list);
260  kfree(add_res);
261  }
262 }
263 
274 static void assign_requested_resources_sorted(struct list_head *head,
275  struct list_head *fail_head)
276 {
277  struct resource *res;
278  struct pci_dev_resource *dev_res;
279  int idx;
280 
281  list_for_each_entry(dev_res, head, list) {
282  res = dev_res->res;
283  idx = res - &dev_res->dev->resource[0];
284  if (resource_size(res) &&
285  pci_assign_resource(dev_res->dev, idx)) {
286  if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) {
287  /*
288  * if the failed res is for ROM BAR, and it will
289  * be enabled later, don't add it to the list
290  */
291  if (!((idx == PCI_ROM_RESOURCE) &&
292  (!(res->flags & IORESOURCE_ROM_ENABLE))))
293  add_to_list(fail_head,
294  dev_res->dev, res,
295  0 /* dont care */,
296  0 /* dont care */);
297  }
298  reset_resource(res);
299  }
300  }
301 }
302 
303 static void __assign_resources_sorted(struct list_head *head,
304  struct list_head *realloc_head,
305  struct list_head *fail_head)
306 {
307  /*
308  * Should not assign requested resources at first.
309  * they could be adjacent, so later reassign can not reallocate
310  * them one by one in parent resource window.
311  * Try to assign requested + add_size at beginning
312  * if could do that, could get out early.
313  * if could not do that, we still try to assign requested at first,
314  * then try to reassign add_size for some resources.
315  */
316  LIST_HEAD(save_head);
317  LIST_HEAD(local_fail_head);
318  struct pci_dev_resource *save_res;
319  struct pci_dev_resource *dev_res;
320 
321  /* Check if optional add_size is there */
322  if (!realloc_head || list_empty(realloc_head))
323  goto requested_and_reassign;
324 
325  /* Save original start, end, flags etc at first */
326  list_for_each_entry(dev_res, head, list) {
327  if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
328  free_list(&save_head);
329  goto requested_and_reassign;
330  }
331  }
332 
333  /* Update res in head list with add_size in realloc_head list */
334  list_for_each_entry(dev_res, head, list)
335  dev_res->res->end += get_res_add_size(realloc_head,
336  dev_res->res);
337 
338  /* Try updated head list with add_size added */
339  assign_requested_resources_sorted(head, &local_fail_head);
340 
341  /* all assigned with add_size ? */
342  if (list_empty(&local_fail_head)) {
343  /* Remove head list from realloc_head list */
344  list_for_each_entry(dev_res, head, list)
345  remove_from_list(realloc_head, dev_res->res);
346  free_list(&save_head);
347  free_list(head);
348  return;
349  }
350 
351  free_list(&local_fail_head);
352  /* Release assigned resource */
353  list_for_each_entry(dev_res, head, list)
354  if (dev_res->res->parent)
355  release_resource(dev_res->res);
356  /* Restore start/end/flags from saved list */
357  list_for_each_entry(save_res, &save_head, list) {
358  struct resource *res = save_res->res;
359 
360  res->start = save_res->start;
361  res->end = save_res->end;
362  res->flags = save_res->flags;
363  }
364  free_list(&save_head);
365 
366 requested_and_reassign:
367  /* Satisfy the must-have resource requests */
368  assign_requested_resources_sorted(head, fail_head);
369 
370  /* Try to satisfy any additional optional resource
371  requests */
372  if (realloc_head)
373  reassign_resources_sorted(realloc_head, head);
374  free_list(head);
375 }
376 
377 static void pdev_assign_resources_sorted(struct pci_dev *dev,
378  struct list_head *add_head,
379  struct list_head *fail_head)
380 {
381  LIST_HEAD(head);
382 
383  __dev_sort_resources(dev, &head);
384  __assign_resources_sorted(&head, add_head, fail_head);
385 
386 }
387 
388 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
389  struct list_head *realloc_head,
390  struct list_head *fail_head)
391 {
392  struct pci_dev *dev;
393  LIST_HEAD(head);
394 
396  __dev_sort_resources(dev, &head);
397 
398  __assign_resources_sorted(&head, realloc_head, fail_head);
399 }
400 
402 {
403  struct pci_dev *bridge = bus->self;
404  struct resource *res;
405  struct pci_bus_region region;
406 
407  dev_info(&bridge->dev, "CardBus bridge to %pR\n",
408  &bus->busn_res);
409 
410  res = bus->resource[0];
411  pcibios_resource_to_bus(bridge, &region, res);
412  if (res->flags & IORESOURCE_IO) {
413  /*
414  * The IO resource is allocated a range twice as large as it
415  * would normally need. This allows us to set both IO regs.
416  */
417  dev_info(&bridge->dev, " bridge window %pR\n", res);
418  pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
419  region.start);
420  pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
421  region.end);
422  }
423 
424  res = bus->resource[1];
425  pcibios_resource_to_bus(bridge, &region, res);
426  if (res->flags & IORESOURCE_IO) {
427  dev_info(&bridge->dev, " bridge window %pR\n", res);
428  pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
429  region.start);
430  pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
431  region.end);
432  }
433 
434  res = bus->resource[2];
435  pcibios_resource_to_bus(bridge, &region, res);
436  if (res->flags & IORESOURCE_MEM) {
437  dev_info(&bridge->dev, " bridge window %pR\n", res);
438  pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
439  region.start);
440  pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
441  region.end);
442  }
443 
444  res = bus->resource[3];
445  pcibios_resource_to_bus(bridge, &region, res);
446  if (res->flags & IORESOURCE_MEM) {
447  dev_info(&bridge->dev, " bridge window %pR\n", res);
448  pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
449  region.start);
450  pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
451  region.end);
452  }
453 }
455 
456 /* Initialize bridges with base/limit values we have collected.
457  PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
458  requires that if there is no I/O ports or memory behind the
459  bridge, corresponding range must be turned off by writing base
460  value greater than limit to the bridge's base/limit registers.
461 
462  Note: care must be taken when updating I/O base/limit registers
463  of bridges which support 32-bit I/O. This update requires two
464  config space writes, so it's quite possible that an I/O window of
465  the bridge will have some undesirable address (e.g. 0) after the
466  first write. Ditto 64-bit prefetchable MMIO. */
467 static void pci_setup_bridge_io(struct pci_bus *bus)
468 {
469  struct pci_dev *bridge = bus->self;
470  struct resource *res;
471  struct pci_bus_region region;
472  unsigned long io_mask;
473  u8 io_base_lo, io_limit_lo;
474  u32 l, io_upper16;
475 
476  io_mask = PCI_IO_RANGE_MASK;
477  if (bridge->io_window_1k)
478  io_mask = PCI_IO_1K_RANGE_MASK;
479 
480  /* Set up the top and bottom of the PCI I/O segment for this bus. */
481  res = bus->resource[0];
482  pcibios_resource_to_bus(bridge, &region, res);
483  if (res->flags & IORESOURCE_IO) {
484  pci_read_config_dword(bridge, PCI_IO_BASE, &l);
485  l &= 0xffff0000;
486  io_base_lo = (region.start >> 8) & io_mask;
487  io_limit_lo = (region.end >> 8) & io_mask;
488  l |= ((u32) io_limit_lo << 8) | io_base_lo;
489  /* Set up upper 16 bits of I/O base/limit. */
490  io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
491  dev_info(&bridge->dev, " bridge window %pR\n", res);
492  } else {
493  /* Clear upper 16 bits of I/O base/limit. */
494  io_upper16 = 0;
495  l = 0x00f0;
496  }
497  /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
498  pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
499  /* Update lower 16 bits of I/O base/limit. */
500  pci_write_config_dword(bridge, PCI_IO_BASE, l);
501  /* Update upper 16 bits of I/O base/limit. */
502  pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
503 }
504 
505 static void pci_setup_bridge_mmio(struct pci_bus *bus)
506 {
507  struct pci_dev *bridge = bus->self;
508  struct resource *res;
509  struct pci_bus_region region;
510  u32 l;
511 
512  /* Set up the top and bottom of the PCI Memory segment for this bus. */
513  res = bus->resource[1];
514  pcibios_resource_to_bus(bridge, &region, res);
515  if (res->flags & IORESOURCE_MEM) {
516  l = (region.start >> 16) & 0xfff0;
517  l |= region.end & 0xfff00000;
518  dev_info(&bridge->dev, " bridge window %pR\n", res);
519  } else {
520  l = 0x0000fff0;
521  }
522  pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
523 }
524 
525 static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
526 {
527  struct pci_dev *bridge = bus->self;
528  struct resource *res;
529  struct pci_bus_region region;
530  u32 l, bu, lu;
531 
532  /* Clear out the upper 32 bits of PREF limit.
533  If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
534  disables PREF range, which is ok. */
535  pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
536 
537  /* Set up PREF base/limit. */
538  bu = lu = 0;
539  res = bus->resource[2];
540  pcibios_resource_to_bus(bridge, &region, res);
541  if (res->flags & IORESOURCE_PREFETCH) {
542  l = (region.start >> 16) & 0xfff0;
543  l |= region.end & 0xfff00000;
544  if (res->flags & IORESOURCE_MEM_64) {
545  bu = upper_32_bits(region.start);
546  lu = upper_32_bits(region.end);
547  }
548  dev_info(&bridge->dev, " bridge window %pR\n", res);
549  } else {
550  l = 0x0000fff0;
551  }
552  pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
553 
554  /* Set the upper 32 bits of PREF base & limit. */
555  pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
556  pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
557 }
558 
559 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
560 {
561  struct pci_dev *bridge = bus->self;
562 
563  dev_info(&bridge->dev, "PCI bridge to %pR\n",
564  &bus->busn_res);
565 
566  if (type & IORESOURCE_IO)
567  pci_setup_bridge_io(bus);
568 
569  if (type & IORESOURCE_MEM)
570  pci_setup_bridge_mmio(bus);
571 
572  if (type & IORESOURCE_PREFETCH)
573  pci_setup_bridge_mmio_pref(bus);
574 
575  pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
576 }
577 
578 void pci_setup_bridge(struct pci_bus *bus)
579 {
580  unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
582 
583  __pci_setup_bridge(bus, type);
584 }
585 
586 /* Check whether the bridge supports optional I/O and
587  prefetchable memory ranges. If not, the respective
588  base/limit registers must be read-only and read as 0. */
589 static void pci_bridge_check_ranges(struct pci_bus *bus)
590 {
591  u16 io;
592  u32 pmem;
593  struct pci_dev *bridge = bus->self;
594  struct resource *b_res;
595 
596  b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
597  b_res[1].flags |= IORESOURCE_MEM;
598 
599  pci_read_config_word(bridge, PCI_IO_BASE, &io);
600  if (!io) {
601  pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
602  pci_read_config_word(bridge, PCI_IO_BASE, &io);
603  pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
604  }
605  if (io)
606  b_res[0].flags |= IORESOURCE_IO;
607  /* DECchip 21050 pass 2 errata: the bridge may miss an address
608  disconnect boundary by one PCI data phase.
609  Workaround: do not use prefetching on this device. */
610  if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
611  return;
612  pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
613  if (!pmem) {
614  pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
615  0xfff0fff0);
616  pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
617  pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
618  }
619  if (pmem) {
620  b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
621  if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
623  b_res[2].flags |= IORESOURCE_MEM_64;
624  b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
625  }
626  }
627 
628  /* double check if bridge does support 64 bit pref */
629  if (b_res[2].flags & IORESOURCE_MEM_64) {
630  u32 mem_base_hi, tmp;
631  pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
632  &mem_base_hi);
633  pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
634  0xffffffff);
635  pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
636  if (!tmp)
637  b_res[2].flags &= ~IORESOURCE_MEM_64;
638  pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
639  mem_base_hi);
640  }
641 }
642 
643 /* Helper function for sizing routines: find first available
644  bus resource of a given type. Note: we intentionally skip
645  the bus resources which have already been assigned (that is,
646  have non-NULL parent resource). */
647 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
648 {
649  int i;
650  struct resource *r;
651  unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
653 
654  pci_bus_for_each_resource(bus, r, i) {
655  if (r == &ioport_resource || r == &iomem_resource)
656  continue;
657  if (r && (r->flags & type_mask) == type && !r->parent)
658  return r;
659  }
660  return NULL;
661 }
662 
663 static resource_size_t calculate_iosize(resource_size_t size,
664  resource_size_t min_size,
665  resource_size_t size1,
667  resource_size_t align)
668 {
669  if (size < min_size)
670  size = min_size;
671  if (old_size == 1 )
672  old_size = 0;
673  /* To be fixed in 2.5: we should have sort of HAVE_ISA
674  flag in the struct pci_bus. */
675 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
676  size = (size & 0xff) + ((size & ~0xffUL) << 2);
677 #endif
678  size = ALIGN(size + size1, align);
679  if (size < old_size)
680  size = old_size;
681  return size;
682 }
683 
684 static resource_size_t calculate_memsize(resource_size_t size,
685  resource_size_t min_size,
686  resource_size_t size1,
687  resource_size_t old_size,
688  resource_size_t align)
689 {
690  if (size < min_size)
691  size = min_size;
692  if (old_size == 1 )
693  old_size = 0;
694  if (size < old_size)
695  size = old_size;
696  size = ALIGN(size + size1, align);
697  return size;
698 }
699 
701  unsigned long type)
702 {
703  return 1;
704 }
705 
706 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
707 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
708 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
709 
710 static resource_size_t window_alignment(struct pci_bus *bus,
711  unsigned long type)
712 {
713  resource_size_t align = 1, arch_align;
714 
715  if (type & IORESOURCE_MEM)
717  else if (type & IORESOURCE_IO) {
718  /*
719  * Per spec, I/O windows are 4K-aligned, but some
720  * bridges have an extension to support 1K alignment.
721  */
722  if (bus->self->io_window_1k)
724  else
725  align = PCI_P2P_DEFAULT_IO_ALIGN;
726  }
727 
728  arch_align = pcibios_window_alignment(bus, type);
729  return max(align, arch_align);
730 }
731 
745 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
746  resource_size_t add_size, struct list_head *realloc_head)
747 {
748  struct pci_dev *dev;
749  struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
750  unsigned long size = 0, size0 = 0, size1 = 0;
751  resource_size_t children_add_size = 0;
752  resource_size_t min_align, io_align, align;
753 
754  if (!b_res)
755  return;
756 
757  io_align = min_align = window_alignment(bus, IORESOURCE_IO);
758  list_for_each_entry(dev, &bus->devices, bus_list) {
759  int i;
760 
761  for (i = 0; i < PCI_NUM_RESOURCES; i++) {
762  struct resource *r = &dev->resource[i];
763  unsigned long r_size;
764 
765  if (r->parent || !(r->flags & IORESOURCE_IO))
766  continue;
767  r_size = resource_size(r);
768 
769  if (r_size < 0x400)
770  /* Might be re-aligned for ISA */
771  size += r_size;
772  else
773  size1 += r_size;
774 
775  align = pci_resource_alignment(dev, r);
776  if (align > min_align)
777  min_align = align;
778 
779  if (realloc_head)
780  children_add_size += get_res_add_size(realloc_head, r);
781  }
782  }
783 
784  if (min_align > io_align)
785  min_align = io_align;
786 
787  size0 = calculate_iosize(size, min_size, size1,
788  resource_size(b_res), min_align);
789  if (children_add_size > add_size)
790  add_size = children_add_size;
791  size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
792  calculate_iosize(size, min_size, add_size + size1,
793  resource_size(b_res), min_align);
794  if (!size0 && !size1) {
795  if (b_res->start || b_res->end)
796  dev_info(&bus->self->dev, "disabling bridge window "
797  "%pR to %pR (unused)\n", b_res,
798  &bus->busn_res);
799  b_res->flags = 0;
800  return;
801  }
802 
803  b_res->start = min_align;
804  b_res->end = b_res->start + size0 - 1;
805  b_res->flags |= IORESOURCE_STARTALIGN;
806  if (size1 > size0 && realloc_head) {
807  add_to_list(realloc_head, bus->self, b_res, size1-size0,
808  min_align);
809  dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
810  "%pR to %pR add_size %lx\n", b_res,
811  &bus->busn_res, size1-size0);
812  }
813 }
814 
815 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
816  int max_order)
817 {
818  resource_size_t align = 0;
819  resource_size_t min_align = 0;
820  int order;
821 
822  for (order = 0; order <= max_order; order++) {
823  resource_size_t align1 = 1;
824 
825  align1 <<= (order + 20);
826 
827  if (!align)
828  min_align = align1;
829  else if (ALIGN(align + min_align, min_align) < align1)
830  min_align = align1 >> 1;
831  align += aligns[order];
832  }
833 
834  return min_align;
835 }
836 
848 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
849  unsigned long type, resource_size_t min_size,
850  resource_size_t add_size,
851  struct list_head *realloc_head)
852 {
853  struct pci_dev *dev;
854  resource_size_t min_align, align, size, size0, size1;
855  resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
856  int order, max_order;
857  struct resource *b_res = find_free_bus_resource(bus, type);
858  unsigned int mem64_mask = 0;
859  resource_size_t children_add_size = 0;
860 
861  if (!b_res)
862  return 0;
863 
864  memset(aligns, 0, sizeof(aligns));
865  max_order = 0;
866  size = 0;
867 
868  mem64_mask = b_res->flags & IORESOURCE_MEM_64;
869  b_res->flags &= ~IORESOURCE_MEM_64;
870 
871  list_for_each_entry(dev, &bus->devices, bus_list) {
872  int i;
873 
874  for (i = 0; i < PCI_NUM_RESOURCES; i++) {
875  struct resource *r = &dev->resource[i];
876  resource_size_t r_size;
877 
878  if (r->parent || (r->flags & mask) != type)
879  continue;
880  r_size = resource_size(r);
881 #ifdef CONFIG_PCI_IOV
882  /* put SRIOV requested res to the optional list */
883  if (realloc_head && i >= PCI_IOV_RESOURCES &&
884  i <= PCI_IOV_RESOURCE_END) {
885  r->end = r->start - 1;
886  add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
887  children_add_size += r_size;
888  continue;
889  }
890 #endif
891  /* For bridges size != alignment */
892  align = pci_resource_alignment(dev, r);
893  order = __ffs(align) - 20;
894  if (order > 11) {
895  dev_warn(&dev->dev, "disabling BAR %d: %pR "
896  "(bad alignment %#llx)\n", i, r,
897  (unsigned long long) align);
898  r->flags = 0;
899  continue;
900  }
901  size += r_size;
902  if (order < 0)
903  order = 0;
904  /* Exclude ranges with size > align from
905  calculation of the alignment. */
906  if (r_size == align)
907  aligns[order] += align;
908  if (order > max_order)
909  max_order = order;
910  mem64_mask &= r->flags & IORESOURCE_MEM_64;
911 
912  if (realloc_head)
913  children_add_size += get_res_add_size(realloc_head, r);
914  }
915  }
916 
917  min_align = calculate_mem_align(aligns, max_order);
918  min_align = max(min_align, window_alignment(bus, b_res->flags & mask));
919  size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
920  if (children_add_size > add_size)
921  add_size = children_add_size;
922  size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
923  calculate_memsize(size, min_size, add_size,
924  resource_size(b_res), min_align);
925  if (!size0 && !size1) {
926  if (b_res->start || b_res->end)
927  dev_info(&bus->self->dev, "disabling bridge window "
928  "%pR to %pR (unused)\n", b_res,
929  &bus->busn_res);
930  b_res->flags = 0;
931  return 1;
932  }
933  b_res->start = min_align;
934  b_res->end = size0 + min_align - 1;
935  b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
936  if (size1 > size0 && realloc_head) {
937  add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
938  dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
939  "%pR to %pR add_size %llx\n", b_res,
940  &bus->busn_res, (unsigned long long)size1-size0);
941  }
942  return 1;
943 }
944 
945 unsigned long pci_cardbus_resource_alignment(struct resource *res)
946 {
947  if (res->flags & IORESOURCE_IO)
948  return pci_cardbus_io_size;
949  if (res->flags & IORESOURCE_MEM)
950  return pci_cardbus_mem_size;
951  return 0;
952 }
953 
954 static void pci_bus_size_cardbus(struct pci_bus *bus,
955  struct list_head *realloc_head)
956 {
957  struct pci_dev *bridge = bus->self;
958  struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
959  resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
960  u16 ctrl;
961 
962  if (b_res[0].parent)
963  goto handle_b_res_1;
964  /*
965  * Reserve some resources for CardBus. We reserve
966  * a fixed amount of bus space for CardBus bridges.
967  */
968  b_res[0].start = pci_cardbus_io_size;
969  b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
970  b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
971  if (realloc_head) {
972  b_res[0].end -= pci_cardbus_io_size;
973  add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
975  }
976 
977 handle_b_res_1:
978  if (b_res[1].parent)
979  goto handle_b_res_2;
980  b_res[1].start = pci_cardbus_io_size;
981  b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
982  b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
983  if (realloc_head) {
984  b_res[1].end -= pci_cardbus_io_size;
985  add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
987  }
988 
989 handle_b_res_2:
990  /* MEM1 must not be pref mmio */
991  pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
992  if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
993  ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
994  pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
995  pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
996  }
997 
998  /*
999  * Check whether prefetchable memory is supported
1000  * by this bridge.
1001  */
1002  pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1003  if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1005  pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1006  pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1007  }
1008 
1009  if (b_res[2].parent)
1010  goto handle_b_res_3;
1011  /*
1012  * If we have prefetchable memory support, allocate
1013  * two regions. Otherwise, allocate one region of
1014  * twice the size.
1015  */
1016  if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1017  b_res[2].start = pci_cardbus_mem_size;
1018  b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1019  b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1021  if (realloc_head) {
1022  b_res[2].end -= pci_cardbus_mem_size;
1023  add_to_list(realloc_head, bridge, b_res+2,
1025  }
1026 
1027  /* reduce that to half */
1028  b_res_3_size = pci_cardbus_mem_size;
1029  }
1030 
1031 handle_b_res_3:
1032  if (b_res[3].parent)
1033  goto handle_done;
1034  b_res[3].start = pci_cardbus_mem_size;
1035  b_res[3].end = b_res[3].start + b_res_3_size - 1;
1036  b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1037  if (realloc_head) {
1038  b_res[3].end -= b_res_3_size;
1039  add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1041  }
1042 
1043 handle_done:
1044  ;
1045 }
1046 
1048  struct list_head *realloc_head)
1049 {
1050  struct pci_dev *dev;
1051  unsigned long mask, prefmask;
1052  resource_size_t additional_mem_size = 0, additional_io_size = 0;
1053 
1054  list_for_each_entry(dev, &bus->devices, bus_list) {
1055  struct pci_bus *b = dev->subordinate;
1056  if (!b)
1057  continue;
1058 
1059  switch (dev->class >> 8) {
1061  pci_bus_size_cardbus(b, realloc_head);
1062  break;
1063 
1064  case PCI_CLASS_BRIDGE_PCI:
1065  default:
1066  __pci_bus_size_bridges(b, realloc_head);
1067  break;
1068  }
1069  }
1070 
1071  /* The root bus? */
1072  if (!bus->self)
1073  return;
1074 
1075  switch (bus->self->class >> 8) {
1077  /* don't size cardbuses yet. */
1078  break;
1079 
1080  case PCI_CLASS_BRIDGE_PCI:
1081  pci_bridge_check_ranges(bus);
1082  if (bus->self->is_hotplug_bridge) {
1083  additional_io_size = pci_hotplug_io_size;
1084  additional_mem_size = pci_hotplug_mem_size;
1085  }
1086  /*
1087  * Follow thru
1088  */
1089  default:
1090  pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1091  additional_io_size, realloc_head);
1092  /* If the bridge supports prefetchable range, size it
1093  separately. If it doesn't, or its prefetchable window
1094  has already been allocated by arch code, try
1095  non-prefetchable range for both types of PCI memory
1096  resources. */
1097  mask = IORESOURCE_MEM;
1098  prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1099  if (pbus_size_mem(bus, prefmask, prefmask,
1100  realloc_head ? 0 : additional_mem_size,
1101  additional_mem_size, realloc_head))
1102  mask = prefmask; /* Success, size non-prefetch only. */
1103  else
1104  additional_mem_size += additional_mem_size;
1105  pbus_size_mem(bus, mask, IORESOURCE_MEM,
1106  realloc_head ? 0 : additional_mem_size,
1107  additional_mem_size, realloc_head);
1108  break;
1109  }
1110 }
1111 
1113 {
1115 }
1117 
1118 static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
1119  struct list_head *realloc_head,
1120  struct list_head *fail_head)
1121 {
1122  struct pci_bus *b;
1123  struct pci_dev *dev;
1124 
1125  pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1126 
1127  list_for_each_entry(dev, &bus->devices, bus_list) {
1128  b = dev->subordinate;
1129  if (!b)
1130  continue;
1131 
1132  __pci_bus_assign_resources(b, realloc_head, fail_head);
1133 
1134  switch (dev->class >> 8) {
1135  case PCI_CLASS_BRIDGE_PCI:
1136  if (!pci_is_enabled(dev))
1137  pci_setup_bridge(b);
1138  break;
1139 
1141  pci_setup_cardbus(b);
1142  break;
1143 
1144  default:
1145  dev_info(&dev->dev, "not setting up bridge for bus "
1146  "%04x:%02x\n", pci_domain_nr(b), b->number);
1147  break;
1148  }
1149  }
1150 }
1151 
1152 void __ref pci_bus_assign_resources(const struct pci_bus *bus)
1153 {
1154  __pci_bus_assign_resources(bus, NULL, NULL);
1155 }
1157 
1158 static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
1159  struct list_head *add_head,
1160  struct list_head *fail_head)
1161 {
1162  struct pci_bus *b;
1163 
1164  pdev_assign_resources_sorted((struct pci_dev *)bridge,
1165  add_head, fail_head);
1166 
1167  b = bridge->subordinate;
1168  if (!b)
1169  return;
1170 
1171  __pci_bus_assign_resources(b, add_head, fail_head);
1172 
1173  switch (bridge->class >> 8) {
1174  case PCI_CLASS_BRIDGE_PCI:
1175  pci_setup_bridge(b);
1176  break;
1177 
1179  pci_setup_cardbus(b);
1180  break;
1181 
1182  default:
1183  dev_info(&bridge->dev, "not setting up bridge for bus "
1184  "%04x:%02x\n", pci_domain_nr(b), b->number);
1185  break;
1186  }
1187 }
1188 static void pci_bridge_release_resources(struct pci_bus *bus,
1189  unsigned long type)
1190 {
1191  int idx;
1192  bool changed = false;
1193  struct pci_dev *dev;
1194  struct resource *r;
1195  unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1197 
1198  dev = bus->self;
1199  for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
1200  idx++) {
1201  r = &dev->resource[idx];
1202  if ((r->flags & type_mask) != type)
1203  continue;
1204  if (!r->parent)
1205  continue;
1206  /*
1207  * if there are children under that, we should release them
1208  * all
1209  */
1211  if (!release_resource(r)) {
1212  dev_printk(KERN_DEBUG, &dev->dev,
1213  "resource %d %pR released\n", idx, r);
1214  /* keep the old size */
1215  r->end = resource_size(r) - 1;
1216  r->start = 0;
1217  r->flags = 0;
1218  changed = true;
1219  }
1220  }
1221 
1222  if (changed) {
1223  /* avoiding touch the one without PREF */
1224  if (type & IORESOURCE_PREFETCH)
1225  type = IORESOURCE_PREFETCH;
1226  __pci_setup_bridge(bus, type);
1227  }
1228 }
1229 
1233 };
1234 /*
1235  * try to release pci bridge resources that is from leaf bridge,
1236  * so we can allocate big new one later
1237  */
1238 static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1239  unsigned long type,
1240  enum release_type rel_type)
1241 {
1242  struct pci_dev *dev;
1243  bool is_leaf_bridge = true;
1244 
1245  list_for_each_entry(dev, &bus->devices, bus_list) {
1246  struct pci_bus *b = dev->subordinate;
1247  if (!b)
1248  continue;
1249 
1250  is_leaf_bridge = false;
1251 
1252  if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1253  continue;
1254 
1255  if (rel_type == whole_subtree)
1256  pci_bus_release_bridge_resources(b, type,
1257  whole_subtree);
1258  }
1259 
1260  if (pci_is_root_bus(bus))
1261  return;
1262 
1263  if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1264  return;
1265 
1266  if ((rel_type == whole_subtree) || is_leaf_bridge)
1267  pci_bridge_release_resources(bus, type);
1268 }
1269 
1270 static void pci_bus_dump_res(struct pci_bus *bus)
1271 {
1272  struct resource *res;
1273  int i;
1274 
1275  pci_bus_for_each_resource(bus, res, i) {
1276  if (!res || !res->end || !res->flags)
1277  continue;
1278 
1279  dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1280  }
1281 }
1282 
1283 static void pci_bus_dump_resources(struct pci_bus *bus)
1284 {
1285  struct pci_bus *b;
1286  struct pci_dev *dev;
1287 
1288 
1289  pci_bus_dump_res(bus);
1290 
1291  list_for_each_entry(dev, &bus->devices, bus_list) {
1292  b = dev->subordinate;
1293  if (!b)
1294  continue;
1295 
1296  pci_bus_dump_resources(b);
1297  }
1298 }
1299 
1300 static int __init pci_bus_get_depth(struct pci_bus *bus)
1301 {
1302  int depth = 0;
1303  struct pci_dev *dev;
1304 
1305  list_for_each_entry(dev, &bus->devices, bus_list) {
1306  int ret;
1307  struct pci_bus *b = dev->subordinate;
1308  if (!b)
1309  continue;
1310 
1311  ret = pci_bus_get_depth(b);
1312  if (ret + 1 > depth)
1313  depth = ret + 1;
1314  }
1315 
1316  return depth;
1317 }
1318 static int __init pci_get_max_depth(void)
1319 {
1320  int depth = 0;
1321  struct pci_bus *bus;
1322 
1323  list_for_each_entry(bus, &pci_root_buses, node) {
1324  int ret;
1325 
1326  ret = pci_bus_get_depth(bus);
1327  if (ret > depth)
1328  depth = ret;
1329  }
1330 
1331  return depth;
1332 }
1333 
1334 /*
1335  * -1: undefined, will auto detect later
1336  * 0: disabled by user
1337  * 1: disabled by auto detect
1338  * 2: enabled by user
1339  * 3: enabled by auto detect
1340  */
1347 };
1348 
1349 static enum enable_type pci_realloc_enable __initdata = undefined;
1351 {
1352  if (!strncmp(str, "off", 3))
1353  pci_realloc_enable = user_disabled;
1354  else if (!strncmp(str, "on", 2))
1355  pci_realloc_enable = user_enabled;
1356 }
1357 static bool __init pci_realloc_enabled(void)
1358 {
1359  return pci_realloc_enable >= user_enabled;
1360 }
1361 
1362 static void __init pci_realloc_detect(void)
1363 {
1364 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1365  struct pci_dev *dev = NULL;
1366 
1367  if (pci_realloc_enable != undefined)
1368  return;
1369 
1370  for_each_pci_dev(dev) {
1371  int i;
1372 
1373  for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1374  struct resource *r = &dev->resource[i];
1375 
1376  /* Not assigned, or rejected by kernel ? */
1377  if (r->flags && !r->start) {
1378  pci_realloc_enable = auto_enabled;
1379 
1380  return;
1381  }
1382  }
1383  }
1384 #endif
1385 }
1386 
1387 /*
1388  * first try will not touch pci bridge res
1389  * second and later try will clear small leaf bridge res
1390  * will stop till to the max deepth if can not find good one
1391  */
1392 void __init
1394 {
1395  struct pci_bus *bus;
1396  LIST_HEAD(realloc_head); /* list of resources that
1397  want additional resources */
1398  struct list_head *add_list = NULL;
1399  int tried_times = 0;
1400  enum release_type rel_type = leaf_only;
1401  LIST_HEAD(fail_head);
1402  struct pci_dev_resource *fail_res;
1403  unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1405  int pci_try_num = 1;
1406 
1407  /* don't realloc if asked to do so */
1408  pci_realloc_detect();
1409  if (pci_realloc_enabled()) {
1410  int max_depth = pci_get_max_depth();
1411 
1412  pci_try_num = max_depth + 1;
1413  printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1414  max_depth, pci_try_num);
1415  }
1416 
1417 again:
1418  /*
1419  * last try will use add_list, otherwise will try good to have as
1420  * must have, so can realloc parent bridge resource
1421  */
1422  if (tried_times + 1 == pci_try_num)
1423  add_list = &realloc_head;
1424  /* Depth first, calculate sizes and alignments of all
1425  subordinate buses. */
1426  list_for_each_entry(bus, &pci_root_buses, node)
1427  __pci_bus_size_bridges(bus, add_list);
1428 
1429  /* Depth last, allocate resources and update the hardware. */
1430  list_for_each_entry(bus, &pci_root_buses, node)
1431  __pci_bus_assign_resources(bus, add_list, &fail_head);
1432  if (add_list)
1433  BUG_ON(!list_empty(add_list));
1434  tried_times++;
1435 
1436  /* any device complain? */
1437  if (list_empty(&fail_head))
1438  goto enable_and_dump;
1439 
1440  if (tried_times >= pci_try_num) {
1441  if (pci_realloc_enable == undefined)
1442  printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1443  else if (pci_realloc_enable == auto_enabled)
1444  printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1445 
1446  free_list(&fail_head);
1447  goto enable_and_dump;
1448  }
1449 
1450  printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1451  tried_times + 1);
1452 
1453  /* third times and later will not check if it is leaf */
1454  if ((tried_times + 1) > 2)
1455  rel_type = whole_subtree;
1456 
1457  /*
1458  * Try to release leaf bridge's resources that doesn't fit resource of
1459  * child device under that bridge
1460  */
1461  list_for_each_entry(fail_res, &fail_head, list) {
1462  bus = fail_res->dev->bus;
1463  pci_bus_release_bridge_resources(bus,
1464  fail_res->flags & type_mask,
1465  rel_type);
1466  }
1467  /* restore size and flags */
1468  list_for_each_entry(fail_res, &fail_head, list) {
1469  struct resource *res = fail_res->res;
1470 
1471  res->start = fail_res->start;
1472  res->end = fail_res->end;
1473  res->flags = fail_res->flags;
1474  if (fail_res->dev->subordinate)
1475  res->flags = 0;
1476  }
1477  free_list(&fail_head);
1478 
1479  goto again;
1480 
1481 enable_and_dump:
1482  /* Depth last, update the hardware. */
1483  list_for_each_entry(bus, &pci_root_buses, node)
1484  pci_enable_bridges(bus);
1485 
1486  /* dump the resource on buses */
1487  list_for_each_entry(bus, &pci_root_buses, node)
1488  pci_bus_dump_resources(bus);
1489 }
1490 
1492 {
1493  struct pci_bus *parent = bridge->subordinate;
1494  LIST_HEAD(add_list); /* list of resources that
1495  want additional resources */
1496  int tried_times = 0;
1497  LIST_HEAD(fail_head);
1498  struct pci_dev_resource *fail_res;
1499  int retval;
1500  unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1502 
1503 again:
1504  __pci_bus_size_bridges(parent, &add_list);
1505  __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1506  BUG_ON(!list_empty(&add_list));
1507  tried_times++;
1508 
1509  if (list_empty(&fail_head))
1510  goto enable_all;
1511 
1512  if (tried_times >= 2) {
1513  /* still fail, don't need to try more */
1514  free_list(&fail_head);
1515  goto enable_all;
1516  }
1517 
1518  printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1519  tried_times + 1);
1520 
1521  /*
1522  * Try to release leaf bridge's resources that doesn't fit resource of
1523  * child device under that bridge
1524  */
1525  list_for_each_entry(fail_res, &fail_head, list) {
1526  struct pci_bus *bus = fail_res->dev->bus;
1527  unsigned long flags = fail_res->flags;
1528 
1529  pci_bus_release_bridge_resources(bus, flags & type_mask,
1530  whole_subtree);
1531  }
1532  /* restore size and flags */
1533  list_for_each_entry(fail_res, &fail_head, list) {
1534  struct resource *res = fail_res->res;
1535 
1536  res->start = fail_res->start;
1537  res->end = fail_res->end;
1538  res->flags = fail_res->flags;
1539  if (fail_res->dev->subordinate)
1540  res->flags = 0;
1541  }
1542  free_list(&fail_head);
1543 
1544  goto again;
1545 
1546 enable_all:
1547  retval = pci_reenable_device(bridge);
1548  pci_set_master(bridge);
1549  pci_enable_bridges(parent);
1550 }
1552 
1553 #ifdef CONFIG_HOTPLUG
1554 
1563 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1564 {
1565  unsigned int max;
1566  struct pci_dev *dev;
1567  LIST_HEAD(add_list); /* list of resources that
1568  want additional resources */
1569 
1570  max = pci_scan_child_bus(bus);
1571 
1572  down_read(&pci_bus_sem);
1573  list_for_each_entry(dev, &bus->devices, bus_list)
1574  if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1576  if (dev->subordinate)
1578  &add_list);
1579  up_read(&pci_bus_sem);
1580  __pci_bus_assign_resources(bus, &add_list, NULL);
1581  BUG_ON(!list_empty(&add_list));
1582 
1583  pci_enable_bridges(bus);
1584  pci_bus_add_devices(bus);
1585 
1586  return max;
1587 }
1588 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1589 #endif