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setup-sh7734.c
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1 /*
2  * arch/sh/kernel/cpu/sh4a/setup-sh7734.c
3 
4  * SH7734 Setup
5  *
6  * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <[email protected]>
7  * Copyright (C) 2011,2012 Renesas Solutions Corp.
8  *
9  * This file is subject to the terms and conditions of the GNU General Public
10  * License. See the file "COPYING" in the main directory of this archive
11  * for more details.
12  */
13 
14 #include <linux/platform_device.h>
15 #include <linux/init.h>
16 #include <linux/serial.h>
17 #include <linux/mm.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/serial_sci.h>
20 #include <linux/sh_timer.h>
21 #include <linux/io.h>
22 #include <asm/clock.h>
23 #include <asm/irq.h>
24 #include <cpu/sh7734.h>
25 
26 /* SCIF */
27 static struct plat_sci_port scif0_platform_data = {
28  .mapbase = 0xFFE40000,
29  .flags = UPF_BOOT_AUTOCONF,
30  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31  .scbrr_algo_id = SCBRR_ALGO_2,
32  .type = PORT_SCIF,
33  .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
34  .regtype = SCIx_SH4_SCIF_REGTYPE,
35 };
36 
37 static struct platform_device scif0_device = {
38  .name = "sh-sci",
39  .id = 0,
40  .dev = {
41  .platform_data = &scif0_platform_data,
42  },
43 };
44 
45 static struct plat_sci_port scif1_platform_data = {
46  .mapbase = 0xFFE41000,
47  .flags = UPF_BOOT_AUTOCONF,
48  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49  .scbrr_algo_id = SCBRR_ALGO_2,
50  .type = PORT_SCIF,
51  .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
52  .regtype = SCIx_SH4_SCIF_REGTYPE,
53 };
54 
55 static struct platform_device scif1_device = {
56  .name = "sh-sci",
57  .id = 1,
58  .dev = {
59  .platform_data = &scif1_platform_data,
60  },
61 };
62 
63 static struct plat_sci_port scif2_platform_data = {
64  .mapbase = 0xFFE42000,
65  .flags = UPF_BOOT_AUTOCONF,
66  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67  .scbrr_algo_id = SCBRR_ALGO_2,
68  .type = PORT_SCIF,
69  .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
70  .regtype = SCIx_SH4_SCIF_REGTYPE,
71 };
72 
73 static struct platform_device scif2_device = {
74  .name = "sh-sci",
75  .id = 2,
76  .dev = {
77  .platform_data = &scif2_platform_data,
78  },
79 };
80 
81 static struct plat_sci_port scif3_platform_data = {
82  .mapbase = 0xFFE43000,
83  .flags = UPF_BOOT_AUTOCONF,
84  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85  .scbrr_algo_id = SCBRR_ALGO_2,
86  .type = PORT_SCIF,
87  .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)),
88  .regtype = SCIx_SH4_SCIF_REGTYPE,
89 };
90 
91 static struct platform_device scif3_device = {
92  .name = "sh-sci",
93  .id = 3,
94  .dev = {
95  .platform_data = &scif3_platform_data,
96  },
97 };
98 
99 static struct plat_sci_port scif4_platform_data = {
100  .mapbase = 0xFFE44000,
101  .flags = UPF_BOOT_AUTOCONF,
102  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
103  .scbrr_algo_id = SCBRR_ALGO_2,
104  .type = PORT_SCIF,
105  .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)),
106  .regtype = SCIx_SH4_SCIF_REGTYPE,
107 };
108 
109 static struct platform_device scif4_device = {
110  .name = "sh-sci",
111  .id = 4,
112  .dev = {
113  .platform_data = &scif4_platform_data,
114  },
115 };
116 
117 static struct plat_sci_port scif5_platform_data = {
118  .mapbase = 0xFFE43000,
119  .flags = UPF_BOOT_AUTOCONF,
120  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121  .scbrr_algo_id = SCBRR_ALGO_2,
122  .type = PORT_SCIF,
123  .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)),
124  .regtype = SCIx_SH4_SCIF_REGTYPE,
125 };
126 
127 static struct platform_device scif5_device = {
128  .name = "sh-sci",
129  .id = 5,
130  .dev = {
131  .platform_data = &scif5_platform_data,
132  },
133 };
134 
135 /* RTC */
136 static struct resource rtc_resources[] = {
137  [0] = {
138  .name = "rtc",
139  .start = 0xFFFC5000,
140  .end = 0xFFFC5000 + 0x26 - 1,
141  .flags = IORESOURCE_IO,
142  },
143  [1] = {
144  .start = evt2irq(0xC00),
145  .flags = IORESOURCE_IRQ,
146  },
147 };
148 
149 static struct platform_device rtc_device = {
150  .name = "sh-rtc",
151  .id = -1,
152  .num_resources = ARRAY_SIZE(rtc_resources),
153  .resource = rtc_resources,
154 };
155 
156 /* I2C 0 */
157 static struct resource i2c0_resources[] = {
158  [0] = {
159  .name = "IIC0",
160  .start = 0xFFC70000,
161  .end = 0xFFC7000A - 1,
162  .flags = IORESOURCE_MEM,
163  },
164  [1] = {
165  .start = evt2irq(0x860),
166  .flags = IORESOURCE_IRQ,
167  },
168 };
169 
170 static struct platform_device i2c0_device = {
171  .name = "i2c-sh7734",
172  .id = 0,
173  .num_resources = ARRAY_SIZE(i2c0_resources),
174  .resource = i2c0_resources,
175 };
176 
177 /* TMU */
178 static struct sh_timer_config tmu0_platform_data = {
179  .channel_offset = 0x04,
180  .timer_bit = 0,
181  .clockevent_rating = 200,
182 };
183 
184 static struct resource tmu0_resources[] = {
185  [0] = {
186  .start = 0xFFD80008,
187  .end = 0xFFD80014 - 1,
188  .flags = IORESOURCE_MEM,
189  },
190  [1] = {
191  .start = evt2irq(0x400),
192  .flags = IORESOURCE_IRQ,
193  },
194 };
195 
196 static struct platform_device tmu0_device = {
197  .name = "sh_tmu",
198  .id = 0,
199  .dev = {
200  .platform_data = &tmu0_platform_data,
201  },
202  .resource = tmu0_resources,
203  .num_resources = ARRAY_SIZE(tmu0_resources),
204 };
205 
206 static struct sh_timer_config tmu1_platform_data = {
207  .channel_offset = 0x10,
208  .timer_bit = 1,
209  .clocksource_rating = 200,
210 };
211 
212 static struct resource tmu1_resources[] = {
213  [0] = {
214  .start = 0xFFD80014,
215  .end = 0xFFD80020 - 1,
216  .flags = IORESOURCE_MEM,
217  },
218  [1] = {
219  .start = evt2irq(0x420),
220  .flags = IORESOURCE_IRQ,
221  },
222 };
223 
224 static struct platform_device tmu1_device = {
225  .name = "sh_tmu",
226  .id = 1,
227  .dev = {
228  .platform_data = &tmu1_platform_data,
229  },
230  .resource = tmu1_resources,
231  .num_resources = ARRAY_SIZE(tmu1_resources),
232 };
233 
234 static struct sh_timer_config tmu2_platform_data = {
235  .channel_offset = 0x1c,
236  .timer_bit = 2,
237 };
238 
239 static struct resource tmu2_resources[] = {
240  [0] = {
241  .start = 0xFFD80020,
242  .end = 0xFFD80030 - 1,
243  .flags = IORESOURCE_MEM,
244  },
245  [1] = {
246  .start = evt2irq(0x440),
247  .flags = IORESOURCE_IRQ,
248  },
249 };
250 
251 static struct platform_device tmu2_device = {
252  .name = "sh_tmu",
253  .id = 2,
254  .dev = {
255  .platform_data = &tmu2_platform_data,
256  },
257  .resource = tmu2_resources,
258  .num_resources = ARRAY_SIZE(tmu2_resources),
259 };
260 
261 
262 static struct sh_timer_config tmu3_platform_data = {
263  .channel_offset = 0x04,
264  .timer_bit = 0,
265 };
266 
267 static struct resource tmu3_resources[] = {
268  [0] = {
269  .start = 0xFFD81008,
270  .end = 0xFFD81014 - 1,
271  .flags = IORESOURCE_MEM,
272  },
273  [1] = {
274  .start = evt2irq(0x480),
275  .flags = IORESOURCE_IRQ,
276  },
277 };
278 
279 static struct platform_device tmu3_device = {
280  .name = "sh_tmu",
281  .id = 3,
282  .dev = {
283  .platform_data = &tmu3_platform_data,
284  },
285  .resource = tmu3_resources,
286  .num_resources = ARRAY_SIZE(tmu3_resources),
287 };
288 
289 static struct sh_timer_config tmu4_platform_data = {
290  .channel_offset = 0x10,
291  .timer_bit = 1,
292 };
293 
294 static struct resource tmu4_resources[] = {
295  [0] = {
296  .start = 0xFFD81014,
297  .end = 0xFFD81020 - 1,
298  .flags = IORESOURCE_MEM,
299  },
300  [1] = {
301  .start = evt2irq(0x4A0),
302  .flags = IORESOURCE_IRQ,
303  },
304 };
305 
306 static struct platform_device tmu4_device = {
307  .name = "sh_tmu",
308  .id = 4,
309  .dev = {
310  .platform_data = &tmu4_platform_data,
311  },
312  .resource = tmu4_resources,
313  .num_resources = ARRAY_SIZE(tmu4_resources),
314 };
315 
316 static struct sh_timer_config tmu5_platform_data = {
317  .channel_offset = 0x1c,
318  .timer_bit = 2,
319 };
320 
321 static struct resource tmu5_resources[] = {
322  [0] = {
323  .start = 0xFFD81020,
324  .end = 0xFFD81030 - 1,
325  .flags = IORESOURCE_MEM,
326  },
327  [1] = {
328  .start = evt2irq(0x4C0),
329  .flags = IORESOURCE_IRQ,
330  },
331 };
332 
333 static struct platform_device tmu5_device = {
334  .name = "sh_tmu",
335  .id = 5,
336  .dev = {
337  .platform_data = &tmu5_platform_data,
338  },
339  .resource = tmu5_resources,
340  .num_resources = ARRAY_SIZE(tmu5_resources),
341 };
342 
343 static struct sh_timer_config tmu6_platform_data = {
344  .channel_offset = 0x4,
345  .timer_bit = 0,
346 };
347 
348 static struct resource tmu6_resources[] = {
349  [0] = {
350  .start = 0xFFD82008,
351  .end = 0xFFD82014 - 1,
352  .flags = IORESOURCE_MEM,
353  },
354  [1] = {
355  .start = evt2irq(0x500),
356  .flags = IORESOURCE_IRQ,
357  },
358 };
359 
360 static struct platform_device tmu6_device = {
361  .name = "sh_tmu",
362  .id = 6,
363  .dev = {
364  .platform_data = &tmu6_platform_data,
365  },
366  .resource = tmu6_resources,
367  .num_resources = ARRAY_SIZE(tmu6_resources),
368 };
369 
370 static struct sh_timer_config tmu7_platform_data = {
371  .channel_offset = 0x10,
372  .timer_bit = 1,
373 };
374 
375 static struct resource tmu7_resources[] = {
376  [0] = {
377  .start = 0xFFD82014,
378  .end = 0xFFD82020 - 1,
379  .flags = IORESOURCE_MEM,
380  },
381  [1] = {
382  .start = evt2irq(0x520),
383  .flags = IORESOURCE_IRQ,
384  },
385 };
386 
387 static struct platform_device tmu7_device = {
388  .name = "sh_tmu",
389  .id = 7,
390  .dev = {
391  .platform_data = &tmu7_platform_data,
392  },
393  .resource = tmu7_resources,
394  .num_resources = ARRAY_SIZE(tmu7_resources),
395 };
396 
397 static struct sh_timer_config tmu8_platform_data = {
398  .channel_offset = 0x1c,
399  .timer_bit = 2,
400 };
401 
402 static struct resource tmu8_resources[] = {
403  [0] = {
404  .start = 0xFFD82020,
405  .end = 0xFFD82030 - 1,
406  .flags = IORESOURCE_MEM,
407  },
408  [1] = {
409  .start = evt2irq(0x540),
410  .flags = IORESOURCE_IRQ,
411  },
412 };
413 
414 static struct platform_device tmu8_device = {
415  .name = "sh_tmu",
416  .id = 8,
417  .dev = {
418  .platform_data = &tmu8_platform_data,
419  },
420  .resource = tmu8_resources,
421  .num_resources = ARRAY_SIZE(tmu8_resources),
422 };
423 
424 static struct platform_device *sh7734_devices[] __initdata = {
425  &scif0_device,
426  &scif1_device,
427  &scif2_device,
428  &scif3_device,
429  &scif4_device,
430  &scif5_device,
431  &tmu0_device,
432  &tmu1_device,
433  &tmu2_device,
434  &tmu3_device,
435  &tmu4_device,
436  &tmu5_device,
437  &tmu6_device,
438  &tmu7_device,
439  &tmu8_device,
440  &rtc_device,
441 };
442 
443 static struct platform_device *sh7734_early_devices[] __initdata = {
444  &scif0_device,
445  &scif1_device,
446  &scif2_device,
447  &scif3_device,
448  &scif4_device,
449  &scif5_device,
450  &tmu0_device,
451  &tmu1_device,
452  &tmu2_device,
453  &tmu3_device,
454  &tmu4_device,
455  &tmu5_device,
456  &tmu6_device,
457  &tmu7_device,
458  &tmu8_device,
459 };
460 
461 void __init plat_early_device_setup(void)
462 {
463  early_platform_add_devices(sh7734_early_devices,
464  ARRAY_SIZE(sh7734_early_devices));
465 }
466 
467 #define GROUP 0
468 enum {
469  UNUSED = 0,
470 
471  /* interrupt sources */
472 
473  IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
474  IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
475  IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
476  IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
477 
478  IRQ0, IRQ1, IRQ2, IRQ3,
479  DU,
480  TMU00, TMU10, TMU20, TMU21,
481  TMU30, TMU40, TMU50, TMU51,
482  TMU60, TMU70, TMU80,
483  RESET_WDT,
484  USB,
485  HUDI,
486  SHDMAC,
487  SSI0, SSI1, SSI2, SSI3,
488  VIN0,
489  RGPVG,
490  _2DG,
491  MMC,
492  HSPI,
493  LBSCATA,
494  I2C0,
495  RCAN0,
496  MIMLB,
497  SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
498  LBSCDMAC0, LBSCDMAC1, LBSCDMAC2,
499  RCAN1,
500  SDHI0, SDHI1,
501  IEBUS,
502  HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28,
503  RTC,
504  VIN1,
505  LCDC,
506  SRC0, SRC1,
507  GETHER,
508  SDHI2,
509  GPIO0_3, GPIO4_5,
510  STIF0, STIF1,
511  ADMAC,
512  HIF,
513  FLCTL,
514  ADC,
515  MTU2,
516  RSPI,
517  QSPI,
518  HSCIF,
519  VEU3F_VE3,
520 
521  /* Group */
522  /* Mask */
523  STIF_M,
524  GPIO_M,
525  HPBDMAC_M,
526  LBSCDMAC_M,
527  RCAN_M,
528  SRC_M,
529  SCIF_M,
530  LCDC_M,
531  _2DG_M,
532  VIN_M,
533  TMU_3_M,
534  TMU_0_M,
535 
536  /* Priority */
537  RCAN_P,
538  LBSCDMAC_P,
539 
540  /* Common */
541  SDHI,
542  SSI,
543  SPI,
544 };
545 
546 static struct intc_vect vectors[] __initdata = {
547  INTC_VECT(DU, 0x3E0),
548  INTC_VECT(TMU00, 0x400),
549  INTC_VECT(TMU10, 0x420),
550  INTC_VECT(TMU20, 0x440),
551  INTC_VECT(TMU30, 0x480),
552  INTC_VECT(TMU40, 0x4A0),
553  INTC_VECT(TMU50, 0x4C0),
554  INTC_VECT(TMU51, 0x4E0),
555  INTC_VECT(TMU60, 0x500),
556  INTC_VECT(TMU70, 0x520),
557  INTC_VECT(TMU80, 0x540),
558  INTC_VECT(RESET_WDT, 0x560),
559  INTC_VECT(USB, 0x580),
560  INTC_VECT(HUDI, 0x600),
561  INTC_VECT(SHDMAC, 0x620),
562  INTC_VECT(SSI0, 0x6C0),
563  INTC_VECT(SSI1, 0x6E0),
564  INTC_VECT(SSI2, 0x700),
565  INTC_VECT(SSI3, 0x720),
566  INTC_VECT(VIN0, 0x740),
567  INTC_VECT(RGPVG, 0x760),
568  INTC_VECT(_2DG, 0x780),
569  INTC_VECT(MMC, 0x7A0),
570  INTC_VECT(HSPI, 0x7E0),
571  INTC_VECT(LBSCATA, 0x840),
572  INTC_VECT(I2C0, 0x860),
573  INTC_VECT(RCAN0, 0x880),
574  INTC_VECT(SCIF0, 0x8A0),
575  INTC_VECT(SCIF1, 0x8C0),
576  INTC_VECT(SCIF2, 0x900),
577  INTC_VECT(SCIF3, 0x920),
578  INTC_VECT(SCIF4, 0x940),
579  INTC_VECT(SCIF5, 0x960),
580  INTC_VECT(LBSCDMAC0, 0x9E0),
581  INTC_VECT(LBSCDMAC1, 0xA00),
582  INTC_VECT(LBSCDMAC2, 0xA20),
583  INTC_VECT(RCAN1, 0xA60),
584  INTC_VECT(SDHI0, 0xAE0),
585  INTC_VECT(SDHI1, 0xB00),
586  INTC_VECT(IEBUS, 0xB20),
587  INTC_VECT(HPBDMAC0_3, 0xB60),
588  INTC_VECT(HPBDMAC4_10, 0xB80),
589  INTC_VECT(HPBDMAC11_18, 0xBA0),
590  INTC_VECT(HPBDMAC19_22, 0xBC0),
591  INTC_VECT(HPBDMAC23_25_27_28, 0xBE0),
592  INTC_VECT(RTC, 0xC00),
593  INTC_VECT(VIN1, 0xC20),
594  INTC_VECT(LCDC, 0xC40),
595  INTC_VECT(SRC0, 0xC60),
596  INTC_VECT(SRC1, 0xC80),
597  INTC_VECT(GETHER, 0xCA0),
598  INTC_VECT(SDHI2, 0xCC0),
599  INTC_VECT(GPIO0_3, 0xCE0),
600  INTC_VECT(GPIO4_5, 0xD00),
601  INTC_VECT(STIF0, 0xD20),
602  INTC_VECT(STIF1, 0xD40),
603  INTC_VECT(ADMAC, 0xDA0),
604  INTC_VECT(HIF, 0xDC0),
605  INTC_VECT(FLCTL, 0xDE0),
606  INTC_VECT(ADC, 0xE00),
607  INTC_VECT(MTU2, 0xE20),
608  INTC_VECT(RSPI, 0xE40),
609  INTC_VECT(QSPI, 0xE60),
610  INTC_VECT(HSCIF, 0xFC0),
611  INTC_VECT(VEU3F_VE3, 0xF40),
612 };
613 
614 static struct intc_group groups[] __initdata = {
615  /* Common */
616  INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2),
617  INTC_GROUP(SPI, HSPI, RSPI, QSPI),
618  INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3),
619 
620  /* Mask group */
621  INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */
622  INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */
623  INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18,
624  HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */
625  INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */
626  INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */
627  INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */
628  INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
629  HSCIF), /* 14 */
630  INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
631  INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */
632  INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */
633  INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51,
634  TMU60, TMU60, TMU70, TMU80), /* 2 */
635  INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */
636 
637  /* Priority group*/
638  INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */
639  INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */
640 };
641 
642 static struct intc_mask_reg mask_registers[] __initdata = {
643  { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */
644  { 0,
645  VEU3F_VE3,
646  SDHI, /* SDHI 0-2 */
647  ADMAC,
648  FLCTL,
649  RESET_WDT,
650  HIF,
651  ADC,
652  MTU2,
653  STIF_M, /* STIF 0,1 */
654  GPIO_M, /* GPIO 0-5*/
655  GETHER,
656  HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */
657  LBSCDMAC_M, /* LBSCDMAC 0 - 2 */
658  RCAN_M, /* RCAN, IEBUS */
659  SRC_M, /* SRC 0,1 */
660  LBSCATA,
661  SCIF_M, /* SCIF 0-5, HSCIF */
662  LCDC_M, /* LCDC, MIMLB */
663  _2DG_M, /* 2DG, RGPVG */
664  SPI, /* HSPI, RSPI, QSPI */
665  VIN_M, /* VIN0, 1 */
666  SSI, /* SSI 0-3 */
667  USB,
668  SHDMAC,
669  HUDI,
670  MMC,
671  RTC,
672  I2C0, /* I2C */ /* I2C 0, 1*/
673  TMU_3_M, /* TMU30 - TMU80 */
674  TMU_0_M, /* TMU00 - TMU21 */
675  DU } },
676 };
677 
678 static struct intc_prio_reg prio_registers[] __initdata = {
679  { 0xFF804000, 0, 32, 8, /* INT2PRI0 */
680  { DU, TMU00, TMU10, TMU20 } },
681  { 0xFF804004, 0, 32, 8, /* INT2PRI1 */
682  { TMU30, TMU60, RTC, SDHI } },
683  { 0xFF804008, 0, 32, 8, /* INT2PRI2 */
684  { HUDI, SHDMAC, USB, SSI } },
685  { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */
686  { VIN0, SPI, _2DG, LBSCATA } },
687  { 0xFF804010, 0, 32, 8, /* INT2PRI4 */
688  { SCIF0, SCIF3, HSCIF, LCDC } },
689  { 0xFF804014, 0, 32, 8, /* INT2PRI5 */
690  { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } },
691  { 0xFF804018, 0, 32, 8, /* INT2PRI6 */
692  { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } },
693  { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */
694  { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } },
695  { 0xFF804020, 0, 32, 8, /* INT2PRI8 */
696  { 0 /* ADIF */, VIN1, RESET_WDT, HIF } },
697  { 0xFF804024, 0, 32, 8, /* INT2PRI9 */
698  { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } },
699  { 0xFF804028, 0, 32, 8, /* INT2PRI10 */
700  { STIF0, STIF1, VEU3F_VE3, GETHER } },
701  { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */
702  { MTU2, RGPVG, MIMLB, IEBUS } },
703 };
704 
705 static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups,
706  mask_registers, prio_registers, NULL);
707 
708 /* Support for external interrupt pins in IRQ mode */
709 
710 static struct intc_vect irq3210_vectors[] __initdata = {
711  INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
712  INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300),
713 };
714 
715 static struct intc_sense_reg irq3210_sense_registers[] __initdata = {
716  { 0xFF80201C, 32, 2, /* ICR1 */
717  { IRQ0, IRQ1, IRQ2, IRQ3, } },
718 };
719 
720 static struct intc_mask_reg irq3210_ack_registers[] __initdata = {
721  { 0xFF802024, 0, 32, /* INTREQ */
722  { IRQ0, IRQ1, IRQ2, IRQ3, } },
723 };
724 
725 static struct intc_mask_reg irq3210_mask_registers[] __initdata = {
726  { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */
727  { IRQ0, IRQ1, IRQ2, IRQ3, } },
728 };
729 
730 static struct intc_prio_reg irq3210_prio_registers[] __initdata = {
731  { 0xFF802010, 0, 32, 4, /* INTPRI */
732  { IRQ0, IRQ1, IRQ2, IRQ3, } },
733 };
734 
735 static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210",
736  irq3210_vectors, NULL,
737  irq3210_mask_registers, irq3210_prio_registers,
738  irq3210_sense_registers, irq3210_ack_registers);
739 
740 /* External interrupt pins in IRL mode */
741 
742 static struct intc_vect vectors_irl3210[] __initdata = {
743  INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
744  INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
745  INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
746  INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
747  INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
748  INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
749  INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
750  INTC_VECT(IRL0_HHHL, 0x3c0),
751 };
752 
753 static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210",
754  vectors_irl3210, NULL, mask_registers, NULL, NULL);
755 
756 #define INTC_ICR0 0xFF802000
757 #define INTC_INTMSK0 0xFF802044
758 #define INTC_INTMSK1 0xFF802048
759 #define INTC_INTMSKCLR0 0xFF802064
760 #define INTC_INTMSKCLR1 0xFF802068
761 
762 void __init plat_irq_setup(void)
763 {
764  /* disable IRQ3-0 */
765  __raw_writel(0xF0000000, INTC_INTMSK0);
766 
767  /* disable IRL3-0 */
768  __raw_writel(0x80000000, INTC_INTMSK1);
769 
770  /* select IRL mode for IRL3-0 */
771  __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
772 
773  /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */
774  __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
775 
776  register_intc_controller(&intc_desc);
777 }
778 
779 void __init plat_irq_setup_pins(int mode)
780 {
781  switch (mode) {
782  case IRQ_MODE_IRQ3210:
783  /* select IRQ mode for IRL3-0 */
784  __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
785  register_intc_controller(&intc_desc_irq3210);
786  break;
787  case IRQ_MODE_IRL3210:
788  /* enable IRL0-3 but don't provide any masking */
789  __raw_writel(0x80000000, INTC_INTMSKCLR1);
790  __raw_writel(0xf0000000, INTC_INTMSKCLR0);
791  break;
792  case IRQ_MODE_IRL3210_MASK:
793  /* enable IRL0-3 and mask using cpu intc controller */
794  __raw_writel(0x80000000, INTC_INTMSKCLR0);
795  register_intc_controller(&intc_desc_irl3210);
796  break;
797  default:
798  BUG();
799  }
800 }
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