Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
Data Structures | Macros | Typedefs | Functions
ncr53c8xx.h File Reference
#include <scsi/scsi_host.h>

Go to the source code of this file.

Data Structures

struct  ncr_chip
 
struct  ncr_driver_setup
 
struct  ncr_reg
 
struct  scr_tblmove
 
struct  scr_tblsel
 
struct  ncr_slot
 
struct  ncr_device
 

Macros

#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
 
#define SCSI_NCR_DEBUG_INFO_SUPPORT
 
#define SCSI_NCR_SETUP_SPECIAL_FEATURES   (3)
 
#define SCSI_NCR_MAX_SYNC   (80)
 
#define SCSI_NCR_MAX_TAGS   (8)
 
#define SCSI_NCR_SETUP_DEFAULT_TAGS   (0)
 
#define CONFIG_SCSI_NCR53C8XX_SYNC   (20)
 
#define SCSI_NCR_SETUP_DEFAULT_SYNC   (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
 
#define SCSI_NCR_SETUP_DISCONNECTION   (1)
 
#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO   (0)
 
#define SCSI_NCR_SETUP_MASTER_PARITY   (1)
 
#define SCSI_NCR_SETUP_SCSI_PARITY   (1)
 
#define SCSI_NCR_SETUP_SETTLE_TIME   (2)
 
#define SCSI_NCR_PCIQ_WORK_AROUND_OPT   1
 
#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
 
#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
 
#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
 
#define SCSI_NCR_ALWAYS_SIMPLE_TAG
 
#define SCSI_NCR_MAX_SCATTER   (127)
 
#define SCSI_NCR_MAX_TARGET   (16)
 
#define SCSI_NCR_CAN_QUEUE   (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
 
#define SCSI_NCR_CMD_PER_LUN   (SCSI_NCR_MAX_TAGS)
 
#define SCSI_NCR_SG_TABLESIZE   (SCSI_NCR_MAX_SCATTER)
 
#define SCSI_NCR_TIMER_INTERVAL   (HZ)
 
#define SCSI_NCR_MAX_LUN   (16)
 
#define inw_raw   inw
 
#define inl_raw   inl
 
#define outw_raw   outw
 
#define outl_raw   outl
 
#define readb_raw   readb
 
#define readw_raw   readw
 
#define readl_raw   readl
 
#define writeb_raw   writeb
 
#define writew_raw   writew
 
#define writel_raw   writel
 
#define MEMORY_BARRIER()   mb()
 
#define ncr_offb(o)   (o)
 
#define ncr_offw(o)   (o)
 
#define cpu_to_scr(dw)   (dw)
 
#define scr_to_cpu(dw)   (dw)
 
#define INB_OFF(o)   readb_raw((char __iomem *)np->reg + ncr_offb(o))
 
#define OUTB_OFF(o, val)   writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
 
#define INW_OFF(o)   readw_raw((char __iomem *)np->reg + ncr_offw(o))
 
#define INL_OFF(o)   readl_raw((char __iomem *)np->reg + (o))
 
#define OUTW_OFF(o, val)   writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
 
#define OUTL_OFF(o, val)   writel_raw((val), (char __iomem *)np->reg + (o))
 
#define INB(r)   INB_OFF (offsetof(struct ncr_reg,r))
 
#define INW(r)   INW_OFF (offsetof(struct ncr_reg,r))
 
#define INL(r)   INL_OFF (offsetof(struct ncr_reg,r))
 
#define OUTB(r, val)   OUTB_OFF (offsetof(struct ncr_reg,r), (val))
 
#define OUTW(r, val)   OUTW_OFF (offsetof(struct ncr_reg,r), (val))
 
#define OUTL(r, val)   OUTL_OFF (offsetof(struct ncr_reg,r), (val))
 
#define OUTONB(r, m)   OUTB(r, INB(r) | (m))
 
#define OUTOFFB(r, m)   OUTB(r, INB(r) & ~(m))
 
#define OUTONW(r, m)   OUTW(r, INW(r) | (m))
 
#define OUTOFFW(r, m)   OUTW(r, INW(r) & ~(m))
 
#define OUTONL(r, m)   OUTL(r, INL(r) | (m))
 
#define OUTOFFL(r, m)   OUTL(r, INL(r) & ~(m))
 
#define OUTL_DSP(v)
 
#define OUTONB_STD()
 
#define FE_LED0   (1<<0)
 
#define FE_WIDE   (1<<1) /* Wide data transfers */
 
#define FE_ULTRA   (1<<2) /* Ultra speed 20Mtrans/sec */
 
#define FE_DBLR   (1<<4) /* Clock doubler present */
 
#define FE_QUAD   (1<<5) /* Clock quadrupler present */
 
#define FE_ERL   (1<<6) /* Enable read line */
 
#define FE_CLSE   (1<<7) /* Cache line size enable */
 
#define FE_WRIE   (1<<8) /* Write & Invalidate enable */
 
#define FE_ERMP   (1<<9) /* Enable read multiple */
 
#define FE_BOF   (1<<10) /* Burst opcode fetch */
 
#define FE_DFS   (1<<11) /* DMA fifo size */
 
#define FE_PFEN   (1<<12) /* Prefetch enable */
 
#define FE_LDSTR   (1<<13) /* Load/Store supported */
 
#define FE_RAM   (1<<14) /* On chip RAM present */
 
#define FE_VARCLK   (1<<15) /* SCSI clock may vary */
 
#define FE_RAM8K   (1<<16) /* On chip RAM sized 8Kb */
 
#define FE_64BIT   (1<<17) /* Have a 64-bit PCI interface */
 
#define FE_IO256   (1<<18) /* Requires full 256 bytes in PCI space */
 
#define FE_NOPM   (1<<19) /* Scripts handles phase mismatch */
 
#define FE_LEDC   (1<<20) /* Hardware control of LED */
 
#define FE_DIFF   (1<<21) /* Support Differential SCSI */
 
#define FE_66MHZ   (1<<23) /* 66MHz PCI Support */
 
#define FE_DAC   (1<<24) /* Support DAC cycles (64 bit addressing) */
 
#define FE_ISTAT1   (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
 
#define FE_DAC_IN_USE   (1<<26) /* Platform does DAC cycles */
 
#define FE_EHP   (1<<27) /* 720: Even host parity */
 
#define FE_MUX   (1<<28) /* 720: Multiplexed bus */
 
#define FE_EA   (1<<29) /* 720: Enable Ack */
 
#define FE_CACHE_SET   (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
 
#define FE_SCSI_SET   (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
 
#define FE_SPECIAL_SET   (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
 
#define SCSI_NCR_MAX_EXCLUDES   8
 
#define SCSI_NCR_DRIVER_SETUP
 
#define SCSI_NCR_DRIVER_SAFE_SETUP
 
#define ISCON   0x10 /* connected to scsi */
 
#define CRST   0x08 /* force reset */
 
#define IARB   0x02 /* immediate arbitration */
 
#define SDU   0x80 /* cmd: disconnect will raise error */
 
#define CHM   0x40 /* sta: chained mode */
 
#define WSS   0x08 /* sta: wide scsi send [W]*/
 
#define WSR   0x01 /* sta: wide scsi received [W]*/
 
#define EWS   0x08 /* cmd: enable wide scsi [W]*/
 
#define ULTRA   0x80 /* cmd: ULTRA enable */
 
#define RRE   0x40 /* r/w:e enable response to resel. */
 
#define SRE   0x20 /* r/w:e enable response to select */
 
#define CREQ   0x80 /* r/w: SCSI-REQ */
 
#define CACK   0x40 /* r/w: SCSI-ACK */
 
#define CBSY   0x20 /* r/w: SCSI-BSY */
 
#define CSEL   0x10 /* r/w: SCSI-SEL */
 
#define CATN   0x08 /* r/w: SCSI-ATN */
 
#define CMSG   0x04 /* r/w: SCSI-MSG */
 
#define CC_D   0x02 /* r/w: SCSI-C_D */
 
#define CI_O   0x01 /* r/w: SCSI-I_O */
 
#define DFE   0x80 /* sta: dma fifo empty */
 
#define MDPE   0x40 /* int: master data parity error */
 
#define BF   0x20 /* int: script: bus fault */
 
#define ABRT   0x10 /* int: script: command aborted */
 
#define SSI   0x08 /* int: script: single step */
 
#define SIR   0x04 /* int: script: interrupt instruct. */
 
#define IID   0x01 /* int: script: illegal instruct. */
 
#define ILF   0x80 /* sta: data in SIDL register lsb */
 
#define ORF   0x40 /* sta: data in SODR register lsb */
 
#define OLF   0x20 /* sta: data in SODL register lsb */
 
#define AIP   0x10 /* sta: arbitration in progress */
 
#define LOA   0x08 /* sta: arbitration lost */
 
#define WOA   0x04 /* sta: arbitration won */
 
#define IRST   0x02 /* sta: scsi reset signal */
 
#define SDP   0x01 /* sta: scsi parity signal */
 
#define FF3210   0xf0 /* sta: bytes in the scsi fifo */
 
#define ILF1   0x80 /* sta: data in SIDL register msb[W]*/
 
#define ORF1   0x40 /* sta: data in SODR register msb[W]*/
 
#define OLF1   0x20 /* sta: data in SODL register msb[W]*/
 
#define DM   0x04 /* sta: DIFFSENS mismatch (895/6 only) */
 
#define LDSC   0x02 /* sta: disconnect & reconnect */
 
#define CABRT   0x80 /* cmd: abort current operation */
 
#define SRST   0x40 /* mod: reset chip */
 
#define SIGP   0x20 /* r/w: message from host to ncr */
 
#define SEM   0x10 /* r/w: message between host + ncr */
 
#define CON   0x08 /* sta: connected to scsi */
 
#define INTF   0x04 /* sta: int on the fly (reset by wr)*/
 
#define SIP   0x02 /* sta: scsi-interrupt */
 
#define DIP   0x01 /* sta: host/script interrupt */
 
#define FLSH   0x04 /* sta: chip is flushing */
 
#define SRUN   0x02 /* sta: scripts are running */
 
#define SIRQD   0x01 /* r/w: disable INT pin */
 
#define EHP   0x04 /* 720 even host parity */
 
#define CSIGP   0x40
 
#define FLF   0x08 /* cmd: flush dma fifo */
 
#define CLF   0x04 /* cmd: clear dma fifo */
 
#define FM   0x02 /* mod: fetch pin mode */
 
#define WRIE   0x01 /* mod: write and invalidate enable */
 
#define MUX   0x80 /* 720 host bus multiplex mode */
 
#define BDIS   0x80 /* mod: burst disable */
 
#define MPEE   0x08 /* mod: master parity error enable */
 
#define DFS   0x20 /* mod: dma fifo size */
 
#define BL_2   0x80 /* mod: burst length shift value +2 */
 
#define BL_1   0x40 /* mod: burst length shift value +1 */
 
#define ERL   0x08 /* mod: enable read line */
 
#define ERMP   0x04 /* mod: enable read multiple */
 
#define BOF   0x02 /* mod: burst op code fetch */
 
#define CLSE   0x80 /* mod: cache line size enable */
 
#define PFF   0x40 /* cmd: pre-fetch flush */
 
#define PFEN   0x20 /* mod: pre-fetch enable */
 
#define EA   0x20 /* mod: 720 enable-ack */
 
#define SSM   0x10 /* mod: single step mode */
 
#define IRQM   0x08 /* mod: irq mode (1 = totem pole !) */
 
#define STD   0x04 /* cmd: start dma mode */
 
#define IRQD   0x02 /* mod: irq disable */
 
#define NOCOM   0x01 /* cmd: protect sfbr while reselect */
 
#define SBMC   0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
 
#define STO   0x0400/* sta: timeout (select) */
 
#define GEN   0x0200/* sta: timeout (general) */
 
#define HTH   0x0100/* sta: timeout (handshake) */
 
#define MA   0x80 /* sta: phase mismatch */
 
#define CMP   0x40 /* sta: arbitration complete */
 
#define SEL   0x20 /* sta: selected by another device */
 
#define RSL   0x10 /* sta: reselected by another device*/
 
#define SGE   0x08 /* sta: gross error (over/underflow)*/
 
#define UDC   0x04 /* sta: unexpected disconnect */
 
#define RST   0x02 /* sta: scsi bus reset detected */
 
#define PAR   0x01 /* sta: scsi parity error */
 
#define SCLK   0x80 /* Use the PCI clock as SCSI clock */
 
#define DBLEN   0x08 /* clock doubler running */
 
#define DBLSEL   0x04 /* clock doubler selected */
 
#define ROF   0x40 /* reset scsi offset (after gross error!) */
 
#define DIF   0x20 /* 720 SCSI differential mode */
 
#define EXT   0x02 /* extended filtering */
 
#define TE   0x80 /* c: tolerAnt enable */
 
#define HSC   0x20 /* c: Halt SCSI Clock */
 
#define CSF   0x02 /* c: clear scsi fifo */
 
#define SMODE   0xc0 /* SCSI bus mode (895/6 only) */
 
#define SMODE_HVD   0x40 /* High Voltage Differential */
 
#define SMODE_SE   0x80 /* Single Ended */
 
#define SMODE_LVD   0xc0 /* Low Voltage Differential */
 
#define LCKFRQ   0x20 /* Frequency Lock (895/6 only) */
 
#define ENPMJ   0x80 /* Enable Phase Mismatch Jump */
 
#define PMJCTL   0x40 /* Phase Mismatch Jump Control */
 
#define ENNDJ   0x20 /* Enable Non Data PM Jump */
 
#define DISFC   0x10 /* Disable Auto FIFO Clear */
 
#define DILS   0x02 /* Disable Internal Load/Store */
 
#define DPR   0x01 /* Disable Pipe Req */
 
#define ZMOD   0x80 /* High Impedance Mode */
 
#define DIC   0x10 /* Disable Internal Cycles */
 
#define DDAC   0x08 /* Disable Dual Address Cycle */
 
#define XTIMOD   0x04 /* 64-bit Table Ind. Indexing Mode */
 
#define EXTIBMV   0x02 /* Enable 64-bit Table Ind. BMOV */
 
#define EXDBMV   0x01 /* Enable 64-bit Direct BMOV */
 
#define U3EN   0x80 /* Enable Ultra 3 */
 
#define AIPEN   0x40 /* Allow check upper byte lanes */
 
#define XCLKH_DT
 
#define XCLKH_ST
 
#define SNDCRC   0x10 /* Send CRC Request */
 
#define REGJ(p, r)   (offsetof(struct ncr_reg, p ## r))
 
#define REG(r)   REGJ (nc_, r)
 
#define SCR_DATA_OUT   0x00000000
 
#define SCR_DATA_IN   0x01000000
 
#define SCR_COMMAND   0x02000000
 
#define SCR_STATUS   0x03000000
 
#define SCR_DT_DATA_OUT   0x04000000
 
#define SCR_DT_DATA_IN   0x05000000
 
#define SCR_MSG_OUT   0x06000000
 
#define SCR_MSG_IN   0x07000000
 
#define SCR_ILG_OUT   0x04000000
 
#define SCR_ILG_IN   0x05000000
 
#define OPC_MOVE   0x08000000
 
#define SCR_MOVE_ABS(l)   ((0x00000000 | OPC_MOVE) | (l))
 
#define SCR_MOVE_IND(l)   ((0x20000000 | OPC_MOVE) | (l))
 
#define SCR_MOVE_TBL   (0x10000000 | OPC_MOVE)
 
#define SCR_CHMOV_ABS(l)   ((0x00000000) | (l))
 
#define SCR_CHMOV_IND(l)   ((0x20000000) | (l))
 
#define SCR_CHMOV_TBL   (0x10000000)
 
#define SCR_SEL_ABS   0x40000000
 
#define SCR_SEL_ABS_ATN   0x41000000
 
#define SCR_SEL_TBL   0x42000000
 
#define SCR_SEL_TBL_ATN   0x43000000
 
#define SCR_JMP_REL   0x04000000
 
#define SCR_ID(id)   (((u32)(id)) << 16)
 
#define SCR_WAIT_DISC   0x48000000
 
#define SCR_WAIT_RESEL   0x50000000
 
#define SCR_SET(f)   (0x58000000 | (f))
 
#define SCR_CLR(f)   (0x60000000 | (f))
 
#define SCR_CARRY   0x00000400
 
#define SCR_TRG   0x00000200
 
#define SCR_ACK   0x00000040
 
#define SCR_ATN   0x00000008
 
#define SCR_NO_FLUSH   0x01000000
 
#define SCR_COPY(n)   (0xc0000000 | SCR_NO_FLUSH | (n))
 
#define SCR_COPY_F(n)   (0xc0000000 | (n))
 
#define SCR_REG_OFS(ofs)   ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
 
#define SCR_SFBR_REG(reg, op, data)   (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
 
#define SCR_REG_SFBR(reg, op, data)   (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
 
#define SCR_REG_REG(reg, op, data)   (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
 
#define SCR_LOAD   0x00000000
 
#define SCR_SHL   0x01000000
 
#define SCR_OR   0x02000000
 
#define SCR_XOR   0x03000000
 
#define SCR_AND   0x04000000
 
#define SCR_SHR   0x05000000
 
#define SCR_ADD   0x06000000
 
#define SCR_ADDC   0x07000000
 
#define SCR_SFBR_DATA   (0x00800000>>8ul) /* Use SFBR as data */
 
#define SCR_FROM_REG(reg)   SCR_REG_SFBR(reg,SCR_OR,0)
 
#define SCR_TO_REG(reg)   SCR_SFBR_REG(reg,SCR_OR,0)
 
#define SCR_LOAD_REG(reg, data)   SCR_REG_REG(reg,SCR_LOAD,data)
 
#define SCR_LOAD_SFBR(data)   (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
 
#define SCR_REG_OFS2(ofs)   (((ofs) & 0xff) << 16ul)
 
#define SCR_NO_FLUSH2   0x02000000
 
#define SCR_DSA_REL2   0x10000000
 
#define SCR_LOAD_R(reg, how, n)   (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
 
#define SCR_STORE_R(reg, how, n)   (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
 
#define SCR_LOAD_ABS(reg, n)   SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
 
#define SCR_LOAD_REL(reg, n)   SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
 
#define SCR_LOAD_ABS_F(reg, n)   SCR_LOAD_R(reg, 0, n)
 
#define SCR_LOAD_REL_F(reg, n)   SCR_LOAD_R(reg, SCR_DSA_REL2, n)
 
#define SCR_STORE_ABS(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
 
#define SCR_STORE_REL(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
 
#define SCR_STORE_ABS_F(reg, n)   SCR_STORE_R(reg, 0, n)
 
#define SCR_STORE_REL_F(reg, n)   SCR_STORE_R(reg, SCR_DSA_REL2, n)
 
#define SCR_NO_OP   0x80000000
 
#define SCR_JUMP   0x80080000
 
#define SCR_JUMP64   0x80480000
 
#define SCR_JUMPR   0x80880000
 
#define SCR_CALL   0x88080000
 
#define SCR_CALLR   0x88880000
 
#define SCR_RETURN   0x90080000
 
#define SCR_INT   0x98080000
 
#define SCR_INT_FLY   0x98180000
 
#define IFFALSE(arg)   (0x00080000 | (arg))
 
#define IFTRUE(arg)   (0x00000000 | (arg))
 
#define WHEN(phase)   (0x00030000 | (phase))
 
#define IF(phase)   (0x00020000 | (phase))
 
#define DATA(D)   (0x00040000 | ((D) & 0xff))
 
#define MASK(D, M)   (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
 
#define CARRYSET   (0x00200000)
 
#define S_GOOD   (0x00)
 
#define S_CHECK_COND   (0x02)
 
#define S_COND_MET   (0x04)
 
#define S_BUSY   (0x08)
 
#define S_INT   (0x10)
 
#define S_INT_COND_MET   (0x14)
 
#define S_CONFLICT   (0x18)
 
#define S_TERMINATED   (0x20)
 
#define S_QUEUE_FULL   (0x28)
 
#define S_ILLEGAL   (0xff)
 
#define S_SENSE   (0x80)
 
#define ncr_build_sge(np, data, badd, len)
 

Typedefs

typedef u32 ncrcmd
 

Functions

struct Scsi_Hostncr_attach (struct scsi_host_template *tpnt, int unit, struct ncr_device *device)
 
void ncr53c8xx_release (struct Scsi_Host *host)
 
irqreturn_t ncr53c8xx_intr (int irq, void *dev_id)
 
int ncr53c8xx_init (void)
 
void ncr53c8xx_exit (void)
 

Macro Definition Documentation

#define ABRT   0x10 /* int: script: command aborted */

Definition at line 671 of file ncr53c8xx.h.

#define AIP   0x10 /* sta: arbitration in progress */

Definition at line 680 of file ncr53c8xx.h.

#define AIPEN   0x40 /* Allow check upper byte lanes */

Definition at line 867 of file ncr53c8xx.h.

#define BDIS   0x80 /* mod: burst disable */

Definition at line 739 of file ncr53c8xx.h.

#define BF   0x20 /* int: script: bus fault */

Definition at line 670 of file ncr53c8xx.h.

#define BL_1   0x40 /* mod: burst length shift value +1 */

Definition at line 759 of file ncr53c8xx.h.

#define BL_2   0x80 /* mod: burst length shift value +2 */

Definition at line 758 of file ncr53c8xx.h.

#define BOF   0x02 /* mod: burst op code fetch */

Definition at line 762 of file ncr53c8xx.h.

#define CABRT   0x80 /* cmd: abort current operation */

Definition at line 702 of file ncr53c8xx.h.

#define CACK   0x40 /* r/w: SCSI-ACK */

Definition at line 655 of file ncr53c8xx.h.

#define CARRYSET   (0x00200000)

Definition at line 1246 of file ncr53c8xx.h.

#define CATN   0x08 /* r/w: SCSI-ATN */

Definition at line 658 of file ncr53c8xx.h.

#define CBSY   0x20 /* r/w: SCSI-BSY */

Definition at line 656 of file ncr53c8xx.h.

#define CC_D   0x02 /* r/w: SCSI-C_D */

Definition at line 660 of file ncr53c8xx.h.

#define CHM   0x40 /* sta: chained mode */

Definition at line 631 of file ncr53c8xx.h.

#define CI_O   0x01 /* r/w: SCSI-I_O */

Definition at line 661 of file ncr53c8xx.h.

#define CLF   0x04 /* cmd: clear dma fifo */

Definition at line 729 of file ncr53c8xx.h.

#define CLSE   0x80 /* mod: cache line size enable */

Definition at line 768 of file ncr53c8xx.h.

#define CMP   0x40 /* sta: arbitration complete */

Definition at line 788 of file ncr53c8xx.h.

#define CMSG   0x04 /* r/w: SCSI-MSG */

Definition at line 659 of file ncr53c8xx.h.

#define CON   0x08 /* sta: connected to scsi */

Definition at line 706 of file ncr53c8xx.h.

#define CONFIG_SCSI_NCR53C8XX_SYNC   (20)

Definition at line 134 of file ncr53c8xx.h.

#define cpu_to_scr (   dw)    (dw)

Definition at line 373 of file ncr53c8xx.h.

#define CREQ   0x80 /* r/w: SCSI-REQ */

Definition at line 654 of file ncr53c8xx.h.

#define CRST   0x08 /* force reset */

Definition at line 626 of file ncr53c8xx.h.

#define CSEL   0x10 /* r/w: SCSI-SEL */

Definition at line 657 of file ncr53c8xx.h.

#define CSF   0x02 /* c: clear scsi fifo */

Definition at line 820 of file ncr53c8xx.h.

#define CSIGP   0x40

Definition at line 724 of file ncr53c8xx.h.

#define DATA (   D)    (0x00040000 | ((D) & 0xff))

Definition at line 1243 of file ncr53c8xx.h.

#define DBLEN   0x08 /* clock doubler running */

Definition at line 808 of file ncr53c8xx.h.

#define DBLSEL   0x04 /* clock doubler selected */

Definition at line 809 of file ncr53c8xx.h.

#define DDAC   0x08 /* Disable Dual Address Cycle */

Definition at line 844 of file ncr53c8xx.h.

#define DFE   0x80 /* sta: dma fifo empty */

Definition at line 668 of file ncr53c8xx.h.

#define DFS   0x20 /* mod: dma fifo size */

Definition at line 743 of file ncr53c8xx.h.

#define DIC   0x10 /* Disable Internal Cycles */

Definition at line 843 of file ncr53c8xx.h.

#define DIF   0x20 /* 720 SCSI differential mode */

Definition at line 814 of file ncr53c8xx.h.

#define DILS   0x02 /* Disable Internal Load/Store */

Definition at line 838 of file ncr53c8xx.h.

#define DIP   0x01 /* sta: host/script interrupt */

Definition at line 709 of file ncr53c8xx.h.

#define DISFC   0x10 /* Disable Auto FIFO Clear */

Definition at line 837 of file ncr53c8xx.h.

#define DM   0x04 /* sta: DIFFSENS mismatch (895/6 only) */

Definition at line 693 of file ncr53c8xx.h.

#define DPR   0x01 /* Disable Pipe Req */

Definition at line 839 of file ncr53c8xx.h.

#define EA   0x20 /* mod: 720 enable-ack */

Definition at line 771 of file ncr53c8xx.h.

#define EHP   0x04 /* 720 even host parity */

Definition at line 720 of file ncr53c8xx.h.

#define ENNDJ   0x20 /* Enable Non Data PM Jump */

Definition at line 836 of file ncr53c8xx.h.

#define ENPMJ   0x80 /* Enable Phase Mismatch Jump */

Definition at line 834 of file ncr53c8xx.h.

#define ERL   0x08 /* mod: enable read line */

Definition at line 760 of file ncr53c8xx.h.

#define ERMP   0x04 /* mod: enable read multiple */

Definition at line 761 of file ncr53c8xx.h.

#define EWS   0x08 /* cmd: enable wide scsi [W]*/

Definition at line 636 of file ncr53c8xx.h.

#define EXDBMV   0x01 /* Enable 64-bit Direct BMOV */

Definition at line 847 of file ncr53c8xx.h.

#define EXT   0x02 /* extended filtering */

Definition at line 815 of file ncr53c8xx.h.

#define EXTIBMV   0x02 /* Enable 64-bit Table Ind. BMOV */

Definition at line 846 of file ncr53c8xx.h.

#define FE_64BIT   (1<<17) /* Have a 64-bit PCI interface */

Definition at line 496 of file ncr53c8xx.h.

#define FE_66MHZ   (1<<23) /* 66MHz PCI Support */

Definition at line 501 of file ncr53c8xx.h.

#define FE_BOF   (1<<10) /* Burst opcode fetch */

Definition at line 489 of file ncr53c8xx.h.

#define FE_CACHE_SET   (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)

Definition at line 509 of file ncr53c8xx.h.

#define FE_CLSE   (1<<7) /* Cache line size enable */

Definition at line 486 of file ncr53c8xx.h.

#define FE_DAC   (1<<24) /* Support DAC cycles (64 bit addressing) */

Definition at line 502 of file ncr53c8xx.h.

#define FE_DAC_IN_USE   (1<<26) /* Platform does DAC cycles */

Definition at line 504 of file ncr53c8xx.h.

#define FE_DBLR   (1<<4) /* Clock doubler present */

Definition at line 483 of file ncr53c8xx.h.

#define FE_DFS   (1<<11) /* DMA fifo size */

Definition at line 490 of file ncr53c8xx.h.

#define FE_DIFF   (1<<21) /* Support Differential SCSI */

Definition at line 500 of file ncr53c8xx.h.

#define FE_EA   (1<<29) /* 720: Enable Ack */

Definition at line 507 of file ncr53c8xx.h.

#define FE_EHP   (1<<27) /* 720: Even host parity */

Definition at line 505 of file ncr53c8xx.h.

#define FE_ERL   (1<<6) /* Enable read line */

Definition at line 485 of file ncr53c8xx.h.

#define FE_ERMP   (1<<9) /* Enable read multiple */

Definition at line 488 of file ncr53c8xx.h.

#define FE_IO256   (1<<18) /* Requires full 256 bytes in PCI space */

Definition at line 497 of file ncr53c8xx.h.

#define FE_ISTAT1   (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */

Definition at line 503 of file ncr53c8xx.h.

#define FE_LDSTR   (1<<13) /* Load/Store supported */

Definition at line 492 of file ncr53c8xx.h.

#define FE_LED0   (1<<0)

Definition at line 480 of file ncr53c8xx.h.

#define FE_LEDC   (1<<20) /* Hardware control of LED */

Definition at line 499 of file ncr53c8xx.h.

#define FE_MUX   (1<<28) /* 720: Multiplexed bus */

Definition at line 506 of file ncr53c8xx.h.

#define FE_NOPM   (1<<19) /* Scripts handles phase mismatch */

Definition at line 498 of file ncr53c8xx.h.

#define FE_PFEN   (1<<12) /* Prefetch enable */

Definition at line 491 of file ncr53c8xx.h.

#define FE_QUAD   (1<<5) /* Clock quadrupler present */

Definition at line 484 of file ncr53c8xx.h.

#define FE_RAM   (1<<14) /* On chip RAM present */

Definition at line 493 of file ncr53c8xx.h.

#define FE_RAM8K   (1<<16) /* On chip RAM sized 8Kb */

Definition at line 495 of file ncr53c8xx.h.

#define FE_SCSI_SET   (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)

Definition at line 510 of file ncr53c8xx.h.

#define FE_SPECIAL_SET   (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)

Definition at line 511 of file ncr53c8xx.h.

#define FE_ULTRA   (1<<2) /* Ultra speed 20Mtrans/sec */

Definition at line 482 of file ncr53c8xx.h.

#define FE_VARCLK   (1<<15) /* SCSI clock may vary */

Definition at line 494 of file ncr53c8xx.h.

#define FE_WIDE   (1<<1) /* Wide data transfers */

Definition at line 481 of file ncr53c8xx.h.

#define FE_WRIE   (1<<8) /* Write & Invalidate enable */

Definition at line 487 of file ncr53c8xx.h.

#define FF3210   0xf0 /* sta: bytes in the scsi fifo */

Definition at line 687 of file ncr53c8xx.h.

#define FLF   0x08 /* cmd: flush dma fifo */

Definition at line 728 of file ncr53c8xx.h.

#define FLSH   0x04 /* sta: chip is flushing */

Definition at line 712 of file ncr53c8xx.h.

#define FM   0x02 /* mod: fetch pin mode */

Definition at line 730 of file ncr53c8xx.h.

#define GEN   0x0200/* sta: timeout (general) */

Definition at line 785 of file ncr53c8xx.h.

#define HSC   0x20 /* c: Halt SCSI Clock */

Definition at line 819 of file ncr53c8xx.h.

#define HTH   0x0100/* sta: timeout (handshake) */

Definition at line 786 of file ncr53c8xx.h.

#define IARB   0x02 /* immediate arbitration */

Definition at line 627 of file ncr53c8xx.h.

#define IF (   phase)    (0x00020000 | (phase))

Definition at line 1241 of file ncr53c8xx.h.

#define IFFALSE (   arg)    (0x00080000 | (arg))

Definition at line 1237 of file ncr53c8xx.h.

#define IFTRUE (   arg)    (0x00000000 | (arg))

Definition at line 1238 of file ncr53c8xx.h.

#define IID   0x01 /* int: script: illegal instruct. */

Definition at line 674 of file ncr53c8xx.h.

#define ILF   0x80 /* sta: data in SIDL register lsb */

Definition at line 677 of file ncr53c8xx.h.

#define ILF1   0x80 /* sta: data in SIDL register msb[W]*/

Definition at line 690 of file ncr53c8xx.h.

#define INB (   r)    INB_OFF (offsetof(struct ncr_reg,r))

Definition at line 434 of file ncr53c8xx.h.

#define INB_OFF (   o)    readb_raw((char __iomem *)np->reg + ncr_offb(o))

Definition at line 395 of file ncr53c8xx.h.

#define INL (   r)    INL_OFF (offsetof(struct ncr_reg,r))

Definition at line 436 of file ncr53c8xx.h.

#define INL_OFF (   o)    readl_raw((char __iomem *)np->reg + (o))

Definition at line 422 of file ncr53c8xx.h.

#define inl_raw   inl

Definition at line 311 of file ncr53c8xx.h.

#define INTF   0x04 /* sta: int on the fly (reset by wr)*/

Definition at line 707 of file ncr53c8xx.h.

#define INW (   r)    INW_OFF (offsetof(struct ncr_reg,r))

Definition at line 435 of file ncr53c8xx.h.

#define INW_OFF (   o)    readw_raw((char __iomem *)np->reg + ncr_offw(o))

Definition at line 420 of file ncr53c8xx.h.

#define inw_raw   inw

Definition at line 310 of file ncr53c8xx.h.

#define IRQD   0x02 /* mod: irq disable */

Definition at line 775 of file ncr53c8xx.h.

#define IRQM   0x08 /* mod: irq mode (1 = totem pole !) */

Definition at line 773 of file ncr53c8xx.h.

#define IRST   0x02 /* sta: scsi reset signal */

Definition at line 683 of file ncr53c8xx.h.

#define ISCON   0x10 /* connected to scsi */

Definition at line 625 of file ncr53c8xx.h.

#define LCKFRQ   0x20 /* Frequency Lock (895/6 only) */

Definition at line 828 of file ncr53c8xx.h.

#define LDSC   0x02 /* sta: disconnect & reconnect */

Definition at line 694 of file ncr53c8xx.h.

#define LOA   0x08 /* sta: arbitration lost */

Definition at line 681 of file ncr53c8xx.h.

#define MA   0x80 /* sta: phase mismatch */

Definition at line 787 of file ncr53c8xx.h.

#define MASK (   D,
  M 
)    (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))

Definition at line 1244 of file ncr53c8xx.h.

#define MDPE   0x40 /* int: master data parity error */

Definition at line 669 of file ncr53c8xx.h.

#define MEMORY_BARRIER ( )    mb()

Definition at line 330 of file ncr53c8xx.h.

#define MPEE   0x08 /* mod: master parity error enable */

Definition at line 740 of file ncr53c8xx.h.

#define MUX   0x80 /* 720 host bus multiplex mode */

Definition at line 738 of file ncr53c8xx.h.

#define ncr_build_sge (   np,
  data,
  badd,
  len 
)
Value:
do { \
(data)->addr = cpu_to_scr(badd); \
(data)->size = cpu_to_scr(len); \
} while (0)

Definition at line 1281 of file ncr53c8xx.h.

#define ncr_offb (   o)    (o)

Definition at line 348 of file ncr53c8xx.h.

#define ncr_offw (   o)    (o)

Definition at line 349 of file ncr53c8xx.h.

#define NOCOM   0x01 /* cmd: protect sfbr while reselect */

Definition at line 776 of file ncr53c8xx.h.

#define OLF   0x20 /* sta: data in SODL register lsb */

Definition at line 679 of file ncr53c8xx.h.

#define OLF1   0x20 /* sta: data in SODL register msb[W]*/

Definition at line 692 of file ncr53c8xx.h.

#define OPC_MOVE   0x08000000

Definition at line 956 of file ncr53c8xx.h.

#define ORF   0x40 /* sta: data in SODR register lsb */

Definition at line 678 of file ncr53c8xx.h.

#define ORF1   0x40 /* sta: data in SODR register msb[W]*/

Definition at line 691 of file ncr53c8xx.h.

#define OUTB (   r,
  val 
)    OUTB_OFF (offsetof(struct ncr_reg,r), (val))

Definition at line 438 of file ncr53c8xx.h.

#define OUTB_OFF (   o,
  val 
)    writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))

Definition at line 396 of file ncr53c8xx.h.

#define OUTL (   r,
  val 
)    OUTL_OFF (offsetof(struct ncr_reg,r), (val))

Definition at line 440 of file ncr53c8xx.h.

#define OUTL_DSP (   v)
Value:
do { \
MEMORY_BARRIER(); \
OUTL (nc_dsp, (v)); \
} while (0)

Definition at line 458 of file ncr53c8xx.h.

#define OUTL_OFF (   o,
  val 
)    writel_raw((val), (char __iomem *)np->reg + (o))

Definition at line 430 of file ncr53c8xx.h.

#define outl_raw   outl

Definition at line 313 of file ncr53c8xx.h.

#define OUTOFFB (   r,
  m 
)    OUTB(r, INB(r) & ~(m))

Definition at line 447 of file ncr53c8xx.h.

#define OUTOFFL (   r,
  m 
)    OUTL(r, INL(r) & ~(m))

Definition at line 451 of file ncr53c8xx.h.

#define OUTOFFW (   r,
  m 
)    OUTW(r, INW(r) & ~(m))

Definition at line 449 of file ncr53c8xx.h.

#define OUTONB (   r,
  m 
)    OUTB(r, INB(r) | (m))

Definition at line 446 of file ncr53c8xx.h.

#define OUTONB_STD ( )
Value:
do { \
MEMORY_BARRIER(); \
OUTONB (nc_dcntl, (STD|NOCOM)); \
} while (0)

Definition at line 464 of file ncr53c8xx.h.

#define OUTONL (   r,
  m 
)    OUTL(r, INL(r) | (m))

Definition at line 450 of file ncr53c8xx.h.

#define OUTONW (   r,
  m 
)    OUTW(r, INW(r) | (m))

Definition at line 448 of file ncr53c8xx.h.

#define OUTW (   r,
  val 
)    OUTW_OFF (offsetof(struct ncr_reg,r), (val))

Definition at line 439 of file ncr53c8xx.h.

#define OUTW_OFF (   o,
  val 
)    writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))

Definition at line 428 of file ncr53c8xx.h.

#define outw_raw   outw

Definition at line 312 of file ncr53c8xx.h.

#define PAR   0x01 /* sta: scsi parity error */

Definition at line 794 of file ncr53c8xx.h.

#define PFEN   0x20 /* mod: pre-fetch enable */

Definition at line 770 of file ncr53c8xx.h.

#define PFF   0x40 /* cmd: pre-fetch flush */

Definition at line 769 of file ncr53c8xx.h.

#define PMJCTL   0x40 /* Phase Mismatch Jump Control */

Definition at line 835 of file ncr53c8xx.h.

#define readb_raw   readb

Definition at line 315 of file ncr53c8xx.h.

#define readl_raw   readl

Definition at line 317 of file ncr53c8xx.h.

#define readw_raw   readw

Definition at line 316 of file ncr53c8xx.h.

#define REG (   r)    REGJ (nc_, r)

Definition at line 913 of file ncr53c8xx.h.

#define REGJ (   p,
  r 
)    (offsetof(struct ncr_reg, p ## r))

Definition at line 912 of file ncr53c8xx.h.

#define ROF   0x40 /* reset scsi offset (after gross error!) */

Definition at line 813 of file ncr53c8xx.h.

#define RRE   0x40 /* r/w:e enable response to resel. */

Definition at line 641 of file ncr53c8xx.h.

#define RSL   0x10 /* sta: reselected by another device*/

Definition at line 790 of file ncr53c8xx.h.

#define RST   0x02 /* sta: scsi bus reset detected */

Definition at line 793 of file ncr53c8xx.h.

#define S_BUSY   (0x08)

Definition at line 1262 of file ncr53c8xx.h.

#define S_CHECK_COND   (0x02)

Definition at line 1260 of file ncr53c8xx.h.

#define S_COND_MET   (0x04)

Definition at line 1261 of file ncr53c8xx.h.

#define S_CONFLICT   (0x18)

Definition at line 1265 of file ncr53c8xx.h.

#define S_GOOD   (0x00)

Definition at line 1259 of file ncr53c8xx.h.

#define S_ILLEGAL   (0xff)

Definition at line 1268 of file ncr53c8xx.h.

#define S_INT   (0x10)

Definition at line 1263 of file ncr53c8xx.h.

#define S_INT_COND_MET   (0x14)

Definition at line 1264 of file ncr53c8xx.h.

#define S_QUEUE_FULL   (0x28)

Definition at line 1267 of file ncr53c8xx.h.

#define S_SENSE   (0x80)

Definition at line 1269 of file ncr53c8xx.h.

#define S_TERMINATED   (0x20)

Definition at line 1266 of file ncr53c8xx.h.

#define SBMC   0x1000/* sta: SCSI Bus Mode Change (895/6 only) */

Definition at line 783 of file ncr53c8xx.h.

#define SCLK   0x80 /* Use the PCI clock as SCSI clock */

Definition at line 807 of file ncr53c8xx.h.

#define SCR_ACK   0x00000040

Definition at line 1047 of file ncr53c8xx.h.

#define SCR_ADD   0x06000000

Definition at line 1118 of file ncr53c8xx.h.

#define SCR_ADDC   0x07000000

Definition at line 1119 of file ncr53c8xx.h.

#define SCR_AND   0x04000000

Definition at line 1116 of file ncr53c8xx.h.

#define SCR_ATN   0x00000008

Definition at line 1048 of file ncr53c8xx.h.

#define SCR_CALL   0x88080000

Definition at line 1231 of file ncr53c8xx.h.

#define SCR_CALLR   0x88880000

Definition at line 1232 of file ncr53c8xx.h.

#define SCR_CARRY   0x00000400

Definition at line 1045 of file ncr53c8xx.h.

#define SCR_CHMOV_ABS (   l)    ((0x00000000) | (l))

Definition at line 962 of file ncr53c8xx.h.

#define SCR_CHMOV_IND (   l)    ((0x20000000) | (l))

Definition at line 963 of file ncr53c8xx.h.

#define SCR_CHMOV_TBL   (0x10000000)

Definition at line 964 of file ncr53c8xx.h.

#define SCR_CLR (   f)    (0x60000000 | (f))

Definition at line 1043 of file ncr53c8xx.h.

#define SCR_COMMAND   0x02000000

Definition at line 928 of file ncr53c8xx.h.

#define SCR_COPY (   n)    (0xc0000000 | SCR_NO_FLUSH | (n))

Definition at line 1073 of file ncr53c8xx.h.

#define SCR_COPY_F (   n)    (0xc0000000 | (n))

Definition at line 1074 of file ncr53c8xx.h.

#define SCR_DATA_IN   0x01000000

Definition at line 927 of file ncr53c8xx.h.

#define SCR_DATA_OUT   0x00000000

Definition at line 926 of file ncr53c8xx.h.

#define SCR_DSA_REL2   0x10000000

Definition at line 1172 of file ncr53c8xx.h.

#define SCR_DT_DATA_IN   0x05000000

Definition at line 931 of file ncr53c8xx.h.

#define SCR_DT_DATA_OUT   0x04000000

Definition at line 930 of file ncr53c8xx.h.

#define SCR_FROM_REG (   reg)    SCR_REG_SFBR(reg,SCR_OR,0)

Definition at line 1140 of file ncr53c8xx.h.

#define SCR_ID (   id)    (((u32)(id)) << 16)

Definition at line 1009 of file ncr53c8xx.h.

#define SCR_ILG_IN   0x05000000

Definition at line 936 of file ncr53c8xx.h.

#define SCR_ILG_OUT   0x04000000

Definition at line 935 of file ncr53c8xx.h.

#define SCR_INT   0x98080000

Definition at line 1234 of file ncr53c8xx.h.

#define SCR_INT_FLY   0x98180000

Definition at line 1235 of file ncr53c8xx.h.

#define SCR_JMP_REL   0x04000000

Definition at line 1008 of file ncr53c8xx.h.

#define SCR_JUMP   0x80080000

Definition at line 1228 of file ncr53c8xx.h.

#define SCR_JUMP64   0x80480000

Definition at line 1229 of file ncr53c8xx.h.

#define SCR_JUMPR   0x80880000

Definition at line 1230 of file ncr53c8xx.h.

#define SCR_LOAD   0x00000000

Definition at line 1112 of file ncr53c8xx.h.

#define SCR_LOAD_ABS (   reg,
  n 
)    SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)

Definition at line 1180 of file ncr53c8xx.h.

#define SCR_LOAD_ABS_F (   reg,
  n 
)    SCR_LOAD_R(reg, 0, n)

Definition at line 1182 of file ncr53c8xx.h.

#define SCR_LOAD_R (   reg,
  how,
  n 
)    (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))

Definition at line 1174 of file ncr53c8xx.h.

#define SCR_LOAD_REG (   reg,
  data 
)    SCR_REG_REG(reg,SCR_LOAD,data)

Definition at line 1146 of file ncr53c8xx.h.

#define SCR_LOAD_REL (   reg,
  n 
)    SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)

Definition at line 1181 of file ncr53c8xx.h.

#define SCR_LOAD_REL_F (   reg,
  n 
)    SCR_LOAD_R(reg, SCR_DSA_REL2, n)

Definition at line 1183 of file ncr53c8xx.h.

#define SCR_LOAD_SFBR (   data)    (SCR_REG_SFBR (gpreg, SCR_LOAD, data))

Definition at line 1149 of file ncr53c8xx.h.

#define SCR_MOVE_ABS (   l)    ((0x00000000 | OPC_MOVE) | (l))

Definition at line 958 of file ncr53c8xx.h.

#define SCR_MOVE_IND (   l)    ((0x20000000 | OPC_MOVE) | (l))

Definition at line 959 of file ncr53c8xx.h.

#define SCR_MOVE_TBL   (0x10000000 | OPC_MOVE)

Definition at line 960 of file ncr53c8xx.h.

#define SCR_MSG_IN   0x07000000

Definition at line 933 of file ncr53c8xx.h.

#define SCR_MSG_OUT   0x06000000

Definition at line 932 of file ncr53c8xx.h.

#define SCR_NO_FLUSH   0x01000000

Definition at line 1071 of file ncr53c8xx.h.

#define SCR_NO_FLUSH2   0x02000000

Definition at line 1171 of file ncr53c8xx.h.

#define SCR_NO_OP   0x80000000

Definition at line 1227 of file ncr53c8xx.h.

#define SCR_OR   0x02000000

Definition at line 1114 of file ncr53c8xx.h.

#define SCR_REG_OFS (   ofs)    ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))

Definition at line 1100 of file ncr53c8xx.h.

#define SCR_REG_OFS2 (   ofs)    (((ofs) & 0xff) << 16ul)

Definition at line 1170 of file ncr53c8xx.h.

#define SCR_REG_REG (   reg,
  op,
  data 
)    (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

Definition at line 1108 of file ncr53c8xx.h.

#define SCR_REG_SFBR (   reg,
  op,
  data 
)    (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

Definition at line 1105 of file ncr53c8xx.h.

#define SCR_RETURN   0x90080000

Definition at line 1233 of file ncr53c8xx.h.

#define SCR_SEL_ABS   0x40000000

Definition at line 986 of file ncr53c8xx.h.

#define SCR_SEL_ABS_ATN   0x41000000

Definition at line 987 of file ncr53c8xx.h.

#define SCR_SEL_TBL   0x42000000

Definition at line 988 of file ncr53c8xx.h.

#define SCR_SEL_TBL_ATN   0x43000000

Definition at line 989 of file ncr53c8xx.h.

#define SCR_SET (   f)    (0x58000000 | (f))

Definition at line 1042 of file ncr53c8xx.h.

#define SCR_SFBR_DATA   (0x00800000>>8ul) /* Use SFBR as data */

Definition at line 1121 of file ncr53c8xx.h.

#define SCR_SFBR_REG (   reg,
  op,
  data 
)    (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

Definition at line 1102 of file ncr53c8xx.h.

#define SCR_SHL   0x01000000

Definition at line 1113 of file ncr53c8xx.h.

#define SCR_SHR   0x05000000

Definition at line 1117 of file ncr53c8xx.h.

#define SCR_STATUS   0x03000000

Definition at line 929 of file ncr53c8xx.h.

#define SCR_STORE_ABS (   reg,
  n 
)    SCR_STORE_R(reg, SCR_NO_FLUSH2, n)

Definition at line 1185 of file ncr53c8xx.h.

#define SCR_STORE_ABS_F (   reg,
  n 
)    SCR_STORE_R(reg, 0, n)

Definition at line 1187 of file ncr53c8xx.h.

#define SCR_STORE_R (   reg,
  how,
  n 
)    (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))

Definition at line 1177 of file ncr53c8xx.h.

#define SCR_STORE_REL (   reg,
  n 
)    SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)

Definition at line 1186 of file ncr53c8xx.h.

#define SCR_STORE_REL_F (   reg,
  n 
)    SCR_STORE_R(reg, SCR_DSA_REL2, n)

Definition at line 1188 of file ncr53c8xx.h.

#define scr_to_cpu (   dw)    (dw)

Definition at line 374 of file ncr53c8xx.h.

#define SCR_TO_REG (   reg)    SCR_SFBR_REG(reg,SCR_OR,0)

Definition at line 1143 of file ncr53c8xx.h.

#define SCR_TRG   0x00000200

Definition at line 1046 of file ncr53c8xx.h.

#define SCR_WAIT_DISC   0x48000000

Definition at line 1026 of file ncr53c8xx.h.

#define SCR_WAIT_RESEL   0x50000000

Definition at line 1027 of file ncr53c8xx.h.

#define SCR_XOR   0x03000000

Definition at line 1115 of file ncr53c8xx.h.

#define SCSI_NCR_ALWAYS_SIMPLE_TAG

Definition at line 251 of file ncr53c8xx.h.

#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT

Definition at line 63 of file ncr53c8xx.h.

#define SCSI_NCR_CAN_QUEUE   (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)

Definition at line 261 of file ncr53c8xx.h.

#define SCSI_NCR_CMD_PER_LUN   (SCSI_NCR_MAX_TAGS)

Definition at line 262 of file ncr53c8xx.h.

#define SCSI_NCR_DEBUG_INFO_SUPPORT

Definition at line 64 of file ncr53c8xx.h.

#define SCSI_NCR_DRIVER_SAFE_SETUP
Value:
{ \
0, \
1, \
0, \
0, \
0, \
0, \
0, \
1, \
2, \
0, \
255, \
0x00, \
255, \
0, \
0, \
10, \
1, \
1, \
1, \
0, \
0, \
255 \
}

Definition at line 586 of file ncr53c8xx.h.

#define SCSI_NCR_DRIVER_SETUP
Value:
{ \
SCSI_NCR_SETUP_MASTER_PARITY, \
SCSI_NCR_SETUP_SCSI_PARITY, \
SCSI_NCR_SETUP_DISCONNECTION, \
SCSI_NCR_SETUP_SPECIAL_FEATURES, \
SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
0, \
0, \
1, \
0, \
SCSI_NCR_SETUP_DEFAULT_TAGS, \
SCSI_NCR_SETUP_DEFAULT_SYNC, \
0x00, \
7, \
0, \
1, \
SCSI_NCR_SETUP_SETTLE_TIME, \
0, \
0, \
1, \
0, \
0, \
255, \
0x00 \
}

Definition at line 554 of file ncr53c8xx.h.

#define SCSI_NCR_MAX_EXCLUDES   8

Definition at line 521 of file ncr53c8xx.h.

#define SCSI_NCR_MAX_LUN   (16)

Definition at line 268 of file ncr53c8xx.h.

#define SCSI_NCR_MAX_SCATTER   (127)

Definition at line 252 of file ncr53c8xx.h.

#define SCSI_NCR_MAX_SYNC   (80)

Definition at line 93 of file ncr53c8xx.h.

#define SCSI_NCR_MAX_TAGS   (8)

Definition at line 107 of file ncr53c8xx.h.

#define SCSI_NCR_MAX_TARGET   (16)

Definition at line 253 of file ncr53c8xx.h.

#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS

Definition at line 215 of file ncr53c8xx.h.

#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM

Definition at line 213 of file ncr53c8xx.h.

#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES

Definition at line 214 of file ncr53c8xx.h.

#define SCSI_NCR_PCIQ_WORK_AROUND_OPT   1

Definition at line 199 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_DEFAULT_SYNC   (250/(CONFIG_SCSI_NCR53C8XX_SYNC))

Definition at line 145 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_DEFAULT_TAGS   (0)

Definition at line 119 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_DISCONNECTION   (1)

Definition at line 160 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO   (0)

Definition at line 169 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_MASTER_PARITY   (1)

Definition at line 178 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_SCSI_PARITY   (1)

Definition at line 187 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_SETTLE_TIME   (2)

Definition at line 193 of file ncr53c8xx.h.

#define SCSI_NCR_SETUP_SPECIAL_FEATURES   (3)

Definition at line 91 of file ncr53c8xx.h.

#define SCSI_NCR_SG_TABLESIZE   (SCSI_NCR_MAX_SCATTER)

Definition at line 264 of file ncr53c8xx.h.

#define SCSI_NCR_TIMER_INTERVAL   (HZ)

Definition at line 265 of file ncr53c8xx.h.

#define SDP   0x01 /* sta: scsi parity signal */

Definition at line 684 of file ncr53c8xx.h.

#define SDU   0x80 /* cmd: disconnect will raise error */

Definition at line 630 of file ncr53c8xx.h.

#define SEL   0x20 /* sta: selected by another device */

Definition at line 789 of file ncr53c8xx.h.

#define SEM   0x10 /* r/w: message between host + ncr */

Definition at line 705 of file ncr53c8xx.h.

#define SGE   0x08 /* sta: gross error (over/underflow)*/

Definition at line 791 of file ncr53c8xx.h.

#define SIGP   0x20 /* r/w: message from host to ncr */

Definition at line 704 of file ncr53c8xx.h.

#define SIP   0x02 /* sta: scsi-interrupt */

Definition at line 708 of file ncr53c8xx.h.

#define SIR   0x04 /* int: script: interrupt instruct. */

Definition at line 673 of file ncr53c8xx.h.

#define SIRQD   0x01 /* r/w: disable INT pin */

Definition at line 714 of file ncr53c8xx.h.

#define SMODE   0xc0 /* SCSI bus mode (895/6 only) */

Definition at line 824 of file ncr53c8xx.h.

#define SMODE_HVD   0x40 /* High Voltage Differential */

Definition at line 825 of file ncr53c8xx.h.

#define SMODE_LVD   0xc0 /* Low Voltage Differential */

Definition at line 827 of file ncr53c8xx.h.

#define SMODE_SE   0x80 /* Single Ended */

Definition at line 826 of file ncr53c8xx.h.

#define SNDCRC   0x10 /* Send CRC Request */

Definition at line 896 of file ncr53c8xx.h.

#define SRE   0x20 /* r/w:e enable response to select */

Definition at line 642 of file ncr53c8xx.h.

#define SRST   0x40 /* mod: reset chip */

Definition at line 703 of file ncr53c8xx.h.

#define SRUN   0x02 /* sta: scripts are running */

Definition at line 713 of file ncr53c8xx.h.

#define SSI   0x08 /* int: script: single step */

Definition at line 672 of file ncr53c8xx.h.

#define SSM   0x10 /* mod: single step mode */

Definition at line 772 of file ncr53c8xx.h.

#define STD   0x04 /* cmd: start dma mode */

Definition at line 774 of file ncr53c8xx.h.

#define STO   0x0400/* sta: timeout (select) */

Definition at line 784 of file ncr53c8xx.h.

#define TE   0x80 /* c: tolerAnt enable */

Definition at line 818 of file ncr53c8xx.h.

#define U3EN   0x80 /* Enable Ultra 3 */

Definition at line 866 of file ncr53c8xx.h.

#define UDC   0x04 /* sta: unexpected disconnect */

Definition at line 792 of file ncr53c8xx.h.

#define ULTRA   0x80 /* cmd: ULTRA enable */

Definition at line 637 of file ncr53c8xx.h.

#define WHEN (   phase)    (0x00030000 | (phase))

Definition at line 1240 of file ncr53c8xx.h.

#define WOA   0x04 /* sta: arbitration won */

Definition at line 682 of file ncr53c8xx.h.

#define WRIE   0x01 /* mod: write and invalidate enable */

Definition at line 731 of file ncr53c8xx.h.

#define writeb_raw   writeb

Definition at line 318 of file ncr53c8xx.h.

#define writel_raw   writel

Definition at line 320 of file ncr53c8xx.h.

#define writew_raw   writew

Definition at line 319 of file ncr53c8xx.h.

#define WSR   0x01 /* sta: wide scsi received [W]*/

Definition at line 633 of file ncr53c8xx.h.

#define WSS   0x08 /* sta: wide scsi send [W]*/

Definition at line 632 of file ncr53c8xx.h.

#define XCLKH_DT
Value:
0x08 /* Extra clock of data hold on DT
transfer edge */

Definition at line 868 of file ncr53c8xx.h.

#define XCLKH_ST
Value:
0x04 /* Extra clock of data hold on ST
transfer edge */

Definition at line 869 of file ncr53c8xx.h.

#define XTIMOD   0x04 /* 64-bit Table Ind. Indexing Mode */

Definition at line 845 of file ncr53c8xx.h.

#define ZMOD   0x80 /* High Impedance Mode */

Definition at line 842 of file ncr53c8xx.h.

Typedef Documentation

typedef u32 ncrcmd

Definition at line 915 of file ncr53c8xx.h.

Function Documentation

void ncr53c8xx_exit ( void  )

Definition at line 8626 of file ncr53c8xx.c.

int ncr53c8xx_init ( void  )

Definition at line 8618 of file ncr53c8xx.c.

irqreturn_t ncr53c8xx_intr ( int  irq,
void dev_id 
)
void ncr53c8xx_release ( struct Scsi_Host host)

Definition at line 8530 of file ncr53c8xx.c.

struct Scsi_Host* ncr_attach ( struct scsi_host_template tpnt,
int  unit,
struct ncr_device device 
)
read

Definition at line 8297 of file ncr53c8xx.c.