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pgtable_64.h
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1 /*
2  * pgtable.h: SpitFire page table operations.
3  *
4  * Copyright 1996,1997 David S. Miller ([email protected])
5  * Copyright 1997,1998 Jakub Jelinek ([email protected])
6  */
7 
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
10 
11 /* This file contains the functions and defines necessary to modify and use
12  * the SpitFire page tables.
13  */
14 
15 #include <linux/compiler.h>
16 #include <linux/const.h>
17 #include <asm/types.h>
18 #include <asm/spitfire.h>
19 #include <asm/asi.h>
20 #include <asm/page.h>
21 #include <asm/processor.h>
22 
23 #include <asm-generic/pgtable-nopud.h>
24 
25 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
26  * The page copy blockops can use 0x6000000 to 0x8000000.
27  * The TSB is mapped in the 0x8000000 to 0xa000000 range.
28  * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
29  * The vmalloc area spans 0x100000000 to 0x200000000.
30  * Since modules need to be in the lowest 32-bits of the address space,
31  * we place them right before the OBP area from 0x10000000 to 0xf0000000.
32  * There is a single static kernel PMD which maps from 0x0 to address
33  * 0x400000000.
34  */
35 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
36 #define TSBMAP_BASE _AC(0x0000000008000000,UL)
37 #define MODULES_VADDR _AC(0x0000000010000000,UL)
38 #define MODULES_LEN _AC(0x00000000e0000000,UL)
39 #define MODULES_END _AC(0x00000000f0000000,UL)
40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42 #define VMALLOC_START _AC(0x0000000100000000,UL)
43 #define VMALLOC_END _AC(0x0000010000000000,UL)
44 #define VMEMMAP_BASE _AC(0x0000010000000000,UL)
45 
46 #define vmemmap ((struct page *)VMEMMAP_BASE)
47 
48 /* PMD_SHIFT determines the size of the area a second-level page
49  * table can map
50  */
51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-4))
52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
53 #define PMD_MASK (~(PMD_SIZE-1))
54 #define PMD_BITS (PAGE_SHIFT - 2)
55 
56 /* PGDIR_SHIFT determines what a third-level page table entry can map */
57 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-4) + PMD_BITS)
58 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
59 #define PGDIR_MASK (~(PGDIR_SIZE-1))
60 #define PGDIR_BITS (PAGE_SHIFT - 2)
61 
62 #if (PGDIR_SHIFT + PGDIR_BITS) != 44
63 #error Page table parameters do not cover virtual address space properly.
64 #endif
65 
66 #if (PMD_SHIFT != HPAGE_SHIFT)
67 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages.
68 #endif
69 
70 /* PMDs point to PTE tables which are 4K aligned. */
71 #define PMD_PADDR _AC(0xfffffffe,UL)
72 #define PMD_PADDR_SHIFT _AC(11,UL)
73 
74 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
75 #define PMD_ISHUGE _AC(0x00000001,UL)
76 
77 /* This is the PMD layout when PMD_ISHUGE is set. With 4MB huge
78  * pages, this frees up a bunch of bits in the layout that we can
79  * use for the protection settings and software metadata.
80  */
81 #define PMD_HUGE_PADDR _AC(0xfffff800,UL)
82 #define PMD_HUGE_PROTBITS _AC(0x000007ff,UL)
83 #define PMD_HUGE_PRESENT _AC(0x00000400,UL)
84 #define PMD_HUGE_WRITE _AC(0x00000200,UL)
85 #define PMD_HUGE_DIRTY _AC(0x00000100,UL)
86 #define PMD_HUGE_ACCESSED _AC(0x00000080,UL)
87 #define PMD_HUGE_EXEC _AC(0x00000040,UL)
88 #define PMD_HUGE_SPLITTING _AC(0x00000020,UL)
89 #endif
90 
91 /* PGDs point to PMD tables which are 8K aligned. */
92 #define PGD_PADDR _AC(0xfffffffc,UL)
93 #define PGD_PADDR_SHIFT _AC(11,UL)
94 
95 #ifndef __ASSEMBLY__
96 
97 #include <linux/sched.h>
98 
99 /* Entries per page directory level. */
100 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-4))
101 #define PTRS_PER_PMD (1UL << PMD_BITS)
102 #define PTRS_PER_PGD (1UL << PGDIR_BITS)
103 
104 /* Kernel has a separate 44bit address space. */
105 #define FIRST_USER_ADDRESS 0
106 
107 #define pte_ERROR(e) __builtin_trap()
108 #define pmd_ERROR(e) __builtin_trap()
109 #define pgd_ERROR(e) __builtin_trap()
110 
111 #endif /* !(__ASSEMBLY__) */
112 
113 /* PTE bits which are the same in SUN4U and SUN4V format. */
114 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
115 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
116 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */
117 
118 /* Advertise support for _PAGE_SPECIAL */
119 #define __HAVE_ARCH_PTE_SPECIAL
120 
121 /* SUN4U pte bits... */
122 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
123 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
124 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
125 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
126 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
127 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
128 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
129 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */
130 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
131 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
132 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
133 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
134 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
135 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
136 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
137 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
138 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
139 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
140 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
141 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
142 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
143 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
144 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
145 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
146 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
147 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
148 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
149 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
150 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
151 
152 /* SUN4V pte bits... */
153 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
154 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
155 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
156 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
157 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
158 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
159 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */
160 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
161 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
162 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
163 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
164 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
165 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
166 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
167 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
168 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
169 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
170 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
171 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
172 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
173 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
174 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
175 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
176 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
177 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
178 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
179 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
180 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
181 
182 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
183 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
184 
185 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
186 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
187 
188 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
189 #define __P000 __pgprot(0)
190 #define __P001 __pgprot(0)
191 #define __P010 __pgprot(0)
192 #define __P011 __pgprot(0)
193 #define __P100 __pgprot(0)
194 #define __P101 __pgprot(0)
195 #define __P110 __pgprot(0)
196 #define __P111 __pgprot(0)
197 
198 #define __S000 __pgprot(0)
199 #define __S001 __pgprot(0)
200 #define __S010 __pgprot(0)
201 #define __S011 __pgprot(0)
202 #define __S100 __pgprot(0)
203 #define __S101 __pgprot(0)
204 #define __S110 __pgprot(0)
205 #define __S111 __pgprot(0)
206 
207 #ifndef __ASSEMBLY__
208 
209 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
210 
211 extern unsigned long pte_sz_bits(unsigned long size);
212 
213 extern pgprot_t PAGE_KERNEL;
214 extern pgprot_t PAGE_KERNEL_LOCKED;
215 extern pgprot_t PAGE_COPY;
216 extern pgprot_t PAGE_SHARED;
217 
218 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
219 extern unsigned long _PAGE_IE;
220 extern unsigned long _PAGE_E;
221 extern unsigned long _PAGE_CACHE;
222 
223 extern unsigned long pg_iobits;
224 extern unsigned long _PAGE_ALL_SZ_BITS;
225 
226 extern struct page *mem_map_zero;
227 #define ZERO_PAGE(vaddr) (mem_map_zero)
228 
229 /* PFNs are real physical page numbers. However, mem_map only begins to record
230  * per-page information starting at pfn_base. This is to handle systems where
231  * the first physical page in the machine is at some huge physical address,
232  * such as 4GB. This is common on a partitioned E10000, for example.
233  */
234 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
235 {
236  unsigned long paddr = pfn << PAGE_SHIFT;
237 
238  BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
239  return __pte(paddr | pgprot_val(prot));
240 }
241 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
242 
243 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
244 extern pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot);
245 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
246 
247 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
248 
249 static inline pmd_t pmd_mkhuge(pmd_t pmd)
250 {
251  /* Do nothing, mk_pmd() does this part. */
252  return pmd;
253 }
254 #endif
255 
256 /* This one can be done with two shifts. */
257 static inline unsigned long pte_pfn(pte_t pte)
258 {
259  unsigned long ret;
260 
261  __asm__ __volatile__(
262  "\n661: sllx %1, %2, %0\n"
263  " srlx %0, %3, %0\n"
264  " .section .sun4v_2insn_patch, \"ax\"\n"
265  " .word 661b\n"
266  " sllx %1, %4, %0\n"
267  " srlx %0, %5, %0\n"
268  " .previous\n"
269  : "=r" (ret)
270  : "r" (pte_val(pte)),
271  "i" (21), "i" (21 + PAGE_SHIFT),
272  "i" (8), "i" (8 + PAGE_SHIFT));
273 
274  return ret;
275 }
276 #define pte_page(x) pfn_to_page(pte_pfn(x))
277 
278 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
279 {
280  unsigned long mask, tmp;
281 
282  /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
283  * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
284  *
285  * Even if we use negation tricks the result is still a 6
286  * instruction sequence, so don't try to play fancy and just
287  * do the most straightforward implementation.
288  *
289  * Note: We encode this into 3 sun4v 2-insn patch sequences.
290  */
291 
292  BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
293  __asm__ __volatile__(
294  "\n661: sethi %%uhi(%2), %1\n"
295  " sethi %%hi(%2), %0\n"
296  "\n662: or %1, %%ulo(%2), %1\n"
297  " or %0, %%lo(%2), %0\n"
298  "\n663: sllx %1, 32, %1\n"
299  " or %0, %1, %0\n"
300  " .section .sun4v_2insn_patch, \"ax\"\n"
301  " .word 661b\n"
302  " sethi %%uhi(%3), %1\n"
303  " sethi %%hi(%3), %0\n"
304  " .word 662b\n"
305  " or %1, %%ulo(%3), %1\n"
306  " or %0, %%lo(%3), %0\n"
307  " .word 663b\n"
308  " sllx %1, 32, %1\n"
309  " or %0, %1, %0\n"
310  " .previous\n"
311  : "=r" (mask), "=r" (tmp)
312  : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
313  _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
314  _PAGE_SPECIAL),
315  "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
316  _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
317  _PAGE_SPECIAL));
318 
319  return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
320 }
321 
322 static inline pte_t pgoff_to_pte(unsigned long off)
323 {
324  off <<= PAGE_SHIFT;
325 
326  __asm__ __volatile__(
327  "\n661: or %0, %2, %0\n"
328  " .section .sun4v_1insn_patch, \"ax\"\n"
329  " .word 661b\n"
330  " or %0, %3, %0\n"
331  " .previous\n"
332  : "=r" (off)
333  : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
334 
335  return __pte(off);
336 }
337 
338 static inline pgprot_t pgprot_noncached(pgprot_t prot)
339 {
340  unsigned long val = pgprot_val(prot);
341 
342  __asm__ __volatile__(
343  "\n661: andn %0, %2, %0\n"
344  " or %0, %3, %0\n"
345  " .section .sun4v_2insn_patch, \"ax\"\n"
346  " .word 661b\n"
347  " andn %0, %4, %0\n"
348  " or %0, %5, %0\n"
349  " .previous\n"
350  : "=r" (val)
351  : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
352  "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
353 
354  return __pgprot(val);
355 }
356 /* Various pieces of code check for platform support by ifdef testing
357  * on "pgprot_noncached". That's broken and should be fixed, but for
358  * now...
359  */
360 #define pgprot_noncached pgprot_noncached
361 
362 #ifdef CONFIG_HUGETLB_PAGE
363 static inline pte_t pte_mkhuge(pte_t pte)
364 {
365  unsigned long mask;
366 
367  __asm__ __volatile__(
368  "\n661: sethi %%uhi(%1), %0\n"
369  " sllx %0, 32, %0\n"
370  " .section .sun4v_2insn_patch, \"ax\"\n"
371  " .word 661b\n"
372  " mov %2, %0\n"
373  " nop\n"
374  " .previous\n"
375  : "=r" (mask)
376  : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
377 
378  return __pte(pte_val(pte) | mask);
379 }
380 #endif
381 
382 static inline pte_t pte_mkdirty(pte_t pte)
383 {
384  unsigned long val = pte_val(pte), tmp;
385 
386  __asm__ __volatile__(
387  "\n661: or %0, %3, %0\n"
388  " nop\n"
389  "\n662: nop\n"
390  " nop\n"
391  " .section .sun4v_2insn_patch, \"ax\"\n"
392  " .word 661b\n"
393  " sethi %%uhi(%4), %1\n"
394  " sllx %1, 32, %1\n"
395  " .word 662b\n"
396  " or %1, %%lo(%4), %1\n"
397  " or %0, %1, %0\n"
398  " .previous\n"
399  : "=r" (val), "=r" (tmp)
400  : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
401  "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
402 
403  return __pte(val);
404 }
405 
406 static inline pte_t pte_mkclean(pte_t pte)
407 {
408  unsigned long val = pte_val(pte), tmp;
409 
410  __asm__ __volatile__(
411  "\n661: andn %0, %3, %0\n"
412  " nop\n"
413  "\n662: nop\n"
414  " nop\n"
415  " .section .sun4v_2insn_patch, \"ax\"\n"
416  " .word 661b\n"
417  " sethi %%uhi(%4), %1\n"
418  " sllx %1, 32, %1\n"
419  " .word 662b\n"
420  " or %1, %%lo(%4), %1\n"
421  " andn %0, %1, %0\n"
422  " .previous\n"
423  : "=r" (val), "=r" (tmp)
424  : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
425  "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
426 
427  return __pte(val);
428 }
429 
430 static inline pte_t pte_mkwrite(pte_t pte)
431 {
432  unsigned long val = pte_val(pte), mask;
433 
434  __asm__ __volatile__(
435  "\n661: mov %1, %0\n"
436  " nop\n"
437  " .section .sun4v_2insn_patch, \"ax\"\n"
438  " .word 661b\n"
439  " sethi %%uhi(%2), %0\n"
440  " sllx %0, 32, %0\n"
441  " .previous\n"
442  : "=r" (mask)
443  : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
444 
445  return __pte(val | mask);
446 }
447 
448 static inline pte_t pte_wrprotect(pte_t pte)
449 {
450  unsigned long val = pte_val(pte), tmp;
451 
452  __asm__ __volatile__(
453  "\n661: andn %0, %3, %0\n"
454  " nop\n"
455  "\n662: nop\n"
456  " nop\n"
457  " .section .sun4v_2insn_patch, \"ax\"\n"
458  " .word 661b\n"
459  " sethi %%uhi(%4), %1\n"
460  " sllx %1, 32, %1\n"
461  " .word 662b\n"
462  " or %1, %%lo(%4), %1\n"
463  " andn %0, %1, %0\n"
464  " .previous\n"
465  : "=r" (val), "=r" (tmp)
466  : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
467  "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
468 
469  return __pte(val);
470 }
471 
472 static inline pte_t pte_mkold(pte_t pte)
473 {
474  unsigned long mask;
475 
476  __asm__ __volatile__(
477  "\n661: mov %1, %0\n"
478  " nop\n"
479  " .section .sun4v_2insn_patch, \"ax\"\n"
480  " .word 661b\n"
481  " sethi %%uhi(%2), %0\n"
482  " sllx %0, 32, %0\n"
483  " .previous\n"
484  : "=r" (mask)
485  : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
486 
487  mask |= _PAGE_R;
488 
489  return __pte(pte_val(pte) & ~mask);
490 }
491 
492 static inline pte_t pte_mkyoung(pte_t pte)
493 {
494  unsigned long mask;
495 
496  __asm__ __volatile__(
497  "\n661: mov %1, %0\n"
498  " nop\n"
499  " .section .sun4v_2insn_patch, \"ax\"\n"
500  " .word 661b\n"
501  " sethi %%uhi(%2), %0\n"
502  " sllx %0, 32, %0\n"
503  " .previous\n"
504  : "=r" (mask)
505  : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
506 
507  mask |= _PAGE_R;
508 
509  return __pte(pte_val(pte) | mask);
510 }
511 
512 static inline pte_t pte_mkspecial(pte_t pte)
513 {
514  pte_val(pte) |= _PAGE_SPECIAL;
515  return pte;
516 }
517 
518 static inline unsigned long pte_young(pte_t pte)
519 {
520  unsigned long mask;
521 
522  __asm__ __volatile__(
523  "\n661: mov %1, %0\n"
524  " nop\n"
525  " .section .sun4v_2insn_patch, \"ax\"\n"
526  " .word 661b\n"
527  " sethi %%uhi(%2), %0\n"
528  " sllx %0, 32, %0\n"
529  " .previous\n"
530  : "=r" (mask)
531  : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
532 
533  return (pte_val(pte) & mask);
534 }
535 
536 static inline unsigned long pte_dirty(pte_t pte)
537 {
538  unsigned long mask;
539 
540  __asm__ __volatile__(
541  "\n661: mov %1, %0\n"
542  " nop\n"
543  " .section .sun4v_2insn_patch, \"ax\"\n"
544  " .word 661b\n"
545  " sethi %%uhi(%2), %0\n"
546  " sllx %0, 32, %0\n"
547  " .previous\n"
548  : "=r" (mask)
549  : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
550 
551  return (pte_val(pte) & mask);
552 }
553 
554 static inline unsigned long pte_write(pte_t pte)
555 {
556  unsigned long mask;
557 
558  __asm__ __volatile__(
559  "\n661: mov %1, %0\n"
560  " nop\n"
561  " .section .sun4v_2insn_patch, \"ax\"\n"
562  " .word 661b\n"
563  " sethi %%uhi(%2), %0\n"
564  " sllx %0, 32, %0\n"
565  " .previous\n"
566  : "=r" (mask)
567  : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
568 
569  return (pte_val(pte) & mask);
570 }
571 
572 static inline unsigned long pte_exec(pte_t pte)
573 {
574  unsigned long mask;
575 
576  __asm__ __volatile__(
577  "\n661: sethi %%hi(%1), %0\n"
578  " .section .sun4v_1insn_patch, \"ax\"\n"
579  " .word 661b\n"
580  " mov %2, %0\n"
581  " .previous\n"
582  : "=r" (mask)
583  : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
584 
585  return (pte_val(pte) & mask);
586 }
587 
588 static inline unsigned long pte_file(pte_t pte)
589 {
590  unsigned long val = pte_val(pte);
591 
592  __asm__ __volatile__(
593  "\n661: and %0, %2, %0\n"
594  " .section .sun4v_1insn_patch, \"ax\"\n"
595  " .word 661b\n"
596  " and %0, %3, %0\n"
597  " .previous\n"
598  : "=r" (val)
599  : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
600 
601  return val;
602 }
603 
604 static inline unsigned long pte_present(pte_t pte)
605 {
606  unsigned long val = pte_val(pte);
607 
608  __asm__ __volatile__(
609  "\n661: and %0, %2, %0\n"
610  " .section .sun4v_1insn_patch, \"ax\"\n"
611  " .word 661b\n"
612  " and %0, %3, %0\n"
613  " .previous\n"
614  : "=r" (val)
615  : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
616 
617  return val;
618 }
619 
620 static inline unsigned long pte_special(pte_t pte)
621 {
622  return pte_val(pte) & _PAGE_SPECIAL;
623 }
624 
625 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
626 static inline int pmd_young(pmd_t pmd)
627 {
628  return pmd_val(pmd) & PMD_HUGE_ACCESSED;
629 }
630 
631 static inline int pmd_write(pmd_t pmd)
632 {
633  return pmd_val(pmd) & PMD_HUGE_WRITE;
634 }
635 
636 static inline unsigned long pmd_pfn(pmd_t pmd)
637 {
638  unsigned long val = pmd_val(pmd) & PMD_HUGE_PADDR;
639 
640  return val >> (PAGE_SHIFT - PMD_PADDR_SHIFT);
641 }
642 
643 static inline int pmd_large(pmd_t pmd)
644 {
645  return (pmd_val(pmd) & (PMD_ISHUGE | PMD_HUGE_PRESENT)) ==
646  (PMD_ISHUGE | PMD_HUGE_PRESENT);
647 }
648 
649 static inline int pmd_trans_splitting(pmd_t pmd)
650 {
651  return (pmd_val(pmd) & (PMD_ISHUGE|PMD_HUGE_SPLITTING)) ==
652  (PMD_ISHUGE|PMD_HUGE_SPLITTING);
653 }
654 
655 static inline int pmd_trans_huge(pmd_t pmd)
656 {
657  return pmd_val(pmd) & PMD_ISHUGE;
658 }
659 
660 #define has_transparent_hugepage() 1
661 
662 static inline pmd_t pmd_mkold(pmd_t pmd)
663 {
664  pmd_val(pmd) &= ~PMD_HUGE_ACCESSED;
665  return pmd;
666 }
667 
668 static inline pmd_t pmd_wrprotect(pmd_t pmd)
669 {
670  pmd_val(pmd) &= ~PMD_HUGE_WRITE;
671  return pmd;
672 }
673 
674 static inline pmd_t pmd_mkdirty(pmd_t pmd)
675 {
676  pmd_val(pmd) |= PMD_HUGE_DIRTY;
677  return pmd;
678 }
679 
680 static inline pmd_t pmd_mkyoung(pmd_t pmd)
681 {
682  pmd_val(pmd) |= PMD_HUGE_ACCESSED;
683  return pmd;
684 }
685 
686 static inline pmd_t pmd_mkwrite(pmd_t pmd)
687 {
688  pmd_val(pmd) |= PMD_HUGE_WRITE;
689  return pmd;
690 }
691 
692 static inline pmd_t pmd_mknotpresent(pmd_t pmd)
693 {
694  pmd_val(pmd) &= ~PMD_HUGE_PRESENT;
695  return pmd;
696 }
697 
698 static inline pmd_t pmd_mksplitting(pmd_t pmd)
699 {
700  pmd_val(pmd) |= PMD_HUGE_SPLITTING;
701  return pmd;
702 }
703 
704 extern pgprot_t pmd_pgprot(pmd_t entry);
705 #endif
706 
707 static inline int pmd_present(pmd_t pmd)
708 {
709  return pmd_val(pmd) != 0U;
710 }
711 
712 #define pmd_none(pmd) (!pmd_val(pmd))
713 
714 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
715 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
716  pmd_t *pmdp, pmd_t pmd);
717 #else
718 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
719  pmd_t *pmdp, pmd_t pmd)
720 {
721  *pmdp = pmd;
722 }
723 #endif
724 
725 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
726 {
727  unsigned long val = __pa((unsigned long) (ptep)) >> PMD_PADDR_SHIFT;
728 
729  pmd_val(*pmdp) = val;
730 }
731 
732 #define pud_set(pudp, pmdp) \
733  (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> PGD_PADDR_SHIFT))
734 static inline unsigned long __pmd_page(pmd_t pmd)
735 {
736  unsigned long paddr = (unsigned long) pmd_val(pmd);
737 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
738  if (pmd_val(pmd) & PMD_ISHUGE)
739  paddr &= PMD_HUGE_PADDR;
740 #endif
741  paddr <<= PMD_PADDR_SHIFT;
742  return ((unsigned long) __va(paddr));
743 }
744 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
745 #define pud_page_vaddr(pud) \
746  ((unsigned long) __va((((unsigned long)pud_val(pud))<<PGD_PADDR_SHIFT)))
747 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
748 #define pmd_bad(pmd) (0)
749 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
750 #define pud_none(pud) (!pud_val(pud))
751 #define pud_bad(pud) (0)
752 #define pud_present(pud) (pud_val(pud) != 0U)
753 #define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
754 
755 /* Same in both SUN4V and SUN4U. */
756 #define pte_none(pte) (!pte_val(pte))
757 
758 /* to find an entry in a page-table-directory. */
759 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
760 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
761 
762 /* to find an entry in a kernel page-table-directory */
763 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
764 
765 /* Find an entry in the second-level page table.. */
766 #define pmd_offset(pudp, address) \
767  ((pmd_t *) pud_page_vaddr(*(pudp)) + \
768  (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
769 
770 /* Find an entry in the third-level page table.. */
771 #define pte_index(dir, address) \
772  ((pte_t *) __pmd_page(*(dir)) + \
773  ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
774 #define pte_offset_kernel pte_index
775 #define pte_offset_map pte_index
776 #define pte_unmap(pte) do { } while (0)
777 
778 /* Actual page table PTE updates. */
779 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
780  pte_t *ptep, pte_t orig, int fullmm);
781 
782 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
783 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
784  unsigned long addr,
785  pmd_t *pmdp)
786 {
787  pmd_t pmd = *pmdp;
788  set_pmd_at(mm, addr, pmdp, __pmd(0U));
789  return pmd;
790 }
791 
792 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
793  pte_t *ptep, pte_t pte, int fullmm)
794 {
795  pte_t orig = *ptep;
796 
797  *ptep = pte;
798 
799  /* It is more efficient to let flush_tlb_kernel_range()
800  * handle init_mm tlb flushes.
801  *
802  * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
803  * and SUN4V pte layout, so this inline test is fine.
804  */
805  if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
806  tlb_batch_add(mm, addr, ptep, orig, fullmm);
807 }
808 
809 #define set_pte_at(mm,addr,ptep,pte) \
810  __set_pte_at((mm), (addr), (ptep), (pte), 0)
811 
812 #define pte_clear(mm,addr,ptep) \
813  set_pte_at((mm), (addr), (ptep), __pte(0UL))
814 
815 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
816 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
817  __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
818 
819 #ifdef DCACHE_ALIASING_POSSIBLE
820 #define __HAVE_ARCH_MOVE_PTE
821 #define move_pte(pte, prot, old_addr, new_addr) \
822 ({ \
823  pte_t newpte = (pte); \
824  if (tlb_type != hypervisor && pte_present(pte)) { \
825  unsigned long this_pfn = pte_pfn(pte); \
826  \
827  if (pfn_valid(this_pfn) && \
828  (((old_addr) ^ (new_addr)) & (1 << 13))) \
829  flush_dcache_page_all(current->mm, \
830  pfn_to_page(this_pfn)); \
831  } \
832  newpte; \
833 })
834 #endif
835 
836 extern pgd_t swapper_pg_dir[2048];
837 extern pmd_t swapper_low_pmd_dir[2048];
838 
839 extern void paging_init(void);
840 extern unsigned long find_ecache_flush_span(unsigned long size);
841 
842 struct seq_file;
843 extern void mmu_info(struct seq_file *);
844 
845 struct vm_area_struct;
846 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
847 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
848 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
849  pmd_t *pmd);
850 
851 #define __HAVE_ARCH_PGTABLE_DEPOSIT
852 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
853 
854 #define __HAVE_ARCH_PGTABLE_WITHDRAW
855 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
856 #endif
857 
858 /* Encode and de-code a swap entry */
859 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
860 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
861 #define __swp_entry(type, offset) \
862  ( (swp_entry_t) \
863  { \
864  (((long)(type) << PAGE_SHIFT) | \
865  ((long)(offset) << (PAGE_SHIFT + 8UL))) \
866  } )
867 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
868 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
869 
870 /* File offset in PTE support. */
871 extern unsigned long pte_file(pte_t);
872 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
873 extern pte_t pgoff_to_pte(unsigned long);
874 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
875 
876 extern unsigned long sparc64_valid_addr_bitmap[];
877 
878 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
879 static inline bool kern_addr_valid(unsigned long addr)
880 {
881  unsigned long paddr = __pa(addr);
882 
883  if ((paddr >> 41UL) != 0UL)
884  return false;
885  return test_bit(paddr >> 22, sparc64_valid_addr_bitmap);
886 }
887 
888 extern int page_in_phys_avail(unsigned long paddr);
889 
890 /*
891  * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
892  * its high 4 bits. These macros/functions put it there or get it from there.
893  */
894 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
895 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
896 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
897 
898 extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
899  unsigned long, pgprot_t);
900 
901 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
902  unsigned long from, unsigned long pfn,
903  unsigned long size, pgprot_t prot)
904 {
905  unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
906  int space = GET_IOSPACE(pfn);
907  unsigned long phys_base;
908 
909  phys_base = offset | (((unsigned long) space) << 32UL);
910 
911  return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
912 }
913 
914 #include <asm-generic/pgtable.h>
915 
916 /* We provide our own get_unmapped_area to cope with VA holes and
917  * SHM area cache aliasing for userland.
918  */
919 #define HAVE_ARCH_UNMAPPED_AREA
920 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
921 
922 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
923  * the largest alignment possible such that larget PTEs can be used.
924  */
925 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
926  unsigned long, unsigned long,
927  unsigned long);
928 #define HAVE_ARCH_FB_UNMAPPED_AREA
929 
930 extern void pgtable_cache_init(void);
931 extern void sun4v_register_fault_status(void);
932 extern void sun4v_ktsb_register(void);
933 extern void __init cheetah_ecache_flush_init(void);
934 extern void sun4v_patch_tlb_handlers(void);
935 
936 extern unsigned long cmdline_memory_size;
937 
938 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
939 
940 #endif /* !(__ASSEMBLY__) */
941 
942 #endif /* !(_SPARC64_PGTABLE_H) */
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