#include <linux/sched.h>
#include <linux/linkage.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/ftrace.h>
#include <linux/irq.h>
#include <linux/kmemleak.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <linux/atomic.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/iommu.h>
#include <asm/upa.h>
#include <asm/oplib.h>
#include <asm/prom.h>
#include <asm/timer.h>
#include <asm/smp.h>
#include <asm/starfire.h>
#include <asm/uaccess.h>
#include <asm/cache.h>
#include <asm/cpudata.h>
#include <asm/auxio.h>
#include <asm/head.h>
#include <asm/hypervisor.h>
#include <asm/cacheflush.h>
#include "entry.h"
#include "cpumap.h"
#include "kstack.h"
Go to the source code of this file.
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unsigned char | irq_alloc (unsigned int dev_handle, unsigned int dev_ino) |
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int | arch_show_interrupts (struct seq_file *p, int prec) |
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void | irq_install_pre_handler (int irq, void(*func)(unsigned int, void *, void *), void *arg1, void *arg2) |
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unsigned int | build_irq (int inofixup, unsigned long iclr, unsigned long imap) |
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unsigned int | sun4v_build_irq (u32 devhandle, unsigned int devino) |
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unsigned int | sun4v_build_virq (u32 devhandle, unsigned int devino) |
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void | ack_bad_irq (unsigned int irq) |
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void __irq_entry | handler_irq (int pil, struct pt_regs *regs) |
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void | do_softirq (void) |
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void notrace | init_irqwork_curcpu (void) |
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void __cpuinit notrace | sun4v_register_mondo_queues (int this_cpu) |
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void __init | init_IRQ (void) |
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void ack_bad_irq |
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unsigned int |
irq | ) |
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unsigned int build_irq |
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int |
inofixup, |
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unsigned long |
iclr, |
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unsigned long |
imap |
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) |
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The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.
The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.
Definition at line 936 of file irq_64.c.
unsigned char irq_alloc |
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unsigned int |
dev_handle, |
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unsigned int |
dev_ino |
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) |
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unsigned int sun4v_build_irq |
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u32 |
devhandle, |
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unsigned int |
devino |
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) |
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unsigned int sun4v_build_virq |
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u32 |
devhandle, |
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unsigned int |
devino |
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) |
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unsigned long ivector_table_pa |