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| #define | ST_VENDOR_ID 0x0483 |
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| #define | ST5481_PRODUCT_ID 0x4810 |
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| #define | ST5481_PRODUCT_ID_MASK 0xFFF0 |
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| #define | EP_CTRL 0x00U /* Control endpoint */ |
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| #define | EP_INT 0x01U /* Interrupt endpoint */ |
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| #define | EP_B1_OUT 0x02U /* B1 channel out */ |
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| #define | EP_B1_IN 0x03U /* B1 channel in */ |
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| #define | EP_B2_OUT 0x04U /* B2 channel out */ |
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| #define | EP_B2_IN 0x05U /* B2 channel in */ |
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| #define | EP_D_OUT 0x06U /* D channel out */ |
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| #define | EP_D_IN 0x07U /* D channel in */ |
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| #define | NUM_ISO_PACKETS_D 20 |
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| #define | NUM_ISO_PACKETS_B 20 |
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| #define | SIZE_ISO_PACKETS_D_IN 16 |
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| #define | SIZE_ISO_PACKETS_D_OUT 2 |
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| #define | SIZE_ISO_PACKETS_B_IN 32 |
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| #define | SIZE_ISO_PACKETS_B_OUT 8 |
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| #define | B_FLOW_ADJUST 2 |
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| #define | LBA 0x02 /* S loopback */ |
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| #define | SET_DEFAULT 0x06 /* Soft reset */ |
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| #define | LBB 0x1D /* S maintenance loopback */ |
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| #define | STT 0x1e /* S force transmission signals */ |
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| #define | SDA_MIN 0x20 /* SDA-sin minimal value */ |
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| #define | SDA_MAX 0x21 /* SDA-sin maximal value */ |
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| #define | SDELAY_VALUE 0x22 /* Delay between Tx and Rx clock */ |
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| #define | IN_D_COUNTER 0x36 /* D receive channel fifo counter */ |
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| #define | OUT_D_COUNTER 0x37 /* D transmit channel fifo counter */ |
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| #define | IN_B1_COUNTER 0x38 /* B1 receive channel fifo counter */ |
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| #define | OUT_B1_COUNTER 0x39 /* B1 transmit channel fifo counter */ |
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| #define | IN_B2_COUNTER 0x3a /* B2 receive channel fifo counter */ |
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| #define | OUT_B2_COUNTER 0x3b /* B2 transmit channel fifo counter */ |
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| #define | FFCTRL_IN_D 0x3C /* D receive channel fifo threshold low */ |
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| #define | FFCTRH_IN_D 0x3D /* D receive channel fifo threshold high */ |
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| #define | FFCTRL_OUT_D 0x3E /* D transmit channel fifo threshold low */ |
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| #define | FFCTRH_OUT_D 0x3F /* D transmit channel fifo threshold high */ |
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| #define | FFCTRL_IN_B1 0x40 /* B1 receive channel fifo threshold low */ |
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| #define | FFCTRH_IN_B1 0x41 /* B1 receive channel fifo threshold high */ |
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| #define | FFCTRL_OUT_B1 0x42 /* B1 transmit channel fifo threshold low */ |
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| #define | FFCTRH_OUT_B1 0x43 /* B1 transmit channel fifo threshold high */ |
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| #define | FFCTRL_IN_B2 0x44 /* B2 receive channel fifo threshold low */ |
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| #define | FFCTRH_IN_B2 0x45 /* B2 receive channel fifo threshold high */ |
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| #define | FFCTRL_OUT_B2 0x46 /* B2 transmit channel fifo threshold low */ |
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| #define | FFCTRH_OUT_B2 0x47 /* B2 transmit channel fifo threshold high */ |
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| #define | MPMSK 0x4A /* Multi purpose interrupt MASK register */ |
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| #define | FFMSK_D 0x4c /* D fifo interrupt MASK register */ |
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| #define | FFMSK_B1 0x4e /* B1 fifo interrupt MASK register */ |
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| #define | FFMSK_B2 0x50 /* B2 fifo interrupt MASK register */ |
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| #define | GPIO_DIR 0x52 /* GPIO pins direction registers */ |
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| #define | GPIO_OUT 0x53 /* GPIO pins output register */ |
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| #define | GPIO_IN 0x54 /* GPIO pins input register */ |
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| #define | TXCI 0x56 /* CI command to be transmitted */ |
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| #define | MPINT 0 |
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| #define | FFINT_D 1 |
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| #define | FFINT_B1 2 |
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| #define | FFINT_B2 3 |
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| #define | CCIST 4 |
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| #define | GPIO_INT 5 |
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| #define | INT_PKT_SIZE 6 |
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| #define | LSD_INT 0x80 /* S line activity detected */ |
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| #define | RXCI_INT 0x40 /* Indicate primitive arrived */ |
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| #define | DEN_INT 0x20 /* Signal enabling data out of D Tx fifo */ |
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| #define | DCOLL_INT 0x10 /* D channel collision */ |
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| #define | AMIVN_INT 0x04 /* AMI violation number reached 2 */ |
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| #define | INFOI_INT 0x04 /* INFOi changed */ |
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| #define | DRXON_INT 0x02 /* Reception channel active */ |
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| #define | GPCHG_INT 0x01 /* GPIO pin value changed */ |
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| #define | IN_OVERRUN 0x80 /* In fifo overrun */ |
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| #define | OUT_UNDERRUN 0x40 /* Out fifo underrun */ |
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| #define | IN_UP 0x20 /* In fifo thresholdh up-crossed */ |
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| #define | IN_DOWN 0x10 /* In fifo thresholdl down-crossed */ |
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| #define | OUT_UP 0x08 /* Out fifo thresholdh up-crossed */ |
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| #define | OUT_DOWN 0x04 /* Out fifo thresholdl down-crossed */ |
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| #define | IN_COUNTER_ZEROED 0x02 /* In down-counter reached 0 */ |
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| #define | OUT_COUNTER_ZEROED 0x01 /* Out down-counter reached 0 */ |
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| #define | ANY_REC_INT (IN_OVERRUN + IN_UP + IN_DOWN + IN_COUNTER_ZEROED) |
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| #define | ANY_XMIT_INT (OUT_UNDERRUN + OUT_UP + OUT_DOWN + OUT_COUNTER_ZEROED) |
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| #define | ST5481_CMD_DR 0x0 /* Deactivation Request */ |
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| #define | ST5481_CMD_RES 0x1 /* state machine RESet */ |
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| #define | ST5481_CMD_TM1 0x2 /* Test Mode 1 */ |
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| #define | ST5481_CMD_TM2 0x3 /* Test Mode 2 */ |
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| #define | ST5481_CMD_PUP 0x7 /* Power UP */ |
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| #define | ST5481_CMD_AR8 0x8 /* Activation Request class 1 */ |
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| #define | ST5481_CMD_AR10 0x9 /* Activation Request class 2 */ |
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| #define | ST5481_CMD_ARL 0xA /* Activation Request Loopback */ |
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| #define | ST5481_CMD_PDN 0xF /* Power DoWn */ |
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| #define | B1_LED 0x10U |
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| #define | B2_LED 0x20U |
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| #define | GREEN_LED 0x40U |
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| #define | RED_LED 0x80U |
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| #define | DOUT_STATE_COUNT (ST_DOUT_WAIT_FOR_RESET + 1) |
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| #define | DOUT_EVENT_COUNT (EV_DOUT_UNDERRUN + 1) |
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| #define | L1_STATE_COUNT (ST_L1_F8 + 1) |
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| #define | L1_EVENT_COUNT (EV_TIMER3 + 1) |
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| #define | ERR(format, arg...) printk(KERN_ERR "%s:%s: " format "\n" , __FILE__, __func__ , ## arg) |
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| #define | WARNING(format, arg...) printk(KERN_WARNING "%s:%s: " format "\n" , __FILE__, __func__ , ## arg) |
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| #define | INFO(format, arg...) printk(KERN_INFO "%s:%s: " format "\n" , __FILE__, __func__ , ## arg) |
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| #define | MAX_EP0_MSG 16 |
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| #define | MAX_DFRAME_LEN_L1 300 |
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| #define | HSCX_BUFMAX 4096 |
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| #define | TIMER3_VALUE 7000 |
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| #define | SUBMIT_URB(urb, mem_flags) |
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| #define | __debug_variable st5481_debug |
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| #define | DBG_ISO_PACKET(level, urb) do {} while (0) |
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1.8.2