Data Structures
struct	d40_phy_lli

struct	d40_phy_lli_bidir

struct	d40_log_lli

struct	d40_log_lli_bidir

struct	d40_log_lli_full

struct	d40_def_lcsp

Macros
#define	D40_DREG_PCBASE 0x400

#define	D40_DREG_PCDELTA (8 * 4)

#define	D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */

#define	D40_LCPA_CHAN_SIZE 32

#define	D40_LCPA_CHAN_DST_DELTA 16

#define	D40_TYPE_TO_GROUP(type) (type / 16)

#define	D40_TYPE_TO_EVENT(type) (type % 16)

#define	D40_GROUP_SIZE 8

#define	D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)

#define	D40_SREG_CFG_MST_POS 15

#define	D40_SREG_CFG_TIM_POS 14

#define	D40_SREG_CFG_EIM_POS 13

#define	D40_SREG_CFG_LOG_INCR_POS 12

#define	D40_SREG_CFG_PHY_PEN_POS 12

#define	D40_SREG_CFG_PSIZE_POS 10

#define	D40_SREG_CFG_ESIZE_POS 8

#define	D40_SREG_CFG_PRI_POS 7

#define	D40_SREG_CFG_LBE_POS 6

#define	D40_SREG_CFG_LOG_GIM_POS 5

#define	D40_SREG_CFG_LOG_MFU_POS 4

#define	D40_SREG_CFG_PHY_TM_POS 4

#define	D40_SREG_CFG_PHY_EVTL_POS 0

#define	D40_SREG_ELEM_PHY_ECNT_POS 16

#define	D40_SREG_ELEM_PHY_EIDX_POS 0

#define	D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)

#define	D40_SREG_LNK_PHY_TCP_POS 0

#define	D40_SREG_LNK_PHY_LMP_POS 1

#define	D40_SREG_LNK_PHY_PRE_POS 2

#define	D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL

#define	D40_SREG_ELEM_LOG_ECNT_POS 16

#define	D40_SREG_ELEM_LOG_LIDX_POS 8

#define	D40_SREG_ELEM_LOG_LOS_POS 1

#define	D40_SREG_ELEM_LOG_TCP_POS 0

#define	D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)

#define	D40_EVENTLINE_POS(i) (2 * i)

#define	D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))

#define	D40_MEM_LCSP0_ECNT_POS 16

#define	D40_MEM_LCSP0_SPTR_POS 0

#define	D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)

#define	D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)

#define	D40_MEM_LCSP1_SPTR_POS 16

#define	D40_MEM_LCSP1_SCFG_MST_POS 15

#define	D40_MEM_LCSP1_SCFG_TIM_POS 14

#define	D40_MEM_LCSP1_SCFG_EIM_POS 13

#define	D40_MEM_LCSP1_SCFG_INCR_POS 12

#define	D40_MEM_LCSP1_SCFG_PSIZE_POS 10

#define	D40_MEM_LCSP1_SCFG_ESIZE_POS 8

#define	D40_MEM_LCSP1_SLOS_POS 1

#define	D40_MEM_LCSP1_STCP_POS 0

#define	D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)

#define	D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)

#define	D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)

#define	D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)

#define	D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)

#define	D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)

#define	D40_MEM_LCSP2_ECNT_POS 16

#define	D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)

#define	D40_MEM_LCSP3_DCFG_MST_POS 15

#define	D40_MEM_LCSP3_DCFG_TIM_POS 14

#define	D40_MEM_LCSP3_DCFG_EIM_POS 13

#define	D40_MEM_LCSP3_DCFG_INCR_POS 12

#define	D40_MEM_LCSP3_DCFG_PSIZE_POS 10

#define	D40_MEM_LCSP3_DCFG_ESIZE_POS 8

#define	D40_MEM_LCSP3_DLOS_POS 1

#define	D40_MEM_LCSP3_DTCP_POS 0

#define	D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)

#define	D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)

#define	D40_CHAN_REG_SSCFG 0x00

#define	D40_CHAN_REG_SSELT 0x04

#define	D40_CHAN_REG_SSPTR 0x08

#define	D40_CHAN_REG_SSLNK 0x0C

#define	D40_CHAN_REG_SDCFG 0x10

#define	D40_CHAN_REG_SDELT 0x14

#define	D40_CHAN_REG_SDPTR 0x18

#define	D40_CHAN_REG_SDLNK 0x1C

#define	D40_DREG_GCC 0x000

#define	D40_DREG_GCC_ENA 0x1

#define	D40_DREG_GCC_ENABLE_ALL 0xff01

#define	D40_DREG_GCC_EVTGRP_POS 8

#define	D40_DREG_GCC_SRC 0

#define	D40_DREG_GCC_DST 1

#define	D40_DREG_GCC_EVTGRP_ENA(x, y) (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))

#define	D40_DREG_PRTYP 0x004

#define	D40_DREG_PRSME 0x008

#define	D40_DREG_PRSMO 0x00C

#define	D40_DREG_PRMSE 0x010

#define	D40_DREG_PRMSO 0x014

#define	D40_DREG_PRMOE 0x018

#define	D40_DREG_PRMOO 0x01C

#define	D40_DREG_PRMO_PCHAN_BASIC 0x1

#define	D40_DREG_PRMO_PCHAN_MODULO 0x2

#define	D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3

#define	D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1

#define	D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2

#define	D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3

#define	D40_DREG_LCPA 0x020

#define	D40_DREG_LCLA 0x024

#define	D40_DREG_ACTIVE 0x050

#define	D40_DREG_ACTIVO 0x054

#define	D40_DREG_FSEB1 0x058

#define	D40_DREG_FSEB2 0x05C

#define	D40_DREG_PCMIS 0x060

#define	D40_DREG_PCICR 0x064

#define	D40_DREG_PCTIS 0x068

#define	D40_DREG_PCEIS 0x06C

#define	D40_DREG_LCMIS0 0x080

#define	D40_DREG_LCMIS1 0x084

#define	D40_DREG_LCMIS2 0x088

#define	D40_DREG_LCMIS3 0x08C

#define	D40_DREG_LCICR0 0x090

#define	D40_DREG_LCICR1 0x094

#define	D40_DREG_LCICR2 0x098

#define	D40_DREG_LCICR3 0x09C

#define	D40_DREG_LCTIS0 0x0A0

#define	D40_DREG_LCTIS1 0x0A4

#define	D40_DREG_LCTIS2 0x0A8

#define	D40_DREG_LCTIS3 0x0AC

#define	D40_DREG_LCEIS0 0x0B0

#define	D40_DREG_LCEIS1 0x0B4

#define	D40_DREG_LCEIS2 0x0B8

#define	D40_DREG_LCEIS3 0x0BC

#define	D40_DREG_PSEG1 0x110

#define	D40_DREG_PSEG2 0x114

#define	D40_DREG_PSEG3 0x118

#define	D40_DREG_PSEG4 0x11C

#define	D40_DREG_PCEG1 0x120

#define	D40_DREG_PCEG2 0x124

#define	D40_DREG_PCEG3 0x128

#define	D40_DREG_PCEG4 0x12C

#define	D40_DREG_RSEG1 0x130

#define	D40_DREG_RSEG2 0x134

#define	D40_DREG_RSEG3 0x138

#define	D40_DREG_RSEG4 0x13C

#define	D40_DREG_RCEG1 0x140

#define	D40_DREG_RCEG2 0x144

#define	D40_DREG_RCEG3 0x148

#define	D40_DREG_RCEG4 0x14C

#define	D40_DREG_STFU 0xFC8

#define	D40_DREG_ICFG 0xFCC

#define	D40_DREG_PERIPHID0 0xFE0

#define	D40_DREG_PERIPHID1 0xFE4

#define	D40_DREG_PERIPHID2 0xFE8

#define	D40_DREG_PERIPHID3 0xFEC

#define	D40_DREG_CELLID0 0xFF0

#define	D40_DREG_CELLID1 0xFF4

#define	D40_DREG_CELLID2 0xFF8

#define	D40_DREG_CELLID3 0xFFC

Enumerations
enum	d40_lli_flags { LLI_ADDR_INC = 1 << 0, LLI_TERM_INT = 1 << 1, LLI_CYCLIC = 1 << 2, LLI_LAST_LINK = 1 << 3 }

Functions
void	d40_phy_cfg (struct stedma40_chan_cfg cfg, u32 src_cfg, u32 *dst_cfg, bool is_log)

void	d40_log_cfg (struct stedma40_chan_cfg cfg, u32 lcsp1, u32 *lcsp2)

int	d40_phy_sg_to_lli (struct scatterlist sg, int sg_len, dma_addr_t target, struct d40_phy_lli lli, dma_addr_t lli_phys, u32 reg_cfg, struct stedma40_half_channel_info info, struct stedma40_half_channel_info otherinfo, unsigned long flags)

int	d40_log_sg_to_lli (struct scatterlist sg, int sg_len, dma_addr_t dev_addr, struct d40_log_lli lli_sg, u32 lcsp13, u32 data_width1, u32 data_width2)

void	d40_log_lli_lcpa_write (struct d40_log_lli_full lcpa, struct d40_log_lli lli_dst, struct d40_log_lli *lli_src, int next, unsigned int flags)

void	d40_log_lli_lcla_write (struct d40_log_lli lcla, struct d40_log_lli lli_dst, struct d40_log_lli *lli_src, int next, unsigned int flags)

Macro Definition Documentation

#define D40_CHAN_REG_SDCFG 0x10

Definition at line 119 of file ste_dma40_ll.h.

#define D40_CHAN_REG_SDELT 0x14

Definition at line 120 of file ste_dma40_ll.h.

#define D40_CHAN_REG_SDLNK 0x1C

Definition at line 122 of file ste_dma40_ll.h.

#define D40_CHAN_REG_SDPTR 0x18

Definition at line 121 of file ste_dma40_ll.h.

#define D40_CHAN_REG_SSCFG 0x00

Definition at line 115 of file ste_dma40_ll.h.

#define D40_CHAN_REG_SSELT 0x04

Definition at line 116 of file ste_dma40_ll.h.

#define D40_CHAN_REG_SSLNK 0x0C

Definition at line 118 of file ste_dma40_ll.h.

#define D40_CHAN_REG_SSPTR 0x08

Definition at line 117 of file ste_dma40_ll.h.

#define D40_DREG_ACTIVE 0x050

Definition at line 151 of file ste_dma40_ll.h.

#define D40_DREG_ACTIVO 0x054

Definition at line 152 of file ste_dma40_ll.h.

#define D40_DREG_CELLID0 0xFF0

Definition at line 197 of file ste_dma40_ll.h.

#define D40_DREG_CELLID1 0xFF4

Definition at line 198 of file ste_dma40_ll.h.

#define D40_DREG_CELLID2 0xFF8

Definition at line 199 of file ste_dma40_ll.h.

#define D40_DREG_CELLID3 0xFFC

Definition at line 200 of file ste_dma40_ll.h.

#define D40_DREG_FSEB1 0x058

Definition at line 153 of file ste_dma40_ll.h.

#define D40_DREG_FSEB2 0x05C

Definition at line 154 of file ste_dma40_ll.h.

#define D40_DREG_GCC 0x000

Definition at line 125 of file ste_dma40_ll.h.

#define D40_DREG_GCC_DST 1

Definition at line 131 of file ste_dma40_ll.h.

#define D40_DREG_GCC_ENA 0x1

Definition at line 126 of file ste_dma40_ll.h.

#define D40_DREG_GCC_ENABLE_ALL 0xff01

Definition at line 128 of file ste_dma40_ll.h.

#define D40_DREG_GCC_EVTGRP_ENA	(	x,
		y
	)	(1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))

Definition at line 132 of file ste_dma40_ll.h.

#define D40_DREG_GCC_EVTGRP_POS 8

Definition at line 129 of file ste_dma40_ll.h.

#define D40_DREG_GCC_SRC 0

Definition at line 130 of file ste_dma40_ll.h.

#define D40_DREG_ICFG 0xFCC

Definition at line 192 of file ste_dma40_ll.h.

#define D40_DREG_LCEIS0 0x0B0

Definition at line 171 of file ste_dma40_ll.h.

#define D40_DREG_LCEIS1 0x0B4

Definition at line 172 of file ste_dma40_ll.h.

#define D40_DREG_LCEIS2 0x0B8

Definition at line 173 of file ste_dma40_ll.h.

#define D40_DREG_LCEIS3 0x0BC

Definition at line 174 of file ste_dma40_ll.h.

#define D40_DREG_LCICR0 0x090

Definition at line 163 of file ste_dma40_ll.h.

#define D40_DREG_LCICR1 0x094

Definition at line 164 of file ste_dma40_ll.h.

#define D40_DREG_LCICR2 0x098

Definition at line 165 of file ste_dma40_ll.h.

#define D40_DREG_LCICR3 0x09C

Definition at line 166 of file ste_dma40_ll.h.

#define D40_DREG_LCLA 0x024

Definition at line 150 of file ste_dma40_ll.h.

#define D40_DREG_LCMIS0 0x080

Definition at line 159 of file ste_dma40_ll.h.

#define D40_DREG_LCMIS1 0x084

Definition at line 160 of file ste_dma40_ll.h.

#define D40_DREG_LCMIS2 0x088

Definition at line 161 of file ste_dma40_ll.h.

#define D40_DREG_LCMIS3 0x08C

Definition at line 162 of file ste_dma40_ll.h.

#define D40_DREG_LCPA 0x020

Definition at line 149 of file ste_dma40_ll.h.

#define D40_DREG_LCTIS0 0x0A0

Definition at line 167 of file ste_dma40_ll.h.

#define D40_DREG_LCTIS1 0x0A4

Definition at line 168 of file ste_dma40_ll.h.

#define D40_DREG_LCTIS2 0x0A8

Definition at line 169 of file ste_dma40_ll.h.

#define D40_DREG_LCTIS3 0x0AC

Definition at line 170 of file ste_dma40_ll.h.

#define D40_DREG_PCBASE 0x400

Definition at line 10 of file ste_dma40_ll.h.

#define D40_DREG_PCDELTA (8 * 4)

Definition at line 11 of file ste_dma40_ll.h.

#define D40_DREG_PCEG1 0x120

Definition at line 179 of file ste_dma40_ll.h.

#define D40_DREG_PCEG2 0x124

Definition at line 180 of file ste_dma40_ll.h.

#define D40_DREG_PCEG3 0x128

Definition at line 181 of file ste_dma40_ll.h.

#define D40_DREG_PCEG4 0x12C

Definition at line 182 of file ste_dma40_ll.h.

#define D40_DREG_PCEIS 0x06C

Definition at line 158 of file ste_dma40_ll.h.

#define D40_DREG_PCICR 0x064

Definition at line 156 of file ste_dma40_ll.h.

#define D40_DREG_PCMIS 0x060

Definition at line 155 of file ste_dma40_ll.h.

#define D40_DREG_PCTIS 0x068

Definition at line 157 of file ste_dma40_ll.h.

#define D40_DREG_PERIPHID0 0xFE0

Definition at line 193 of file ste_dma40_ll.h.

#define D40_DREG_PERIPHID1 0xFE4

Definition at line 194 of file ste_dma40_ll.h.

#define D40_DREG_PERIPHID2 0xFE8

Definition at line 195 of file ste_dma40_ll.h.

#define D40_DREG_PERIPHID3 0xFEC

Definition at line 196 of file ste_dma40_ll.h.

#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3

Definition at line 147 of file ste_dma40_ll.h.

#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2

Definition at line 146 of file ste_dma40_ll.h.

#define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1

Definition at line 145 of file ste_dma40_ll.h.

#define D40_DREG_PRMO_PCHAN_BASIC 0x1

Definition at line 142 of file ste_dma40_ll.h.

#define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3

Definition at line 144 of file ste_dma40_ll.h.

#define D40_DREG_PRMO_PCHAN_MODULO 0x2

Definition at line 143 of file ste_dma40_ll.h.

#define D40_DREG_PRMOE 0x018

Definition at line 140 of file ste_dma40_ll.h.

#define D40_DREG_PRMOO 0x01C

Definition at line 141 of file ste_dma40_ll.h.

#define D40_DREG_PRMSE 0x010

Definition at line 138 of file ste_dma40_ll.h.

#define D40_DREG_PRMSO 0x014

Definition at line 139 of file ste_dma40_ll.h.

#define D40_DREG_PRSME 0x008

Definition at line 136 of file ste_dma40_ll.h.

#define D40_DREG_PRSMO 0x00C

Definition at line 137 of file ste_dma40_ll.h.

#define D40_DREG_PRTYP 0x004

Definition at line 135 of file ste_dma40_ll.h.

#define D40_DREG_PSEG1 0x110

Definition at line 175 of file ste_dma40_ll.h.

#define D40_DREG_PSEG2 0x114

Definition at line 176 of file ste_dma40_ll.h.

#define D40_DREG_PSEG3 0x118

Definition at line 177 of file ste_dma40_ll.h.

#define D40_DREG_PSEG4 0x11C

Definition at line 178 of file ste_dma40_ll.h.

#define D40_DREG_RCEG1 0x140

Definition at line 187 of file ste_dma40_ll.h.

#define D40_DREG_RCEG2 0x144

Definition at line 188 of file ste_dma40_ll.h.

#define D40_DREG_RCEG3 0x148

Definition at line 189 of file ste_dma40_ll.h.

#define D40_DREG_RCEG4 0x14C

Definition at line 190 of file ste_dma40_ll.h.

#define D40_DREG_RSEG1 0x130

Definition at line 183 of file ste_dma40_ll.h.

#define D40_DREG_RSEG2 0x134

Definition at line 184 of file ste_dma40_ll.h.

#define D40_DREG_RSEG3 0x138

Definition at line 185 of file ste_dma40_ll.h.

#define D40_DREG_RSEG4 0x13C

Definition at line 186 of file ste_dma40_ll.h.

#define D40_DREG_STFU 0xFC8

Definition at line 191 of file ste_dma40_ll.h.

#define D40_EVENTLINE_MASK ( i ) (0x3 << D40_EVENTLINE_POS(i))

Definition at line 66 of file ste_dma40_ll.h.

#define D40_EVENTLINE_POS ( i ) (2 * i)

Definition at line 65 of file ste_dma40_ll.h.

#define D40_GROUP_SIZE 8

Definition at line 19 of file ste_dma40_ll.h.

#define D40_LCPA_CHAN_DST_DELTA 16

Definition at line 15 of file ste_dma40_ll.h.

#define D40_LCPA_CHAN_SIZE 32

Definition at line 14 of file ste_dma40_ll.h.

#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */

Definition at line 12 of file ste_dma40_ll.h.

#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)

Definition at line 74 of file ste_dma40_ll.h.

#define D40_MEM_LCSP0_ECNT_POS 16

Definition at line 71 of file ste_dma40_ll.h.

#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)

Definition at line 75 of file ste_dma40_ll.h.

#define D40_MEM_LCSP0_SPTR_POS 0

Definition at line 72 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_EIM_POS 13

Definition at line 81 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_ESIZE_POS 8

Definition at line 84 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)

Definition at line 90 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_INCR_POS 12

Definition at line 82 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_MST_POS 15

Definition at line 79 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)

Definition at line 91 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_PSIZE_POS 10

Definition at line 83 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)

Definition at line 89 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SCFG_TIM_POS 14

Definition at line 80 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)

Definition at line 92 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SLOS_POS 1

Definition at line 85 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)

Definition at line 88 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_SPTR_POS 16

Definition at line 78 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)

Definition at line 93 of file ste_dma40_ll.h.

#define D40_MEM_LCSP1_STCP_POS 0

Definition at line 86 of file ste_dma40_ll.h.

#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)

Definition at line 98 of file ste_dma40_ll.h.

#define D40_MEM_LCSP2_ECNT_POS 16

Definition at line 96 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DCFG_EIM_POS 13

Definition at line 103 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8

Definition at line 106 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DCFG_INCR_POS 12

Definition at line 104 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DCFG_MST_POS 15

Definition at line 101 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10

Definition at line 105 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DCFG_TIM_POS 14

Definition at line 102 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)

Definition at line 110 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DLOS_POS 1

Definition at line 107 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)

Definition at line 111 of file ste_dma40_ll.h.

#define D40_MEM_LCSP3_DTCP_POS 0

Definition at line 108 of file ste_dma40_ll.h.

#define D40_PHYS_TO_GROUP ( phys ) ((phys & (D40_GROUP_SIZE - 1)) / 2)

Definition at line 20 of file ste_dma40_ll.h.

#define D40_SREG_CFG_EIM_POS 13

Definition at line 25 of file ste_dma40_ll.h.

#define D40_SREG_CFG_ESIZE_POS 8

Definition at line 29 of file ste_dma40_ll.h.

#define D40_SREG_CFG_LBE_POS 6

Definition at line 31 of file ste_dma40_ll.h.

#define D40_SREG_CFG_LOG_GIM_POS 5

Definition at line 32 of file ste_dma40_ll.h.

#define D40_SREG_CFG_LOG_INCR_POS 12

Definition at line 26 of file ste_dma40_ll.h.

#define D40_SREG_CFG_LOG_MFU_POS 4

Definition at line 33 of file ste_dma40_ll.h.

#define D40_SREG_CFG_MST_POS 15

Definition at line 23 of file ste_dma40_ll.h.

#define D40_SREG_CFG_PHY_EVTL_POS 0

Definition at line 35 of file ste_dma40_ll.h.

#define D40_SREG_CFG_PHY_PEN_POS 12

Definition at line 27 of file ste_dma40_ll.h.

#define D40_SREG_CFG_PHY_TM_POS 4

Definition at line 34 of file ste_dma40_ll.h.

#define D40_SREG_CFG_PRI_POS 7

Definition at line 30 of file ste_dma40_ll.h.

#define D40_SREG_CFG_PSIZE_POS 10

Definition at line 28 of file ste_dma40_ll.h.

#define D40_SREG_CFG_TIM_POS 14

Definition at line 24 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_LOG_ECNT_POS 16

Definition at line 57 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)

Definition at line 62 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_LOG_LIDX_POS 8

Definition at line 58 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_LOG_LOS_POS 1

Definition at line 59 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_LOG_TCP_POS 0

Definition at line 60 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)

Definition at line 42 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_PHY_ECNT_POS 16

Definition at line 39 of file ste_dma40_ll.h.

#define D40_SREG_ELEM_PHY_EIDX_POS 0

Definition at line 40 of file ste_dma40_ll.h.

#define D40_SREG_LNK_PHY_LMP_POS 1

Definition at line 46 of file ste_dma40_ll.h.

#define D40_SREG_LNK_PHY_PRE_POS 2

Definition at line 47 of file ste_dma40_ll.h.

#define D40_SREG_LNK_PHY_TCP_POS 0

Definition at line 45 of file ste_dma40_ll.h.

#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL

Definition at line 52 of file ste_dma40_ll.h.

#define D40_TYPE_TO_EVENT ( type ) (type % 16)

Definition at line 18 of file ste_dma40_ll.h.

#define D40_TYPE_TO_GROUP ( type ) (type / 16)

Definition at line 17 of file ste_dma40_ll.h.

Enumeration Type Documentation

enum d40_lli_flags

Enumerator:

LLI_ADDR_INC
LLI_TERM_INT
LLI_CYCLIC
LLI_LAST_LINK

Definition at line 302 of file ste_dma40_ll.h.

Function Documentation

void d40_log_cfg	(	struct stedma40_chan_cfg *	cfg,
		u32 *	lcsp1,
		u32 *	lcsp2
	)

Definition at line 14 of file ste_dma40_ll.c.

void d40_log_lli_lcla_write	(	struct d40_log_lli *	lcla,
		struct d40_log_lli *	lli_dst,
		struct d40_log_lli *	lli_src,
		int	next,
		unsigned int	flags
	)

Definition at line 340 of file ste_dma40_ll.c.

void d40_log_lli_lcpa_write	(	struct d40_log_lli_full *	lcpa,
		struct d40_log_lli *	lli_dst,
		struct d40_log_lli *	lli_src,
		int	next,
		unsigned int	flags
	)

Definition at line 327 of file ste_dma40_ll.c.

int d40_log_sg_to_lli	(	struct scatterlist *	sg,
		int	sg_len,
		dma_addr_t	dev_addr,
		struct d40_log_lli *	lli_sg,
		u32	lcsp13,
		u32	data_width1,
		u32	data_width2
	)

Definition at line 409 of file ste_dma40_ll.c.

void d40_phy_cfg	(	struct stedma40_chan_cfg *	cfg,
		u32 *	src_cfg,
		u32 *	dst_cfg,
		bool	is_log
	)

Definition at line 54 of file ste_dma40_ll.c.

int d40_phy_sg_to_lli	(	struct scatterlist *	sg,
		int	sg_len,
		dma_addr_t	target,
		struct d40_phy_lli *	lli,
		dma_addr_t	lli_phys,
		u32	reg_cfg,
		struct stedma40_half_channel_info *	info,
		struct stedma40_half_channel_info *	otherinfo,
		unsigned long	flags
	)

Definition at line 257 of file ste_dma40_ll.c.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation