Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
stv0900_sw.c
Go to the documentation of this file.
1 /*
2  * stv0900_sw.c
3  *
4  * Driver for ST STV0900 satellite demodulator IC.
5  *
6  * Copyright (C) ST Microelectronics.
7  * Copyright (C) 2009 NetUP Inc.
8  * Copyright (C) 2009 Igor M. Liplianin <[email protected]>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  *
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24  */
25 
26 #include "stv0900.h"
27 #include "stv0900_reg.h"
28 #include "stv0900_priv.h"
29 
30 s32 shiftx(s32 x, int demod, s32 shift)
31 {
32  if (demod == 1)
33  return x - shift;
34 
35  return x;
36 }
37 
38 int stv0900_check_signal_presence(struct stv0900_internal *intp,
39  enum fe_stv0900_demod_num demod)
40 {
41  s32 carr_offset,
42  agc2_integr,
43  max_carrier;
44 
45  int no_signal = FALSE;
46 
47  carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
48  | stv0900_read_reg(intp, CFR1);
49  carr_offset = ge2comp(carr_offset, 16);
50  agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
51  | stv0900_read_reg(intp, AGC2I0);
52  max_carrier = intp->srch_range[demod] / 1000;
53 
54  max_carrier += (max_carrier / 10);
55  max_carrier = 65536 * (max_carrier / 2);
56  max_carrier /= intp->mclk / 1000;
57  if (max_carrier > 0x4000)
58  max_carrier = 0x4000;
59 
60  if ((agc2_integr > 0x2000)
61  || (carr_offset > (2 * max_carrier))
62  || (carr_offset < (-2 * max_carrier)))
63  no_signal = TRUE;
64 
65  return no_signal;
66 }
67 
68 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
69  s32 *frequency_inc, s32 *sw_timeout,
70  s32 *steps,
71  enum fe_stv0900_demod_num demod)
72 {
73  s32 timeout, freq_inc, max_steps, srate, max_carrier;
74 
75  enum fe_stv0900_search_standard standard;
76 
77  srate = intp->symbol_rate[demod];
78  max_carrier = intp->srch_range[demod] / 1000;
79  max_carrier += max_carrier / 10;
80  standard = intp->srch_standard[demod];
81 
82  max_carrier = 65536 * (max_carrier / 2);
83  max_carrier /= intp->mclk / 1000;
84 
85  if (max_carrier > 0x4000)
86  max_carrier = 0x4000;
87 
88  freq_inc = srate;
89  freq_inc /= intp->mclk >> 10;
90  freq_inc = freq_inc << 6;
91 
92  switch (standard) {
93  case STV0900_SEARCH_DVBS1:
94  case STV0900_SEARCH_DSS:
95  freq_inc *= 3;
96  timeout = 20;
97  break;
98  case STV0900_SEARCH_DVBS2:
99  freq_inc *= 4;
100  timeout = 25;
101  break;
102  case STV0900_AUTO_SEARCH:
103  default:
104  freq_inc *= 3;
105  timeout = 25;
106  break;
107  }
108 
109  freq_inc /= 100;
110 
111  if ((freq_inc > max_carrier) || (freq_inc < 0))
112  freq_inc = max_carrier / 2;
113 
114  timeout *= 27500;
115 
116  if (srate > 0)
117  timeout /= srate / 1000;
118 
119  if ((timeout > 100) || (timeout < 0))
120  timeout = 100;
121 
122  max_steps = (max_carrier / freq_inc) + 1;
123 
124  if ((max_steps > 100) || (max_steps < 0)) {
125  max_steps = 100;
126  freq_inc = max_carrier / max_steps;
127  }
128 
129  *frequency_inc = freq_inc;
130  *sw_timeout = timeout;
131  *steps = max_steps;
132 
133 }
134 
135 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
136  s32 FreqIncr, s32 Timeout, int zigzag,
137  s32 MaxStep, enum fe_stv0900_demod_num demod)
138 {
139  int no_signal,
140  lock = FALSE;
141  s32 stepCpt,
142  freqOffset,
143  max_carrier;
144 
145  max_carrier = intp->srch_range[demod] / 1000;
146  max_carrier += (max_carrier / 10);
147 
148  max_carrier = 65536 * (max_carrier / 2);
149  max_carrier /= intp->mclk / 1000;
150 
151  if (max_carrier > 0x4000)
152  max_carrier = 0x4000;
153 
154  if (zigzag == TRUE)
155  freqOffset = 0;
156  else
157  freqOffset = -max_carrier + FreqIncr;
158 
159  stepCpt = 0;
160 
161  do {
162  stv0900_write_reg(intp, DMDISTATE, 0x1c);
163  stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
164  stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
165  stv0900_write_reg(intp, DMDISTATE, 0x18);
166  stv0900_write_bits(intp, ALGOSWRST, 1);
167 
168  if (intp->chip_id == 0x12) {
169  stv0900_write_bits(intp, RST_HWARE, 1);
170  stv0900_write_bits(intp, RST_HWARE, 0);
171  }
172 
173  if (zigzag == TRUE) {
174  if (freqOffset >= 0)
175  freqOffset = -freqOffset - 2 * FreqIncr;
176  else
177  freqOffset = -freqOffset;
178  } else
179  freqOffset += + 2 * FreqIncr;
180 
181  stepCpt++;
182  lock = stv0900_get_demod_lock(intp, demod, Timeout);
183  no_signal = stv0900_check_signal_presence(intp, demod);
184 
185  } while ((lock == FALSE)
186  && (no_signal == FALSE)
187  && ((freqOffset - FreqIncr) < max_carrier)
188  && ((freqOffset + FreqIncr) > -max_carrier)
189  && (stepCpt < MaxStep));
190 
191  stv0900_write_bits(intp, ALGOSWRST, 0);
192 
193  return lock;
194 }
195 
196 static int stv0900_sw_algo(struct stv0900_internal *intp,
197  enum fe_stv0900_demod_num demod)
198 {
199  int lock = FALSE,
200  no_signal,
201  zigzag;
202  s32 s2fw,
203  fqc_inc,
204  sft_stp_tout,
205  trial_cntr,
206  max_steps;
207 
208  stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
209  &max_steps, demod);
210  switch (intp->srch_standard[demod]) {
211  case STV0900_SEARCH_DVBS1:
212  case STV0900_SEARCH_DSS:
213  if (intp->chip_id >= 0x20)
214  stv0900_write_reg(intp, CARFREQ, 0x3b);
215  else
216  stv0900_write_reg(intp, CARFREQ, 0xef);
217 
218  stv0900_write_reg(intp, DMDCFGMD, 0x49);
219  zigzag = FALSE;
220  break;
221  case STV0900_SEARCH_DVBS2:
222  if (intp->chip_id >= 0x20)
223  stv0900_write_reg(intp, CORRELABS, 0x79);
224  else
225  stv0900_write_reg(intp, CORRELABS, 0x68);
226 
227  stv0900_write_reg(intp, DMDCFGMD, 0x89);
228 
229  zigzag = TRUE;
230  break;
231  case STV0900_AUTO_SEARCH:
232  default:
233  if (intp->chip_id >= 0x20) {
234  stv0900_write_reg(intp, CARFREQ, 0x3b);
235  stv0900_write_reg(intp, CORRELABS, 0x79);
236  } else {
237  stv0900_write_reg(intp, CARFREQ, 0xef);
238  stv0900_write_reg(intp, CORRELABS, 0x68);
239  }
240 
241  stv0900_write_reg(intp, DMDCFGMD, 0xc9);
242  zigzag = FALSE;
243  break;
244  }
245 
246  trial_cntr = 0;
247  do {
248  lock = stv0900_search_carr_sw_loop(intp,
249  fqc_inc,
250  sft_stp_tout,
251  zigzag,
252  max_steps,
253  demod);
254  no_signal = stv0900_check_signal_presence(intp, demod);
255  trial_cntr++;
256  if ((lock == TRUE)
257  || (no_signal == TRUE)
258  || (trial_cntr == 2)) {
259 
260  if (intp->chip_id >= 0x20) {
261  stv0900_write_reg(intp, CARFREQ, 0x49);
262  stv0900_write_reg(intp, CORRELABS, 0x9e);
263  } else {
264  stv0900_write_reg(intp, CARFREQ, 0xed);
265  stv0900_write_reg(intp, CORRELABS, 0x88);
266  }
267 
268  if ((stv0900_get_bits(intp, HEADER_MODE) ==
269  STV0900_DVBS2_FOUND) &&
270  (lock == TRUE)) {
271  msleep(sft_stp_tout);
272  s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
273 
274  if (s2fw < 0xd) {
275  msleep(sft_stp_tout);
276  s2fw = stv0900_get_bits(intp,
277  FLYWHEEL_CPT);
278  }
279 
280  if (s2fw < 0xd) {
281  lock = FALSE;
282 
283  if (trial_cntr < 2) {
284  if (intp->chip_id >= 0x20)
285  stv0900_write_reg(intp,
286  CORRELABS,
287  0x79);
288  else
289  stv0900_write_reg(intp,
290  CORRELABS,
291  0x68);
292 
293  stv0900_write_reg(intp,
294  DMDCFGMD,
295  0x89);
296  }
297  }
298  }
299  }
300 
301  } while ((lock == FALSE)
302  && (trial_cntr < 2)
303  && (no_signal == FALSE));
304 
305  return lock;
306 }
307 
308 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
309  u32 mclk,
310  enum fe_stv0900_demod_num demod)
311 {
312  s32 rem1, rem2, intval1, intval2, srate;
313 
314  srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
315  (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
316  (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
317  (stv0900_get_bits(intp, SYMB_FREQ0));
318  dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
319  srate, stv0900_get_bits(intp, SYMB_FREQ0),
320  stv0900_get_bits(intp, SYMB_FREQ1),
321  stv0900_get_bits(intp, SYMB_FREQ2),
322  stv0900_get_bits(intp, SYMB_FREQ3));
323 
324  intval1 = (mclk) >> 16;
325  intval2 = (srate) >> 16;
326 
327  rem1 = (mclk) % 0x10000;
328  rem2 = (srate) % 0x10000;
329  srate = (intval1 * intval2) +
330  ((intval1 * rem2) >> 16) +
331  ((intval2 * rem1) >> 16);
332 
333  return srate;
334 }
335 
336 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
337  u32 mclk, u32 srate,
338  enum fe_stv0900_demod_num demod)
339 {
340  u32 symb;
341 
342  dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
343  srate, demod);
344 
345  if (srate > 60000000) {
346  symb = srate << 4;
347  symb /= (mclk >> 12);
348  } else if (srate > 6000000) {
349  symb = srate << 6;
350  symb /= (mclk >> 10);
351  } else {
352  symb = srate << 9;
353  symb /= (mclk >> 7);
354  }
355 
356  stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
357  stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
358 }
359 
360 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
361  u32 mclk, u32 srate,
362  enum fe_stv0900_demod_num demod)
363 {
364  u32 symb;
365 
366  srate = 105 * (srate / 100);
367 
368  if (srate > 60000000) {
369  symb = srate << 4;
370  symb /= (mclk >> 12);
371  } else if (srate > 6000000) {
372  symb = srate << 6;
373  symb /= (mclk >> 10);
374  } else {
375  symb = srate << 9;
376  symb /= (mclk >> 7);
377  }
378 
379  if (symb < 0x7fff) {
380  stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
381  stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
382  } else {
383  stv0900_write_reg(intp, SFRUP1, 0x7f);
384  stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
385  }
386 }
387 
388 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
389  u32 mclk, u32 srate,
390  enum fe_stv0900_demod_num demod)
391 {
392  u32 symb;
393 
394  srate = 95 * (srate / 100);
395  if (srate > 60000000) {
396  symb = srate << 4;
397  symb /= (mclk >> 12);
398 
399  } else if (srate > 6000000) {
400  symb = srate << 6;
401  symb /= (mclk >> 10);
402 
403  } else {
404  symb = srate << 9;
405  symb /= (mclk >> 7);
406  }
407 
408  stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
409  stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
410 }
411 
412 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
413  u32 srate,
414  enum fe_stv0900_demod_num demod)
415 {
416  s32 timingoffset;
417 
418 
419  timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
420  (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
421  (stv0900_read_reg(intp, TMGREG2 + 2));
422 
423  timingoffset = ge2comp(timingoffset, 24);
424 
425 
426  if (timingoffset == 0)
427  timingoffset = 1;
428 
429  timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
430  timingoffset /= 320;
431 
432  return timingoffset;
433 }
434 
435 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
436  enum fe_stv0900_demod_num demod)
437 {
438  s32 rolloff;
439 
440  if (intp->chip_id == 0x10) {
441  stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
442  rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
443  stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
444  } else if (intp->chip_id <= 0x20)
445  stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
446  else /* cut 3.0 */
447  stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
448 }
449 
450 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
451 {
452  u32 rolloff;
453 
454  switch (ro) {
455  case STV0900_20:
456  rolloff = 20;
457  break;
458  case STV0900_25:
459  rolloff = 25;
460  break;
461  case STV0900_35:
462  default:
463  rolloff = 35;
464  break;
465  }
466 
467  return srate + (srate * rolloff) / 100;
468 }
469 
470 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
471  enum fe_stv0900_demod_num demod)
472 {
473  int timingLock = FALSE;
474  s32 i,
475  timingcpt = 0;
476  u8 car_freq,
477  tmg_th_high,
478  tmg_th_low;
479 
480  car_freq = stv0900_read_reg(intp, CARFREQ);
481  tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
482  tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
483  stv0900_write_reg(intp, TMGTHRISE, 0x20);
484  stv0900_write_reg(intp, TMGTHFALL, 0x0);
485  stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
486  stv0900_write_reg(intp, RTC, 0x80);
487  stv0900_write_reg(intp, RTCS2, 0x40);
488  stv0900_write_reg(intp, CARFREQ, 0x0);
489  stv0900_write_reg(intp, CFRINIT1, 0x0);
490  stv0900_write_reg(intp, CFRINIT0, 0x0);
491  stv0900_write_reg(intp, AGC2REF, 0x65);
492  stv0900_write_reg(intp, DMDISTATE, 0x18);
493  msleep(7);
494 
495  for (i = 0; i < 10; i++) {
496  if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
497  timingcpt++;
498 
499  msleep(1);
500  }
501 
502  if (timingcpt >= 3)
503  timingLock = TRUE;
504 
505  stv0900_write_reg(intp, AGC2REF, 0x38);
506  stv0900_write_reg(intp, RTC, 0x88);
507  stv0900_write_reg(intp, RTCS2, 0x68);
508  stv0900_write_reg(intp, CARFREQ, car_freq);
509  stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
510  stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
511 
512  return timingLock;
513 }
514 
515 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
516  s32 demod_timeout)
517 {
518  struct stv0900_state *state = fe->demodulator_priv;
519  struct stv0900_internal *intp = state->internal;
520  enum fe_stv0900_demod_num demod = state->demod;
521  int lock = FALSE,
522  d = demod;
523  s32 srate,
524  search_range,
525  locktimeout,
526  currier_step,
527  nb_steps,
528  current_step,
529  direction,
530  tuner_freq,
531  timeout,
532  freq;
533 
534  srate = intp->symbol_rate[d];
535  search_range = intp->srch_range[d];
536 
537  if (srate >= 10000000)
538  locktimeout = demod_timeout / 3;
539  else
540  locktimeout = demod_timeout / 2;
541 
542  lock = stv0900_get_demod_lock(intp, d, locktimeout);
543 
544  if (lock != FALSE)
545  return lock;
546 
547  if (srate >= 10000000) {
548  if (stv0900_check_timing_lock(intp, d) == TRUE) {
549  stv0900_write_reg(intp, DMDISTATE, 0x1f);
550  stv0900_write_reg(intp, DMDISTATE, 0x15);
551  lock = stv0900_get_demod_lock(intp, d, demod_timeout);
552  } else
553  lock = FALSE;
554 
555  return lock;
556  }
557 
558  if (intp->chip_id <= 0x20) {
559  if (srate <= 1000000)
560  currier_step = 500;
561  else if (srate <= 4000000)
562  currier_step = 1000;
563  else if (srate <= 7000000)
564  currier_step = 2000;
565  else if (srate <= 10000000)
566  currier_step = 3000;
567  else
568  currier_step = 5000;
569 
570  if (srate >= 2000000) {
571  timeout = (demod_timeout / 3);
572  if (timeout > 1000)
573  timeout = 1000;
574  } else
575  timeout = (demod_timeout / 2);
576  } else {
577  /*cut 3.0 */
578  currier_step = srate / 4000;
579  timeout = (demod_timeout * 3) / 4;
580  }
581 
582  nb_steps = ((search_range / 1000) / currier_step);
583 
584  if ((nb_steps % 2) != 0)
585  nb_steps += 1;
586 
587  if (nb_steps <= 0)
588  nb_steps = 2;
589  else if (nb_steps > 12)
590  nb_steps = 12;
591 
592  current_step = 1;
593  direction = 1;
594 
595  if (intp->chip_id <= 0x20) {
596  tuner_freq = intp->freq[d];
597  intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
598  intp->rolloff) + intp->symbol_rate[d];
599  } else
600  tuner_freq = 0;
601 
602  while ((current_step <= nb_steps) && (lock == FALSE)) {
603  if (direction > 0)
604  tuner_freq += (current_step * currier_step);
605  else
606  tuner_freq -= (current_step * currier_step);
607 
608  if (intp->chip_id <= 0x20) {
609  if (intp->tuner_type[d] == 3)
610  stv0900_set_tuner_auto(intp, tuner_freq,
611  intp->bw[d], demod);
612  else
613  stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
614 
615  stv0900_write_reg(intp, DMDISTATE, 0x1c);
616  stv0900_write_reg(intp, CFRINIT1, 0);
617  stv0900_write_reg(intp, CFRINIT0, 0);
618  stv0900_write_reg(intp, DMDISTATE, 0x1f);
619  stv0900_write_reg(intp, DMDISTATE, 0x15);
620  } else {
621  stv0900_write_reg(intp, DMDISTATE, 0x1c);
622  freq = (tuner_freq * 65536) / (intp->mclk / 1000);
623  stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
624  stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
625  stv0900_write_reg(intp, DMDISTATE, 0x1f);
626  stv0900_write_reg(intp, DMDISTATE, 0x05);
627  }
628 
629  lock = stv0900_get_demod_lock(intp, d, timeout);
630  direction *= -1;
631  current_step++;
632  }
633 
634  return lock;
635 }
636 
637 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
638  s32 srate,
639  enum fe_stv0900_search_algo algo)
640 {
641  switch (algo) {
642  case STV0900_BLIND_SEARCH:
643  if (srate <= 1500000) {
644  (*demod_timeout) = 1500;
645  (*fec_timeout) = 400;
646  } else if (srate <= 5000000) {
647  (*demod_timeout) = 1000;
648  (*fec_timeout) = 300;
649  } else {
650  (*demod_timeout) = 700;
651  (*fec_timeout) = 100;
652  }
653 
654  break;
655  case STV0900_COLD_START:
656  case STV0900_WARM_START:
657  default:
658  if (srate <= 1000000) {
659  (*demod_timeout) = 3000;
660  (*fec_timeout) = 1700;
661  } else if (srate <= 2000000) {
662  (*demod_timeout) = 2500;
663  (*fec_timeout) = 1100;
664  } else if (srate <= 5000000) {
665  (*demod_timeout) = 1000;
666  (*fec_timeout) = 550;
667  } else if (srate <= 10000000) {
668  (*demod_timeout) = 700;
669  (*fec_timeout) = 250;
670  } else if (srate <= 20000000) {
671  (*demod_timeout) = 400;
672  (*fec_timeout) = 130;
673  } else {
674  (*demod_timeout) = 300;
675  (*fec_timeout) = 100;
676  }
677 
678  break;
679 
680  }
681 
682  if (algo == STV0900_WARM_START)
683  (*demod_timeout) /= 2;
684 }
685 
686 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
687  enum fe_stv0900_demod_num demod)
688 {
689 
690  s32 vth_reg = VTH12;
691 
692  dprintk("%s\n", __func__);
693 
694  stv0900_write_reg(intp, vth_reg++, 0xd0);
695  stv0900_write_reg(intp, vth_reg++, 0x7d);
696  stv0900_write_reg(intp, vth_reg++, 0x53);
697  stv0900_write_reg(intp, vth_reg++, 0x2f);
698  stv0900_write_reg(intp, vth_reg++, 0x24);
699  stv0900_write_reg(intp, vth_reg++, 0x1f);
700 }
701 
702 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
703  enum fe_stv0900_search_standard standard,
704  enum fe_stv0900_fec fec,
705  enum fe_stv0900_demod_num demod)
706 {
707  dprintk("%s: ViterbiStandard = ", __func__);
708 
709  switch (standard) {
710  case STV0900_AUTO_SEARCH:
711  dprintk("Auto\n");
712  stv0900_write_reg(intp, FECM, 0x10);
713  stv0900_write_reg(intp, PRVIT, 0x3f);
714  break;
715  case STV0900_SEARCH_DVBS1:
716  dprintk("DVBS1\n");
717  stv0900_write_reg(intp, FECM, 0x00);
718  switch (fec) {
719  case STV0900_FEC_UNKNOWN:
720  default:
721  stv0900_write_reg(intp, PRVIT, 0x2f);
722  break;
723  case STV0900_FEC_1_2:
724  stv0900_write_reg(intp, PRVIT, 0x01);
725  break;
726  case STV0900_FEC_2_3:
727  stv0900_write_reg(intp, PRVIT, 0x02);
728  break;
729  case STV0900_FEC_3_4:
730  stv0900_write_reg(intp, PRVIT, 0x04);
731  break;
732  case STV0900_FEC_5_6:
733  stv0900_write_reg(intp, PRVIT, 0x08);
734  break;
735  case STV0900_FEC_7_8:
736  stv0900_write_reg(intp, PRVIT, 0x20);
737  break;
738  }
739 
740  break;
741  case STV0900_SEARCH_DSS:
742  dprintk("DSS\n");
743  stv0900_write_reg(intp, FECM, 0x80);
744  switch (fec) {
745  case STV0900_FEC_UNKNOWN:
746  default:
747  stv0900_write_reg(intp, PRVIT, 0x13);
748  break;
749  case STV0900_FEC_1_2:
750  stv0900_write_reg(intp, PRVIT, 0x01);
751  break;
752  case STV0900_FEC_2_3:
753  stv0900_write_reg(intp, PRVIT, 0x02);
754  break;
755  case STV0900_FEC_6_7:
756  stv0900_write_reg(intp, PRVIT, 0x10);
757  break;
758  }
759  break;
760  default:
761  break;
762  }
763 }
764 
765 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
766  enum fe_stv0900_demod_num demod)
767 {
768  enum fe_stv0900_fec prate;
769  s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
770 
771  switch (rate_fld) {
772  case 13:
773  prate = STV0900_FEC_1_2;
774  break;
775  case 18:
776  prate = STV0900_FEC_2_3;
777  break;
778  case 21:
779  prate = STV0900_FEC_3_4;
780  break;
781  case 24:
782  prate = STV0900_FEC_5_6;
783  break;
784  case 25:
785  prate = STV0900_FEC_6_7;
786  break;
787  case 26:
788  prate = STV0900_FEC_7_8;
789  break;
790  default:
791  prate = STV0900_FEC_UNKNOWN;
792  break;
793  }
794 
795  return prate;
796 }
797 
798 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
799  enum fe_stv0900_demod_num demod,
800  u32 srate)
801 {
802  if (intp->chip_id >= 0x30) {
803  if (srate >= 15000000) {
804  stv0900_write_reg(intp, ACLC, 0x2b);
805  stv0900_write_reg(intp, BCLC, 0x1a);
806  } else if ((srate >= 7000000) && (15000000 > srate)) {
807  stv0900_write_reg(intp, ACLC, 0x0c);
808  stv0900_write_reg(intp, BCLC, 0x1b);
809  } else if (srate < 7000000) {
810  stv0900_write_reg(intp, ACLC, 0x2c);
811  stv0900_write_reg(intp, BCLC, 0x1c);
812  }
813 
814  } else { /*cut 2.0 and 1.x*/
815  stv0900_write_reg(intp, ACLC, 0x1a);
816  stv0900_write_reg(intp, BCLC, 0x09);
817  }
818 
819 }
820 
821 static void stv0900_track_optimization(struct dvb_frontend *fe)
822 {
823  struct stv0900_state *state = fe->demodulator_priv;
824  struct stv0900_internal *intp = state->internal;
825  enum fe_stv0900_demod_num demod = state->demod;
826 
827  s32 srate,
828  pilots,
829  aclc,
830  freq1,
831  freq0,
832  i = 0,
833  timed,
834  timef,
835  blind_tun_sw = 0,
836  modulation;
837 
838  enum fe_stv0900_modcode foundModcod;
839 
840  dprintk("%s\n", __func__);
841 
842  srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
843  srate += stv0900_get_timing_offst(intp, srate, demod);
844 
845  switch (intp->result[demod].standard) {
846  case STV0900_DVBS1_STANDARD:
847  case STV0900_DSS_STANDARD:
848  dprintk("%s: found DVB-S or DSS\n", __func__);
849  if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
850  stv0900_write_bits(intp, DVBS1_ENABLE, 1);
851  stv0900_write_bits(intp, DVBS2_ENABLE, 0);
852  }
853 
854  stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
855  stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
856 
857  if (intp->chip_id < 0x30) {
858  stv0900_write_reg(intp, ERRCTRL1, 0x75);
859  break;
860  }
861 
862  if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
863  stv0900_write_reg(intp, GAUSSR0, 0x98);
864  stv0900_write_reg(intp, CCIR0, 0x18);
865  } else {
866  stv0900_write_reg(intp, GAUSSR0, 0x18);
867  stv0900_write_reg(intp, CCIR0, 0x18);
868  }
869 
870  stv0900_write_reg(intp, ERRCTRL1, 0x75);
871  break;
872  case STV0900_DVBS2_STANDARD:
873  dprintk("%s: found DVB-S2\n", __func__);
874  stv0900_write_bits(intp, DVBS1_ENABLE, 0);
875  stv0900_write_bits(intp, DVBS2_ENABLE, 1);
876  stv0900_write_reg(intp, ACLC, 0);
877  stv0900_write_reg(intp, BCLC, 0);
878  if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
879  foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
880  pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
881  aclc = stv0900_get_optim_carr_loop(srate,
882  foundModcod,
883  pilots,
884  intp->chip_id);
885  if (foundModcod <= STV0900_QPSK_910)
886  stv0900_write_reg(intp, ACLC2S2Q, aclc);
887  else if (foundModcod <= STV0900_8PSK_910) {
888  stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
889  stv0900_write_reg(intp, ACLC2S28, aclc);
890  }
891 
892  if ((intp->demod_mode == STV0900_SINGLE) &&
893  (foundModcod > STV0900_8PSK_910)) {
894  if (foundModcod <= STV0900_16APSK_910) {
895  stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
896  stv0900_write_reg(intp, ACLC2S216A,
897  aclc);
898  } else if (foundModcod <= STV0900_32APSK_910) {
899  stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
900  stv0900_write_reg(intp, ACLC2S232A,
901  aclc);
902  }
903  }
904 
905  } else {
906  modulation = intp->result[demod].modulation;
907  aclc = stv0900_get_optim_short_carr_loop(srate,
908  modulation, intp->chip_id);
909  if (modulation == STV0900_QPSK)
910  stv0900_write_reg(intp, ACLC2S2Q, aclc);
911  else if (modulation == STV0900_8PSK) {
912  stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
913  stv0900_write_reg(intp, ACLC2S28, aclc);
914  } else if (modulation == STV0900_16APSK) {
915  stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
916  stv0900_write_reg(intp, ACLC2S216A, aclc);
917  } else if (modulation == STV0900_32APSK) {
918  stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
919  stv0900_write_reg(intp, ACLC2S232A, aclc);
920  }
921 
922  }
923 
924  if (intp->chip_id <= 0x11) {
925  if (intp->demod_mode != STV0900_SINGLE)
926  stv0900_activate_s2_modcod(intp, demod);
927 
928  }
929 
930  stv0900_write_reg(intp, ERRCTRL1, 0x67);
931  break;
932  case STV0900_UNKNOWN_STANDARD:
933  default:
934  dprintk("%s: found unknown standard\n", __func__);
935  stv0900_write_bits(intp, DVBS1_ENABLE, 1);
936  stv0900_write_bits(intp, DVBS2_ENABLE, 1);
937  break;
938  }
939 
940  freq1 = stv0900_read_reg(intp, CFR2);
941  freq0 = stv0900_read_reg(intp, CFR1);
942  if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
943  stv0900_write_reg(intp, SFRSTEP, 0x00);
944  stv0900_write_bits(intp, SCAN_ENABLE, 0);
945  stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
946  stv0900_write_reg(intp, TMGCFG2, 0xc1);
947  stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
948  blind_tun_sw = 1;
949  if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
950  stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
951 
952  }
953 
954  if (intp->chip_id >= 0x20) {
955  if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
956  (intp->srch_standard[demod] ==
957  STV0900_SEARCH_DSS) ||
958  (intp->srch_standard[demod] ==
959  STV0900_AUTO_SEARCH)) {
960  stv0900_write_reg(intp, VAVSRVIT, 0x0a);
961  stv0900_write_reg(intp, VITSCALE, 0x0);
962  }
963  }
964 
965  if (intp->chip_id < 0x20)
966  stv0900_write_reg(intp, CARHDR, 0x08);
967 
968  if (intp->chip_id == 0x10)
969  stv0900_write_reg(intp, CORRELEXP, 0x0a);
970 
971  stv0900_write_reg(intp, AGC2REF, 0x38);
972 
973  if ((intp->chip_id >= 0x20) ||
974  (blind_tun_sw == 1) ||
975  (intp->symbol_rate[demod] < 10000000)) {
976  stv0900_write_reg(intp, CFRINIT1, freq1);
977  stv0900_write_reg(intp, CFRINIT0, freq0);
978  intp->bw[demod] = stv0900_carrier_width(srate,
979  intp->rolloff) + 10000000;
980 
981  if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
982  if (intp->srch_algo[demod] != STV0900_WARM_START) {
983  if (intp->tuner_type[demod] == 3)
984  stv0900_set_tuner_auto(intp,
985  intp->freq[demod],
986  intp->bw[demod],
987  demod);
988  else
989  stv0900_set_bandwidth(fe,
990  intp->bw[demod]);
991  }
992  }
993 
994  if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
995  (intp->symbol_rate[demod] < 10000000))
996  msleep(50);
997  else
998  msleep(5);
999 
1000  stv0900_get_lock_timeout(&timed, &timef, srate,
1001  STV0900_WARM_START);
1002 
1003  if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
1004  stv0900_write_reg(intp, DMDISTATE, 0x1f);
1005  stv0900_write_reg(intp, CFRINIT1, freq1);
1006  stv0900_write_reg(intp, CFRINIT0, freq0);
1007  stv0900_write_reg(intp, DMDISTATE, 0x18);
1008  i = 0;
1009  while ((stv0900_get_demod_lock(intp,
1010  demod,
1011  timed / 2) == FALSE) &&
1012  (i <= 2)) {
1013  stv0900_write_reg(intp, DMDISTATE, 0x1f);
1014  stv0900_write_reg(intp, CFRINIT1, freq1);
1015  stv0900_write_reg(intp, CFRINIT0, freq0);
1016  stv0900_write_reg(intp, DMDISTATE, 0x18);
1017  i++;
1018  }
1019  }
1020 
1021  }
1022 
1023  if (intp->chip_id >= 0x20)
1024  stv0900_write_reg(intp, CARFREQ, 0x49);
1025 
1026  if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1027  (intp->result[demod].standard == STV0900_DSS_STANDARD))
1028  stv0900_set_viterbi_tracq(intp, demod);
1029 
1030 }
1031 
1032 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1033  enum fe_stv0900_demod_num demod, s32 time_out)
1034 {
1035  s32 timer = 0, lock = 0;
1036 
1037  enum fe_stv0900_search_state dmd_state;
1038 
1039  dprintk("%s\n", __func__);
1040 
1041  dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1042 
1043  while ((timer < time_out) && (lock == 0)) {
1044  switch (dmd_state) {
1045  case STV0900_SEARCH:
1046  case STV0900_PLH_DETECTED:
1047  default:
1048  lock = 0;
1049  break;
1050  case STV0900_DVBS2_FOUND:
1051  lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1052  break;
1053  case STV0900_DVBS_FOUND:
1054  lock = stv0900_get_bits(intp, LOCKEDVIT);
1055  break;
1056  }
1057 
1058  if (lock == 0) {
1059  msleep(10);
1060  timer += 10;
1061  }
1062  }
1063 
1064  if (lock)
1065  dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1066  else
1067  dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1068 
1069  return lock;
1070 }
1071 
1072 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1073  enum fe_stv0900_demod_num demod,
1074  s32 dmd_timeout, s32 fec_timeout)
1075 {
1076 
1077  s32 timer = 0, lock = 0;
1078 
1079  dprintk("%s\n", __func__);
1080 
1081  lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1082 
1083  if (lock)
1084  lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
1085 
1086  if (lock) {
1087  lock = 0;
1088 
1089  dprintk("%s: Timer = %d, time_out = %d\n",
1090  __func__, timer, fec_timeout);
1091 
1092  while ((timer < fec_timeout) && (lock == 0)) {
1093  lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1094  msleep(1);
1095  timer++;
1096  }
1097  }
1098 
1099  if (lock)
1100  dprintk("%s: DEMOD LOCK OK\n", __func__);
1101  else
1102  dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1103 
1104  if (lock)
1105  return TRUE;
1106  else
1107  return FALSE;
1108 }
1109 
1110 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1111  enum fe_stv0900_demod_num demod)
1112 {
1113  struct stv0900_state *state = fe->demodulator_priv;
1114  struct stv0900_internal *intp = state->internal;
1115  enum fe_stv0900_tracking_standard fnd_standard;
1116 
1117  int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1118 
1119  switch (hdr_mode) {
1120  case 2:
1121  fnd_standard = STV0900_DVBS2_STANDARD;
1122  break;
1123  case 3:
1124  if (stv0900_get_bits(intp, DSS_DVB) == 1)
1125  fnd_standard = STV0900_DSS_STANDARD;
1126  else
1127  fnd_standard = STV0900_DVBS1_STANDARD;
1128 
1129  break;
1130  default:
1131  fnd_standard = STV0900_UNKNOWN_STANDARD;
1132  }
1133 
1134  dprintk("%s: standard %d\n", __func__, fnd_standard);
1135 
1136  return fnd_standard;
1137 }
1138 
1139 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1140  enum fe_stv0900_demod_num demod)
1141 {
1142  s32 derot,
1143  rem1,
1144  rem2,
1145  intval1,
1146  intval2;
1147 
1148  derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1149  (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1150  (stv0900_get_bits(intp, CAR_FREQ0));
1151 
1152  derot = ge2comp(derot, 24);
1153  intval1 = mclk >> 12;
1154  intval2 = derot >> 12;
1155  rem1 = mclk % 0x1000;
1156  rem2 = derot % 0x1000;
1157  derot = (intval1 * intval2) +
1158  ((intval1 * rem2) >> 12) +
1159  ((intval2 * rem1) >> 12);
1160 
1161  return derot;
1162 }
1163 
1164 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1165 {
1166  struct dvb_frontend_ops *frontend_ops = NULL;
1167  struct dvb_tuner_ops *tuner_ops = NULL;
1168  u32 freq = 0;
1169 
1170  if (&fe->ops)
1171  frontend_ops = &fe->ops;
1172 
1173  if (&frontend_ops->tuner_ops)
1174  tuner_ops = &frontend_ops->tuner_ops;
1175 
1176  if (tuner_ops->get_frequency) {
1177  if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1178  dprintk("%s: Invalid parameter\n", __func__);
1179  else
1180  dprintk("%s: Frequency=%d\n", __func__, freq);
1181 
1182  }
1183 
1184  return freq;
1185 }
1186 
1187 static enum
1188 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1189 {
1190  struct stv0900_state *state = fe->demodulator_priv;
1191  struct stv0900_internal *intp = state->internal;
1192  enum fe_stv0900_demod_num demod = state->demod;
1193  enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1194  struct stv0900_signal_info *result = &intp->result[demod];
1195  s32 offsetFreq,
1196  srate_offset;
1197  int i = 0,
1198  d = demod;
1199 
1200  u8 timing;
1201 
1202  msleep(5);
1203  if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1204  timing = stv0900_read_reg(intp, TMGREG2);
1205  i = 0;
1206  stv0900_write_reg(intp, SFRSTEP, 0x5c);
1207 
1208  while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1209  timing = stv0900_read_reg(intp, TMGREG2);
1210  msleep(5);
1211  i += 5;
1212  }
1213  }
1214 
1215  result->standard = stv0900_get_standard(fe, d);
1216  if (intp->tuner_type[demod] == 3)
1217  result->frequency = stv0900_get_freq_auto(intp, d);
1218  else
1219  result->frequency = stv0900_get_tuner_freq(fe);
1220 
1221  offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1222  result->frequency += offsetFreq;
1223  result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1224  srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1225  result->symbol_rate += srate_offset;
1226  result->fec = stv0900_get_vit_fec(intp, d);
1227  result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1228  result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1229  result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1230  result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1231 
1232  dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
1233 
1234  switch (result->standard) {
1235  case STV0900_DVBS2_STANDARD:
1236  result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1237  if (result->modcode <= STV0900_QPSK_910)
1238  result->modulation = STV0900_QPSK;
1239  else if (result->modcode <= STV0900_8PSK_910)
1240  result->modulation = STV0900_8PSK;
1241  else if (result->modcode <= STV0900_16APSK_910)
1242  result->modulation = STV0900_16APSK;
1243  else if (result->modcode <= STV0900_32APSK_910)
1244  result->modulation = STV0900_32APSK;
1245  else
1246  result->modulation = STV0900_UNKNOWN;
1247  break;
1248  case STV0900_DVBS1_STANDARD:
1249  case STV0900_DSS_STANDARD:
1250  result->spectrum = stv0900_get_bits(intp, IQINV);
1251  result->modulation = STV0900_QPSK;
1252  break;
1253  default:
1254  break;
1255  }
1256 
1257  if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1258  (intp->symbol_rate[d] < 10000000)) {
1259  offsetFreq = result->frequency - intp->freq[d];
1260  if (intp->tuner_type[demod] == 3)
1261  intp->freq[d] = stv0900_get_freq_auto(intp, d);
1262  else
1263  intp->freq[d] = stv0900_get_tuner_freq(fe);
1264 
1265  if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1266  range = STV0900_RANGEOK;
1267  else if (ABS(offsetFreq) <=
1268  (stv0900_carrier_width(result->symbol_rate,
1269  result->rolloff) / 2000))
1270  range = STV0900_RANGEOK;
1271 
1272  } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1273  range = STV0900_RANGEOK;
1274 
1275  dprintk("%s: range %d\n", __func__, range);
1276 
1277  return range;
1278 }
1279 
1280 static enum
1281 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1282 {
1283  struct stv0900_state *state = fe->demodulator_priv;
1284  struct stv0900_internal *intp = state->internal;
1285  enum fe_stv0900_demod_num demod = state->demod;
1286  enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1287 
1288  s32 srate,
1289  demod_timeout,
1290  fec_timeout,
1291  freq1,
1292  freq0;
1293 
1294  intp->result[demod].locked = FALSE;
1295 
1296  if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1297  srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1298  srate += stv0900_get_timing_offst(intp, srate, demod);
1299  if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1300  stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1301 
1302  stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1303  srate, STV0900_WARM_START);
1304  freq1 = stv0900_read_reg(intp, CFR2);
1305  freq0 = stv0900_read_reg(intp, CFR1);
1306  stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1307  stv0900_write_bits(intp, SPECINV_CONTROL,
1308  STV0900_IQ_FORCE_SWAPPED);
1309  stv0900_write_reg(intp, DMDISTATE, 0x1c);
1310  stv0900_write_reg(intp, CFRINIT1, freq1);
1311  stv0900_write_reg(intp, CFRINIT0, freq0);
1312  stv0900_write_reg(intp, DMDISTATE, 0x18);
1313  if (stv0900_wait_for_lock(intp, demod,
1314  demod_timeout, fec_timeout) == TRUE) {
1315  intp->result[demod].locked = TRUE;
1316  signal_type = stv0900_get_signal_params(fe);
1317  stv0900_track_optimization(fe);
1318  } else {
1319  stv0900_write_bits(intp, SPECINV_CONTROL,
1320  STV0900_IQ_FORCE_NORMAL);
1321  stv0900_write_reg(intp, DMDISTATE, 0x1c);
1322  stv0900_write_reg(intp, CFRINIT1, freq1);
1323  stv0900_write_reg(intp, CFRINIT0, freq0);
1324  stv0900_write_reg(intp, DMDISTATE, 0x18);
1325  if (stv0900_wait_for_lock(intp, demod,
1326  demod_timeout, fec_timeout) == TRUE) {
1327  intp->result[demod].locked = TRUE;
1328  signal_type = stv0900_get_signal_params(fe);
1329  stv0900_track_optimization(fe);
1330  }
1331 
1332  }
1333 
1334  } else
1335  intp->result[demod].locked = FALSE;
1336 
1337  return signal_type;
1338 }
1339 
1340 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1341  enum fe_stv0900_demod_num demod)
1342 {
1343  u32 minagc2level = 0xffff,
1344  agc2level,
1345  init_freq, freq_step;
1346 
1347  s32 i, j, nb_steps, direction;
1348 
1349  dprintk("%s\n", __func__);
1350 
1351  stv0900_write_reg(intp, AGC2REF, 0x38);
1352  stv0900_write_bits(intp, SCAN_ENABLE, 0);
1353  stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1354 
1355  stv0900_write_bits(intp, AUTO_GUP, 1);
1356  stv0900_write_bits(intp, AUTO_GLOW, 1);
1357 
1358  stv0900_write_reg(intp, DMDT0M, 0x0);
1359 
1360  stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1361  nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1362  nb_steps /= 2;
1363  nb_steps = (2 * nb_steps) + 1;
1364 
1365  if (nb_steps < 0)
1366  nb_steps = 1;
1367 
1368  direction = 1;
1369 
1370  freq_step = (1000000 << 8) / (intp->mclk >> 8);
1371 
1372  init_freq = 0;
1373 
1374  for (i = 0; i < nb_steps; i++) {
1375  if (direction > 0)
1376  init_freq = init_freq + (freq_step * i);
1377  else
1378  init_freq = init_freq - (freq_step * i);
1379 
1380  direction *= -1;
1381  stv0900_write_reg(intp, DMDISTATE, 0x5C);
1382  stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1383  stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1384  stv0900_write_reg(intp, DMDISTATE, 0x58);
1385  msleep(10);
1386  agc2level = 0;
1387 
1388  for (j = 0; j < 10; j++)
1389  agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1390  | stv0900_read_reg(intp, AGC2I0);
1391 
1392  agc2level /= 10;
1393 
1394  if (agc2level < minagc2level)
1395  minagc2level = agc2level;
1396 
1397  }
1398 
1399  return (u16)minagc2level;
1400 }
1401 
1402 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1403 {
1404  struct stv0900_state *state = fe->demodulator_priv;
1405  struct stv0900_internal *intp = state->internal;
1406  enum fe_stv0900_demod_num demod = state->demod;
1407  int timing_lck = FALSE;
1408  s32 i, timingcpt = 0,
1409  direction = 1,
1410  nb_steps,
1411  current_step = 0,
1412  tuner_freq;
1413  u32 agc2_th,
1414  coarse_srate = 0,
1415  agc2_integr = 0,
1416  currier_step = 1200;
1417 
1418  if (intp->chip_id >= 0x30)
1419  agc2_th = 0x2e00;
1420  else
1421  agc2_th = 0x1f00;
1422 
1423  stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1424  stv0900_write_reg(intp, TMGCFG, 0x12);
1425  stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1426  stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1427  stv0900_write_bits(intp, SCAN_ENABLE, 1);
1428  stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1429  stv0900_write_reg(intp, SFRUP1, 0x83);
1430  stv0900_write_reg(intp, SFRUP0, 0xc0);
1431  stv0900_write_reg(intp, SFRLOW1, 0x82);
1432  stv0900_write_reg(intp, SFRLOW0, 0xa0);
1433  stv0900_write_reg(intp, DMDT0M, 0x0);
1434  stv0900_write_reg(intp, AGC2REF, 0x50);
1435 
1436  if (intp->chip_id >= 0x30) {
1437  stv0900_write_reg(intp, CARFREQ, 0x99);
1438  stv0900_write_reg(intp, SFRSTEP, 0x98);
1439  } else if (intp->chip_id >= 0x20) {
1440  stv0900_write_reg(intp, CARFREQ, 0x6a);
1441  stv0900_write_reg(intp, SFRSTEP, 0x95);
1442  } else {
1443  stv0900_write_reg(intp, CARFREQ, 0xed);
1444  stv0900_write_reg(intp, SFRSTEP, 0x73);
1445  }
1446 
1447  if (intp->symbol_rate[demod] <= 2000000)
1448  currier_step = 1000;
1449  else if (intp->symbol_rate[demod] <= 5000000)
1450  currier_step = 2000;
1451  else if (intp->symbol_rate[demod] <= 12000000)
1452  currier_step = 3000;
1453  else
1454  currier_step = 5000;
1455 
1456  nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1457  nb_steps /= 2;
1458  nb_steps = (2 * nb_steps) + 1;
1459 
1460  if (nb_steps < 0)
1461  nb_steps = 1;
1462  else if (nb_steps > 10) {
1463  nb_steps = 11;
1464  currier_step = (intp->srch_range[demod] / 1000) / 10;
1465  }
1466 
1467  current_step = 0;
1468  direction = 1;
1469 
1470  tuner_freq = intp->freq[demod];
1471 
1472  while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1473  stv0900_write_reg(intp, DMDISTATE, 0x5f);
1474  stv0900_write_bits(intp, DEMOD_MODE, 0);
1475 
1476  msleep(50);
1477 
1478  for (i = 0; i < 10; i++) {
1479  if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1480  timingcpt++;
1481 
1482  agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1483  stv0900_read_reg(intp, AGC2I0);
1484  }
1485 
1486  agc2_integr /= 10;
1487  coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1488  current_step++;
1489  direction *= -1;
1490 
1491  dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
1492  " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1493  tuner_freq, agc2_integr, coarse_srate, timingcpt);
1494 
1495  if ((timingcpt >= 5) &&
1496  (agc2_integr < agc2_th) &&
1497  (coarse_srate < 55000000) &&
1498  (coarse_srate > 850000))
1499  timing_lck = TRUE;
1500  else if (current_step < nb_steps) {
1501  if (direction > 0)
1502  tuner_freq += (current_step * currier_step);
1503  else
1504  tuner_freq -= (current_step * currier_step);
1505 
1506  if (intp->tuner_type[demod] == 3)
1507  stv0900_set_tuner_auto(intp, tuner_freq,
1508  intp->bw[demod], demod);
1509  else
1510  stv0900_set_tuner(fe, tuner_freq,
1511  intp->bw[demod]);
1512  }
1513  }
1514 
1515  if (timing_lck == FALSE)
1516  coarse_srate = 0;
1517  else
1518  coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1519 
1520  return coarse_srate;
1521 }
1522 
1523 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1524 {
1525  struct stv0900_state *state = fe->demodulator_priv;
1526  struct stv0900_internal *intp = state->internal;
1527  enum fe_stv0900_demod_num demod = state->demod;
1528  u32 coarse_srate,
1529  coarse_freq,
1530  symb,
1531  symbmax,
1532  symbmin,
1533  symbcomp;
1534 
1535  coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1536 
1537  if (coarse_srate > 3000000) {
1538  symbmax = 13 * (coarse_srate / 10);
1539  symbmax = (symbmax / 1000) * 65536;
1540  symbmax /= (intp->mclk / 1000);
1541 
1542  symbmin = 10 * (coarse_srate / 13);
1543  symbmin = (symbmin / 1000)*65536;
1544  symbmin /= (intp->mclk / 1000);
1545 
1546  symb = (coarse_srate / 1000) * 65536;
1547  symb /= (intp->mclk / 1000);
1548  } else {
1549  symbmax = 13 * (coarse_srate / 10);
1550  symbmax = (symbmax / 100) * 65536;
1551  symbmax /= (intp->mclk / 100);
1552 
1553  symbmin = 10 * (coarse_srate / 14);
1554  symbmin = (symbmin / 100) * 65536;
1555  symbmin /= (intp->mclk / 100);
1556 
1557  symb = (coarse_srate / 100) * 65536;
1558  symb /= (intp->mclk / 100);
1559  }
1560 
1561  symbcomp = 13 * (coarse_srate / 10);
1562  coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1563  | stv0900_read_reg(intp, CFR1);
1564 
1565  if (symbcomp < intp->symbol_rate[demod])
1566  coarse_srate = 0;
1567  else {
1568  stv0900_write_reg(intp, DMDISTATE, 0x1f);
1569  stv0900_write_reg(intp, TMGCFG2, 0xc1);
1570  stv0900_write_reg(intp, TMGTHRISE, 0x20);
1571  stv0900_write_reg(intp, TMGTHFALL, 0x00);
1572  stv0900_write_reg(intp, TMGCFG, 0xd2);
1573  stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1574  stv0900_write_reg(intp, AGC2REF, 0x38);
1575 
1576  if (intp->chip_id >= 0x30)
1577  stv0900_write_reg(intp, CARFREQ, 0x79);
1578  else if (intp->chip_id >= 0x20)
1579  stv0900_write_reg(intp, CARFREQ, 0x49);
1580  else
1581  stv0900_write_reg(intp, CARFREQ, 0xed);
1582 
1583  stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1584  stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1585 
1586  stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1587  stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1588 
1589  stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1590  stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1591 
1592  stv0900_write_reg(intp, DMDT0M, 0x20);
1593  stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1594  stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1595  stv0900_write_reg(intp, DMDISTATE, 0x15);
1596  }
1597 
1598  return coarse_srate;
1599 }
1600 
1601 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1602 {
1603  struct stv0900_state *state = fe->demodulator_priv;
1604  struct stv0900_internal *intp = state->internal;
1605  enum fe_stv0900_demod_num demod = state->demod;
1606  u8 k_ref_tmg,
1607  k_ref_tmg_max,
1608  k_ref_tmg_min;
1609  u32 coarse_srate,
1610  agc2_th;
1611  int lock = FALSE,
1612  coarse_fail = FALSE;
1613  s32 demod_timeout = 500,
1614  fec_timeout = 50,
1615  fail_cpt,
1616  i,
1617  agc2_overflow;
1618  u16 agc2_int;
1619  u8 dstatus2;
1620 
1621  dprintk("%s\n", __func__);
1622 
1623  if (intp->chip_id < 0x20) {
1624  k_ref_tmg_max = 233;
1625  k_ref_tmg_min = 143;
1626  } else {
1627  k_ref_tmg_max = 110;
1628  k_ref_tmg_min = 10;
1629  }
1630 
1631  if (intp->chip_id <= 0x20)
1632  agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1633  else
1634  agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1635 
1636  agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1637 
1638  dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
1639  if (agc2_int > agc2_th)
1640  return FALSE;
1641 
1642  if (intp->chip_id == 0x10)
1643  stv0900_write_reg(intp, CORRELEXP, 0xaa);
1644 
1645  if (intp->chip_id < 0x20)
1646  stv0900_write_reg(intp, CARHDR, 0x55);
1647  else
1648  stv0900_write_reg(intp, CARHDR, 0x20);
1649 
1650  if (intp->chip_id <= 0x20)
1651  stv0900_write_reg(intp, CARCFG, 0xc4);
1652  else
1653  stv0900_write_reg(intp, CARCFG, 0x6);
1654 
1655  stv0900_write_reg(intp, RTCS2, 0x44);
1656 
1657  if (intp->chip_id >= 0x20) {
1658  stv0900_write_reg(intp, EQUALCFG, 0x41);
1659  stv0900_write_reg(intp, FFECFG, 0x41);
1660  stv0900_write_reg(intp, VITSCALE, 0x82);
1661  stv0900_write_reg(intp, VAVSRVIT, 0x0);
1662  }
1663 
1664  k_ref_tmg = k_ref_tmg_max;
1665 
1666  do {
1667  stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1668  if (stv0900_search_srate_coarse(fe) != 0) {
1669  coarse_srate = stv0900_search_srate_fine(fe);
1670 
1671  if (coarse_srate != 0) {
1672  stv0900_get_lock_timeout(&demod_timeout,
1673  &fec_timeout,
1674  coarse_srate,
1675  STV0900_BLIND_SEARCH);
1676  lock = stv0900_get_demod_lock(intp,
1677  demod,
1678  demod_timeout);
1679  } else
1680  lock = FALSE;
1681  } else {
1682  fail_cpt = 0;
1683  agc2_overflow = 0;
1684 
1685  for (i = 0; i < 10; i++) {
1686  agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1687  | stv0900_read_reg(intp, AGC2I0);
1688 
1689  if (agc2_int >= 0xff00)
1690  agc2_overflow++;
1691 
1692  dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1693 
1694  if (((dstatus2 & 0x1) == 0x1) &&
1695  ((dstatus2 >> 7) == 1))
1696  fail_cpt++;
1697  }
1698 
1699  if ((fail_cpt > 7) || (agc2_overflow > 7))
1700  coarse_fail = TRUE;
1701 
1702  lock = FALSE;
1703  }
1704  k_ref_tmg -= 30;
1705  } while ((k_ref_tmg >= k_ref_tmg_min) &&
1706  (lock == FALSE) &&
1707  (coarse_fail == FALSE));
1708 
1709  return lock;
1710 }
1711 
1712 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1713  enum fe_stv0900_demod_num demod)
1714 {
1715  s32 vth_reg = VTH12;
1716 
1717  dprintk("%s\n", __func__);
1718 
1719  stv0900_write_reg(intp, vth_reg++, 0x96);
1720  stv0900_write_reg(intp, vth_reg++, 0x64);
1721  stv0900_write_reg(intp, vth_reg++, 0x36);
1722  stv0900_write_reg(intp, vth_reg++, 0x23);
1723  stv0900_write_reg(intp, vth_reg++, 0x1e);
1724  stv0900_write_reg(intp, vth_reg++, 0x19);
1725 }
1726 
1727 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1728  enum fe_stv0900_demod_num demod)
1729 {
1730 
1731  dprintk("%s\n", __func__);
1732 
1733  switch (intp->srch_standard[demod]) {
1734  case STV0900_SEARCH_DVBS1:
1735  dprintk("Search Standard = DVBS1\n");
1736  break;
1737  case STV0900_SEARCH_DSS:
1738  dprintk("Search Standard = DSS\n");
1739  case STV0900_SEARCH_DVBS2:
1740  break;
1741  dprintk("Search Standard = DVBS2\n");
1742  case STV0900_AUTO_SEARCH:
1743  default:
1744  dprintk("Search Standard = AUTO\n");
1745  break;
1746  }
1747 
1748  switch (intp->srch_standard[demod]) {
1749  case STV0900_SEARCH_DVBS1:
1750  case STV0900_SEARCH_DSS:
1751  stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1752  stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1753  stv0900_write_bits(intp, STOP_CLKVIT, 0);
1754  stv0900_set_dvbs1_track_car_loop(intp,
1755  demod,
1756  intp->symbol_rate[demod]);
1757  stv0900_write_reg(intp, CAR2CFG, 0x22);
1758 
1759  stv0900_set_viterbi_acq(intp, demod);
1760  stv0900_set_viterbi_standard(intp,
1761  intp->srch_standard[demod],
1762  intp->fec[demod], demod);
1763 
1764  break;
1765  case STV0900_SEARCH_DVBS2:
1766  stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1767  stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1768  stv0900_write_bits(intp, STOP_CLKVIT, 1);
1769  stv0900_write_reg(intp, ACLC, 0x1a);
1770  stv0900_write_reg(intp, BCLC, 0x09);
1771  if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1772  stv0900_write_reg(intp, CAR2CFG, 0x26);
1773  else
1774  stv0900_write_reg(intp, CAR2CFG, 0x66);
1775 
1776  if (intp->demod_mode != STV0900_SINGLE) {
1777  if (intp->chip_id <= 0x11)
1778  stv0900_stop_all_s2_modcod(intp, demod);
1779  else
1780  stv0900_activate_s2_modcod(intp, demod);
1781 
1782  } else
1783  stv0900_activate_s2_modcod_single(intp, demod);
1784 
1785  stv0900_set_viterbi_tracq(intp, demod);
1786 
1787  break;
1788  case STV0900_AUTO_SEARCH:
1789  default:
1790  stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1791  stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1792  stv0900_write_bits(intp, STOP_CLKVIT, 0);
1793  stv0900_write_reg(intp, ACLC, 0x1a);
1794  stv0900_write_reg(intp, BCLC, 0x09);
1795  stv0900_set_dvbs1_track_car_loop(intp,
1796  demod,
1797  intp->symbol_rate[demod]);
1798  if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1799  stv0900_write_reg(intp, CAR2CFG, 0x26);
1800  else
1801  stv0900_write_reg(intp, CAR2CFG, 0x66);
1802 
1803  if (intp->demod_mode != STV0900_SINGLE) {
1804  if (intp->chip_id <= 0x11)
1805  stv0900_stop_all_s2_modcod(intp, demod);
1806  else
1807  stv0900_activate_s2_modcod(intp, demod);
1808 
1809  } else
1810  stv0900_activate_s2_modcod_single(intp, demod);
1811 
1812  stv0900_set_viterbi_tracq(intp, demod);
1813  stv0900_set_viterbi_standard(intp,
1814  intp->srch_standard[demod],
1815  intp->fec[demod], demod);
1816 
1817  break;
1818  }
1819 }
1820 
1821 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1822 {
1823  struct stv0900_state *state = fe->demodulator_priv;
1824  struct stv0900_internal *intp = state->internal;
1825  enum fe_stv0900_demod_num demod = state->demod;
1826 
1827  s32 demod_timeout = 500, fec_timeout = 50;
1828  s32 aq_power, agc1_power, i;
1829 
1830  int lock = FALSE, low_sr = FALSE;
1831 
1832  enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1833  enum fe_stv0900_search_algo algo;
1834  int no_signal = FALSE;
1835 
1836  dprintk("%s\n", __func__);
1837 
1838  algo = intp->srch_algo[demod];
1839  stv0900_write_bits(intp, RST_HWARE, 1);
1840  stv0900_write_reg(intp, DMDISTATE, 0x5c);
1841  if (intp->chip_id >= 0x20) {
1842  if (intp->symbol_rate[demod] > 5000000)
1843  stv0900_write_reg(intp, CORRELABS, 0x9e);
1844  else
1845  stv0900_write_reg(intp, CORRELABS, 0x82);
1846  } else
1847  stv0900_write_reg(intp, CORRELABS, 0x88);
1848 
1849  stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1850  intp->symbol_rate[demod],
1851  intp->srch_algo[demod]);
1852 
1853  if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1854  intp->bw[demod] = 2 * 36000000;
1855 
1856  stv0900_write_reg(intp, TMGCFG2, 0xc0);
1857  stv0900_write_reg(intp, CORRELMANT, 0x70);
1858 
1859  stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1860  } else {
1861  stv0900_write_reg(intp, DMDT0M, 0x20);
1862  stv0900_write_reg(intp, TMGCFG, 0xd2);
1863 
1864  if (intp->symbol_rate[demod] < 2000000)
1865  stv0900_write_reg(intp, CORRELMANT, 0x63);
1866  else
1867  stv0900_write_reg(intp, CORRELMANT, 0x70);
1868 
1869  stv0900_write_reg(intp, AGC2REF, 0x38);
1870 
1871  intp->bw[demod] =
1872  stv0900_carrier_width(intp->symbol_rate[demod],
1873  intp->rolloff);
1874  if (intp->chip_id >= 0x20) {
1875  stv0900_write_reg(intp, KREFTMG, 0x5a);
1876 
1877  if (intp->srch_algo[demod] == STV0900_COLD_START) {
1878  intp->bw[demod] += 10000000;
1879  intp->bw[demod] *= 15;
1880  intp->bw[demod] /= 10;
1881  } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1882  intp->bw[demod] += 10000000;
1883 
1884  } else {
1885  stv0900_write_reg(intp, KREFTMG, 0xc1);
1886  intp->bw[demod] += 10000000;
1887  intp->bw[demod] *= 15;
1888  intp->bw[demod] /= 10;
1889  }
1890 
1891  stv0900_write_reg(intp, TMGCFG2, 0xc1);
1892 
1893  stv0900_set_symbol_rate(intp, intp->mclk,
1894  intp->symbol_rate[demod], demod);
1895  stv0900_set_max_symbol_rate(intp, intp->mclk,
1896  intp->symbol_rate[demod], demod);
1897  stv0900_set_min_symbol_rate(intp, intp->mclk,
1898  intp->symbol_rate[demod], demod);
1899  if (intp->symbol_rate[demod] >= 10000000)
1900  low_sr = FALSE;
1901  else
1902  low_sr = TRUE;
1903 
1904  }
1905 
1906  if (intp->tuner_type[demod] == 3)
1907  stv0900_set_tuner_auto(intp, intp->freq[demod],
1908  intp->bw[demod], demod);
1909  else
1910  stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1911 
1912  agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1913  stv0900_get_bits(intp, AGCIQ_VALUE0));
1914 
1915  aq_power = 0;
1916 
1917  if (agc1_power == 0) {
1918  for (i = 0; i < 5; i++)
1919  aq_power += (stv0900_get_bits(intp, POWER_I) +
1920  stv0900_get_bits(intp, POWER_Q)) / 2;
1921 
1922  aq_power /= 5;
1923  }
1924 
1925  if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1926  intp->result[demod].locked = FALSE;
1927  signal_type = STV0900_NOAGC1;
1928  dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1929  } else {
1930  stv0900_write_bits(intp, SPECINV_CONTROL,
1931  intp->srch_iq_inv[demod]);
1932  if (intp->chip_id <= 0x20) /*cut 2.0*/
1933  stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1934  else /*cut 3.0*/
1935  stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1936 
1937  stv0900_set_search_standard(intp, demod);
1938 
1939  if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1940  stv0900_start_search(intp, demod);
1941  }
1942 
1943  if (signal_type == STV0900_NOAGC1)
1944  return signal_type;
1945 
1946  if (intp->chip_id == 0x12) {
1947  stv0900_write_bits(intp, RST_HWARE, 0);
1948  msleep(3);
1949  stv0900_write_bits(intp, RST_HWARE, 1);
1950  stv0900_write_bits(intp, RST_HWARE, 0);
1951  }
1952 
1953  if (algo == STV0900_BLIND_SEARCH)
1954  lock = stv0900_blind_search_algo(fe);
1955  else if (algo == STV0900_COLD_START)
1956  lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1957  else if (algo == STV0900_WARM_START)
1958  lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1959 
1960  if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1961  if (low_sr == FALSE) {
1962  if (stv0900_check_timing_lock(intp, demod) == TRUE)
1963  lock = stv0900_sw_algo(intp, demod);
1964  }
1965  }
1966 
1967  if (lock == TRUE)
1968  signal_type = stv0900_get_signal_params(fe);
1969 
1970  if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1971  stv0900_track_optimization(fe);
1972  if (intp->chip_id <= 0x11) {
1973  if ((stv0900_get_standard(fe, 0) ==
1974  STV0900_DVBS1_STANDARD) &&
1975  (stv0900_get_standard(fe, 1) ==
1976  STV0900_DVBS1_STANDARD)) {
1977  msleep(20);
1978  stv0900_write_bits(intp, RST_HWARE, 0);
1979  } else {
1980  stv0900_write_bits(intp, RST_HWARE, 0);
1981  msleep(3);
1982  stv0900_write_bits(intp, RST_HWARE, 1);
1983  stv0900_write_bits(intp, RST_HWARE, 0);
1984  }
1985 
1986  } else if (intp->chip_id >= 0x20) {
1987  stv0900_write_bits(intp, RST_HWARE, 0);
1988  msleep(3);
1989  stv0900_write_bits(intp, RST_HWARE, 1);
1990  stv0900_write_bits(intp, RST_HWARE, 0);
1991  }
1992 
1993  if (stv0900_wait_for_lock(intp, demod,
1994  fec_timeout, fec_timeout) == TRUE) {
1995  lock = TRUE;
1996  intp->result[demod].locked = TRUE;
1997  if (intp->result[demod].standard ==
1998  STV0900_DVBS2_STANDARD) {
1999  stv0900_set_dvbs2_rolloff(intp, demod);
2000  stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
2001  stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
2002  stv0900_write_reg(intp, ERRCTRL1, 0x67);
2003  } else {
2004  stv0900_write_reg(intp, ERRCTRL1, 0x75);
2005  }
2006 
2007  stv0900_write_reg(intp, FBERCPT4, 0);
2008  stv0900_write_reg(intp, ERRCTRL2, 0xc1);
2009  } else {
2010  lock = FALSE;
2011  signal_type = STV0900_NODATA;
2012  no_signal = stv0900_check_signal_presence(intp, demod);
2013 
2014  intp->result[demod].locked = FALSE;
2015  }
2016  }
2017 
2018  if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2019  return signal_type;
2020 
2021  if (intp->chip_id > 0x11) {
2022  intp->result[demod].locked = FALSE;
2023  return signal_type;
2024  }
2025 
2026  if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2027  (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
2028  signal_type = stv0900_dvbs1_acq_workaround(fe);
2029 
2030  return signal_type;
2031 }
2032 
Generated on Thu Jan 10 2013 13:46:01 for Linux Kernel by   doxygen 1.8.2