Data Structures
struct	gem_txd

struct	gem_rxd

struct	gem_init_block

struct	gem

Macros
#define	GREG_SEBSTATE 0x0000UL /* SEB State Register */

#define	GREG_CFG 0x0004UL /* Configuration Register */

#define	GREG_STAT 0x000CUL /* Status Register */

#define	GREG_IMASK 0x0010UL /* Interrupt Mask Register */

#define	GREG_IACK 0x0014UL /* Interrupt ACK Register */

#define	GREG_STAT2 0x001CUL /* Alias of GREG_STAT */

#define	GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */

#define	GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */

#define	GREG_BIFCFG 0x1008UL /* BIF Configuration Register */

#define	GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */

#define	GREG_SWRST 0x1010UL /* Software Reset Register */

#define	GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */

#define	GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */

#define	GREG_CFG_IBURST 0x00000001 /* Infinite Burst */

#define	GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */

#define	GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */

#define	GREG_CFG_RONPAULBIT

#define	GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */

#define	GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */

#define	GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */

#define	GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */

#define	GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */

#define	GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */

#define	GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */

#define	GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */

#define	GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */

#define	GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */

#define	GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */

#define	GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */

#define	GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */

#define	GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */

#define	GREG_STAT_TXNR_SHIFT 19

#define	GREG_STAT_ABNORMAL

#define	GREG_STAT_NAPI

#define	GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */

#define	GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */

#define	GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */

#define	GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */

#define	GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/

#define	GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */

#define	GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */

#define	GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */

#define	GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */

#define	GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */

#define	GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */

#define	GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */

#define	GREG_SWRST_CACHE_SHIFT 16

#define	TXDMA_KICK 0x2000UL /* TX Kick Register */

#define	TXDMA_CFG 0x2004UL /* TX Configuration Register */

#define	TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */

#define	TXDMA_DBHI 0x200CUL /* TX Desc. Base High */

#define	TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */

#define	TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */

#define	TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */

#define	TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */

#define	TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */

#define	TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */

#define	TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */

#define	TXDMA_DPHI 0x2034UL /* TX Data Pointer High */

#define	TXDMA_TXDONE 0x2100UL /* TX Completion Register */

#define	TXDMA_FADDR 0x2104UL /* TX FIFO Address */

#define	TXDMA_FTAG 0x2108UL /* TX FIFO Tag */

#define	TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */

#define	TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */

#define	TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */

#define	TXDMA_FSZ 0x2118UL /* TX FIFO Size */

#define	TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */

#define	TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */

#define	TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */

#define	TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */

#define	TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */

#define	TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */

#define	TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */

#define	TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */

#define	TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */

#define	TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */

#define	TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */

#define	TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */

#define	TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */

#define	TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/

#define	WOL_MATCH0 0x3000UL

#define	WOL_MATCH1 0x3004UL

#define	WOL_MATCH2 0x3008UL

#define	WOL_MCOUNT 0x300CUL

#define	WOL_WAKECSR 0x3010UL

#define	WOL_MCOUNT_N 0x00000010

#define	WOL_MCOUNT_M 0x00000000 /* 0 << 8 */

#define	WOL_WAKECSR_ENABLE 0x00000001

#define	WOL_WAKECSR_MII 0x00000002

#define	WOL_WAKECSR_SEEN 0x00000004

#define	WOL_WAKECSR_FILT_UCAST 0x00000008

#define	WOL_WAKECSR_FILT_MCAST 0x00000010

#define	WOL_WAKECSR_FILT_BCAST 0x00000020

#define	WOL_WAKECSR_FILT_SEEN 0x00000040

#define	RXDMA_CFG 0x4000UL /* RX Configuration Register */

#define	RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */

#define	RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */

#define	RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */

#define	RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */

#define	RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */

#define	RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */

#define	RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */

#define	RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */

#define	RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */

#define	RXDMA_DPHI 0x4028UL /* RX Data Pointer High */

#define	RXDMA_KICK 0x4100UL /* RX Kick Register */

#define	RXDMA_DONE 0x4104UL /* RX Completion Register */

#define	RXDMA_BLANK 0x4108UL /* RX Blanking Register */

#define	RXDMA_FADDR 0x410CUL /* RX FIFO Address */

#define	RXDMA_FTAG 0x4110UL /* RX FIFO Tag */

#define	RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */

#define	RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */

#define	RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */

#define	RXDMA_FSZ 0x4120UL /* RX FIFO Size */

#define	RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */

#define	RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */

#define	RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */

#define	RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */

#define	RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */

#define	RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */

#define	RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */

#define	RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */

#define	RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */

#define	RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */

#define	RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */

#define	RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */

#define	RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */

#define	RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */

#define	RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */

#define	RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */

#define	RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */

#define	RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */

#define	RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */

#define	RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */

#define	RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */

#define	RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */

#define	RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */

#define	RXDMA_BLANK_IPKTS

#define	RXDMA_BLANK_ITIME

#define	MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/

#define	MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/

#define	MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */

#define	MAC_TXSTAT 0x6010UL /* TX MAC Status Register */

#define	MAC_RXSTAT 0x6014UL /* RX MAC Status Register */

#define	MAC_CSTAT 0x6018UL /* MAC Control Status Register */

#define	MAC_TXMASK 0x6020UL /* TX MAC Mask Register */

#define	MAC_RXMASK 0x6024UL /* RX MAC Mask Register */

#define	MAC_MCMASK 0x6028UL /* MAC Control Mask Register */

#define	MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/

#define	MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/

#define	MAC_MCCFG 0x6038UL /* MAC Control Config Register */

#define	MAC_XIFCFG 0x603CUL /* XIF Configuration Register */

#define	MAC_IPG0 0x6040UL /* InterPacketGap0 Register */

#define	MAC_IPG1 0x6044UL /* InterPacketGap1 Register */

#define	MAC_IPG2 0x6048UL /* InterPacketGap2 Register */

#define	MAC_STIME 0x604CUL /* SlotTime Register */

#define	MAC_MINFSZ 0x6050UL /* MinFrameSize Register */

#define	MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */

#define	MAC_PASIZE 0x6058UL /* PA Size Register */

#define	MAC_JAMSIZE 0x605CUL /* JamSize Register */

#define	MAC_ATTLIM 0x6060UL /* Attempt Limit Register */

#define	MAC_MCTYPE 0x6064UL /* MAC Control Type Register */

#define	MAC_ADDR0 0x6080UL /* MAC Address 0 Register */

#define	MAC_ADDR1 0x6084UL /* MAC Address 1 Register */

#define	MAC_ADDR2 0x6088UL /* MAC Address 2 Register */

#define	MAC_ADDR3 0x608CUL /* MAC Address 3 Register */

#define	MAC_ADDR4 0x6090UL /* MAC Address 4 Register */

#define	MAC_ADDR5 0x6094UL /* MAC Address 5 Register */

#define	MAC_ADDR6 0x6098UL /* MAC Address 6 Register */

#define	MAC_ADDR7 0x609CUL /* MAC Address 7 Register */

#define	MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */

#define	MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */

#define	MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */

#define	MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */

#define	MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */

#define	MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */

#define	MAC_HASH0 0x60C0UL /* Hash Table 0 Register */

#define	MAC_HASH1 0x60C4UL /* Hash Table 1 Register */

#define	MAC_HASH2 0x60C8UL /* Hash Table 2 Register */

#define	MAC_HASH3 0x60CCUL /* Hash Table 3 Register */

#define	MAC_HASH4 0x60D0UL /* Hash Table 4 Register */

#define	MAC_HASH5 0x60D4UL /* Hash Table 5 Register */

#define	MAC_HASH6 0x60D8UL /* Hash Table 6 Register */

#define	MAC_HASH7 0x60DCUL /* Hash Table 7 Register */

#define	MAC_HASH8 0x60E0UL /* Hash Table 8 Register */

#define	MAC_HASH9 0x60E4UL /* Hash Table 9 Register */

#define	MAC_HASH10 0x60E8UL /* Hash Table 10 Register */

#define	MAC_HASH11 0x60ECUL /* Hash Table 11 Register */

#define	MAC_HASH12 0x60F0UL /* Hash Table 12 Register */

#define	MAC_HASH13 0x60F4UL /* Hash Table 13 Register */

#define	MAC_HASH14 0x60F8UL /* Hash Table 14 Register */

#define	MAC_HASH15 0x60FCUL /* Hash Table 15 Register */

#define	MAC_NCOLL 0x6100UL /* Normal Collision Counter */

#define	MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */

#define	MAC_ECOLL 0x6108UL /* Excessive Collision Counter */

#define	MAC_LCOLL 0x610CUL /* Late Collision Counter */

#define	MAC_DTIMER 0x6110UL /* Defer Timer */

#define	MAC_PATMPS 0x6114UL /* Peak Attempts Register */

#define	MAC_RFCTR 0x6118UL /* Receive Frame Counter */

#define	MAC_LERR 0x611CUL /* Length Error Counter */

#define	MAC_AERR 0x6120UL /* Alignment Error Counter */

#define	MAC_FCSERR 0x6124UL /* FCS Error Counter */

#define	MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */

#define	MAC_RANDSEED 0x6130UL /* Random Number Seed Register */

#define	MAC_SMACHINE 0x6134UL /* State Machine Register */

#define	MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */

#define	MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */

#define	MAC_SNDPAUSE_TS

#define	MAC_SNDPAUSE_SP

#define	MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */

#define	MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */

#define	MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */

#define	MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */

#define	MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */

#define	MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */

#define	MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */

#define	MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */

#define	MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */

#define	MAC_RXSTAT_RCV 0x00000001 /* Frame Received */

#define	MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */

#define	MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */

#define	MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */

#define	MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */

#define	MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */

#define	MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */

#define	MAC_CSTAT_PRCV 0x00000001 /* Pause Received */

#define	MAC_CSTAT_PS 0x00000002 /* Paused State */

#define	MAC_CSTAT_NPS 0x00000004 /* Not Paused State */

#define	MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */

#define	MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */

#define	MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */

#define	MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */

#define	MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */

#define	MAC_TXCFG_NGU 0x00000010 /* Never Give Up */

#define	MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */

#define	MAC_TXCFG_NBO 0x00000040 /* No Backoff */

#define	MAC_TXCFG_SD 0x00000080 /* Slow Down */

#define	MAC_TXCFG_NFCS 0x00000100 /* No FCS */

#define	MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */

#define	MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */

#define	MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */

#define	MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */

#define	MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */

#define	MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */

#define	MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */

#define	MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */

#define	MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */

#define	MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */

#define	MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */

#define	MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */

#define	MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */

#define	MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */

#define	MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */

#define	MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */

#define	MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */

#define	MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */

#define	MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */

#define	MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */

#define	MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */

#define	MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */

#define	MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */

#define	MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */

#define	MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */

#define	MIF_FRAME 0x620CUL /* MIF Frame/Output Register */

#define	MIF_CFG 0x6210UL /* MIF Configuration Register */

#define	MIF_MASK 0x6214UL /* MIF Mask Register */

#define	MIF_STATUS 0x6218UL /* MIF Status Register */

#define	MIF_SMACHINE 0x621CUL /* MIF State Machine Register */

#define	MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */

#define	MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */

#define	MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */

#define	MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */

#define	MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */

#define	MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */

#define	MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */

#define	MIF_FRAME_ST 0xc0000000 /* STart of frame */

#define	MIF_FRAME_OP 0x30000000 /* OPcode */

#define	MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */

#define	MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */

#define	MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */

#define	MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */

#define	MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */

#define	MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */

#define	MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */

#define	PCS_MIICTRL 0x9000UL /* PCS MII Control Register */

#define	PCS_MIISTAT 0x9004UL /* PCS MII Status Register */

#define	PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */

#define	PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */

#define	PCS_CFG 0x9010UL /* PCS Configuration Register */

#define	PCS_SMACHINE 0x9014UL /* PCS State Machine Register */

#define	PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */

#define	PCS_DMODE 0x9050UL /* Datapath Mode Register */

#define	PCS_SCTRL 0x9054UL /* Serialink Control Register */

#define	PCS_SOS 0x9058UL /* Shared Output Select Reg */

#define	PCS_SSTATE 0x905CUL /* Serialink State Register */

#define	PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */

#define	PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */

#define	PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */

#define	PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */

#define	PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */

#define	PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */

#define	PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */

#define	PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */

#define	PCS_MIICTRL_WB

#define	PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */

#define	PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */

#define	PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */

#define	PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */

#define	PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */

#define	PCS_MIISTAT_RF 0x00000010 /* Remote Fault */

#define	PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */

#define	PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */

#define	PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */

#define	PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */

#define	PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */

#define	PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */

#define	PCS_MIIADV_RF 0x00003000 /* Remote Fault */

#define	PCS_MIIADV_ACK 0x00004000 /* Read-only */

#define	PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */

#define	PCS_CFG_ENABLE

#define	PCS_CFG_SDO 0x00000002 /* Signal detect override */

#define	PCS_CFG_SDL 0x00000004 /* Signal detect active low */

#define	PCS_CFG_JS

#define	PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */

#define	PCS_ISTAT_LSC 0x00000004 /* Link Status Change */

#define	PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */

#define	PCS_DMODE_ESM 0x00000002 /* External SERDES mode */

#define	PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */

#define	PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */

#define	PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */

#define	PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */

#define	PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */

#define	PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */

#define	PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */

#define	PCS_SCTRL_PDWN 0x00000200 /* Software power-down */

#define	PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */

#define	PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */

#define	PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */

#define	PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */

#define	PCS_SOS_PADDR 0x00000003 /* PROM Address */

#define	PROM_START 0x100000UL /* Expansion ROM run time access*/

#define	PROM_SIZE 0x0fffffUL /* Size of ROM */

#define	PROM_END 0x200000UL /* End of ROM */

#define	BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */

#define	LPA_PAUSE 0x0400

#define	MII_BCM5201_INTERRUPT 0x1A

#define	MII_BCM5201_INTERRUPT_INTENABLE 0x4000

#define	MII_BCM5201_AUXMODE2 0x1B

#define	MII_BCM5201_AUXMODE2_LOWPOWER 0x0008

#define	MII_BCM5201_MULTIPHY 0x1E

#define	MII_BCM5201_MULTIPHY_SERIALMODE 0x0002

#define	MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008

#define	MII_BCM5400_GB_CONTROL 0x09

#define	MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200

#define	MII_BCM5400_AUXCONTROL 0x18

#define	MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004

#define	MII_BCM5400_AUXSTATUS 0x19

#define	MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700

#define	MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8

#define	TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */

#define	TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */

#define	TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */

#define	TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */

#define	TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */

#define	TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */

#define	TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */

#define	TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */

#define	RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */

#define	RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */

#define	RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */

#define	RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */

#define	RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */

#define	RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */

#define	RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */

#define	RXDCTRL_FRESH(gp)

#define	TX_RING_SIZE 128

#define	RX_RING_SIZE 128

#define	TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128

#define	RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128

#define	NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))

#define	NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))

#define	TX_BUFFS_AVAIL(GP)

#define	RX_OFFSET 2

#define	RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)

#define	RX_COPY_THRESHOLD 256

#define	INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE

#define	INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE

#define	found_mii_phy(gp)

Enumerations
enum	gem_phy_type { phy_mii_mdio0, phy_mii_mdio1, phy_serialink, phy_serdes }

enum	link_state { link_down = 0, link_aneg, link_force_try, link_force_ret, link_force_ok, link_up, link_down = 0, link_aneg, link_force_try, link_force_ret, link_force_ok, link_up }

Macro Definition Documentation

#define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */

Definition at line 764 of file sungem.h.

#define found_mii_phy ( gp )

Value:

((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \

gp->phy_mii.def && gp->phy_mii.def->ops)

Definition at line 1001 of file sungem.h.

#define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */

Definition at line 19 of file sungem.h.

#define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/

Definition at line 85 of file sungem.h.

#define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */

Definition at line 86 of file sungem.h.

#define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */

Definition at line 84 of file sungem.h.

#define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */

Definition at line 20 of file sungem.h.

#define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */

Definition at line 90 of file sungem.h.

#define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */

Definition at line 89 of file sungem.h.

#define GREG_CFG 0x0004UL /* Configuration Register */

Definition at line 12 of file sungem.h.

#define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */

Definition at line 32 of file sungem.h.

#define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */

Definition at line 28 of file sungem.h.

#define GREG_CFG_RONPAULBIT

Value:

0x00000800 /* Use mem read multiple for PCI read

* after infinite burst (Apple) */

Definition at line 31 of file sungem.h.

#define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */

Definition at line 30 of file sungem.h.

#define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */

Definition at line 29 of file sungem.h.

#define GREG_IACK 0x0014UL /* Interrupt ACK Register */

Definition at line 15 of file sungem.h.

#define GREG_IMASK 0x0010UL /* Interrupt Mask Register */

Definition at line 14 of file sungem.h.

#define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */

Definition at line 18 of file sungem.h.

#define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */

Definition at line 17 of file sungem.h.

#define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */

Definition at line 74 of file sungem.h.

#define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */

Definition at line 75 of file sungem.h.

#define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */

Definition at line 76 of file sungem.h.

#define GREG_SEBSTATE 0x0000UL /* SEB State Register */

Definition at line 11 of file sungem.h.

#define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */

Definition at line 24 of file sungem.h.

#define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */

Definition at line 25 of file sungem.h.

#define GREG_STAT 0x000CUL /* Status Register */

Definition at line 13 of file sungem.h.

#define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */

Definition at line 16 of file sungem.h.

#define GREG_STAT_ABNORMAL

Value:

(GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \
                 GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \
                 GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR)

Definition at line 58 of file sungem.h.

#define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */

Definition at line 52 of file sungem.h.

#define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */

Definition at line 53 of file sungem.h.

#define GREG_STAT_NAPI

Value:

(GREG_STAT_TXALL | GREG_STAT_TXINTME | \

GREG_STAT_RXDONE | GREG_STAT_ABNORMAL)

Definition at line 62 of file sungem.h.

#define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */

Definition at line 54 of file sungem.h.

#define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */

Definition at line 49 of file sungem.h.

#define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */

Definition at line 46 of file sungem.h.

#define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */

Definition at line 51 of file sungem.h.

#define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */

Definition at line 47 of file sungem.h.

#define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */

Definition at line 48 of file sungem.h.

#define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */

Definition at line 44 of file sungem.h.

#define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */

Definition at line 45 of file sungem.h.

#define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */

Definition at line 43 of file sungem.h.

#define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */

Definition at line 50 of file sungem.h.

#define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */

Definition at line 55 of file sungem.h.

#define GREG_STAT_TXNR_SHIFT 19

Definition at line 56 of file sungem.h.

#define GREG_SWRST 0x1010UL /* Software Reset Register */

Definition at line 21 of file sungem.h.

#define GREG_SWRST_CACHE_SHIFT 16

Definition at line 103 of file sungem.h.

#define GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */

Definition at line 102 of file sungem.h.

#define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */

Definition at line 101 of file sungem.h.

#define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */

Definition at line 100 of file sungem.h.

#define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */

Definition at line 99 of file sungem.h.

#define INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE

Definition at line 928 of file sungem.h.

#define INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE

Definition at line 922 of file sungem.h.

#define LPA_PAUSE 0x0400

Definition at line 765 of file sungem.h.

#define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */

Definition at line 315 of file sungem.h.

#define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */

Definition at line 316 of file sungem.h.

#define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */

Definition at line 317 of file sungem.h.

#define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */

Definition at line 318 of file sungem.h.

#define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */

Definition at line 319 of file sungem.h.

#define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */

Definition at line 320 of file sungem.h.

#define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */

Definition at line 321 of file sungem.h.

#define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */

Definition at line 322 of file sungem.h.

#define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */

Definition at line 323 of file sungem.h.

#define MAC_AERR 0x6120UL /* Alignment Error Counter */

Definition at line 353 of file sungem.h.

#define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */

Definition at line 328 of file sungem.h.

#define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */

Definition at line 327 of file sungem.h.

#define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */

Definition at line 324 of file sungem.h.

#define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */

Definition at line 325 of file sungem.h.

#define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */

Definition at line 326 of file sungem.h.

#define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */

Definition at line 313 of file sungem.h.

#define MAC_CSTAT 0x6018UL /* MAC Control Status Register */

Definition at line 297 of file sungem.h.

#define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */

Definition at line 392 of file sungem.h.

#define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */

Definition at line 390 of file sungem.h.

#define MAC_CSTAT_PS 0x00000002 /* Paused State */

Definition at line 391 of file sungem.h.

#define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */

Definition at line 393 of file sungem.h.

#define MAC_DTIMER 0x6110UL /* Defer Timer */

Definition at line 349 of file sungem.h.

#define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */

Definition at line 347 of file sungem.h.

#define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */

Definition at line 346 of file sungem.h.

#define MAC_FCSERR 0x6124UL /* FCS Error Counter */

Definition at line 354 of file sungem.h.

#define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */

Definition at line 329 of file sungem.h.

#define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */

Definition at line 330 of file sungem.h.

#define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */

Definition at line 339 of file sungem.h.

#define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */

Definition at line 340 of file sungem.h.

#define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */

Definition at line 341 of file sungem.h.

#define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */

Definition at line 342 of file sungem.h.

#define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */

Definition at line 343 of file sungem.h.

#define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */

Definition at line 344 of file sungem.h.

#define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */

Definition at line 331 of file sungem.h.

#define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */

Definition at line 332 of file sungem.h.

#define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */

Definition at line 333 of file sungem.h.

#define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */

Definition at line 334 of file sungem.h.

#define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */

Definition at line 335 of file sungem.h.

#define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */

Definition at line 336 of file sungem.h.

#define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */

Definition at line 337 of file sungem.h.

#define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */

Definition at line 338 of file sungem.h.

#define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */

Definition at line 305 of file sungem.h.

#define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */

Definition at line 306 of file sungem.h.

#define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */

Definition at line 307 of file sungem.h.

#define MAC_JAMSIZE 0x605CUL /* JamSize Register */

Definition at line 312 of file sungem.h.

#define MAC_LCOLL 0x610CUL /* Late Collision Counter */

Definition at line 348 of file sungem.h.

#define MAC_LERR 0x611CUL /* Length Error Counter */

Definition at line 352 of file sungem.h.

#define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */

Definition at line 310 of file sungem.h.

#define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */

Definition at line 512 of file sungem.h.

#define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */

Definition at line 511 of file sungem.h.

#define MAC_MCCFG 0x6038UL /* MAC Control Config Register */

Definition at line 303 of file sungem.h.

#define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */

Definition at line 446 of file sungem.h.

#define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */

Definition at line 445 of file sungem.h.

#define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */

Definition at line 444 of file sungem.h.

#define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */

Definition at line 300 of file sungem.h.

#define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */

Definition at line 314 of file sungem.h.

#define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */

Definition at line 309 of file sungem.h.

#define MAC_NCOLL 0x6100UL /* Normal Collision Counter */

Definition at line 345 of file sungem.h.

#define MAC_PASIZE 0x6058UL /* PA Size Register */

Definition at line 311 of file sungem.h.

#define MAC_PATMPS 0x6114UL /* Peak Attempts Register */

Definition at line 350 of file sungem.h.

#define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */

Definition at line 356 of file sungem.h.

#define MAC_RFCTR 0x6118UL /* Receive Frame Counter */

Definition at line 351 of file sungem.h.

#define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/

Definition at line 302 of file sungem.h.

#define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */

Definition at line 439 of file sungem.h.

#define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */

Definition at line 440 of file sungem.h.

#define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */

Definition at line 433 of file sungem.h.

#define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */

Definition at line 438 of file sungem.h.

#define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */

Definition at line 437 of file sungem.h.

#define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */

Definition at line 436 of file sungem.h.

#define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */

Definition at line 441 of file sungem.h.

#define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */

Definition at line 435 of file sungem.h.

#define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */

Definition at line 434 of file sungem.h.

#define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */

Definition at line 355 of file sungem.h.

#define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */

Definition at line 299 of file sungem.h.

#define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/

Definition at line 293 of file sungem.h.

#define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */

Definition at line 363 of file sungem.h.

#define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */

Definition at line 296 of file sungem.h.

#define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */

Definition at line 384 of file sungem.h.

#define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */

Definition at line 385 of file sungem.h.

#define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */

Definition at line 383 of file sungem.h.

#define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */

Definition at line 386 of file sungem.h.

#define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */

Definition at line 382 of file sungem.h.

#define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */

Definition at line 381 of file sungem.h.

#define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */

Definition at line 387 of file sungem.h.

#define MAC_SMACHINE 0x6134UL /* State Machine Register */

Definition at line 357 of file sungem.h.

#define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */

Definition at line 294 of file sungem.h.

#define MAC_SNDPAUSE_SP

Value:

0x00010000  /* Setting this bit instructs the MAC
                     * to send a Pause Flow Control
                     * frame onto the network.
                     */

Definition at line 367 of file sungem.h.

#define MAC_SNDPAUSE_TS

Value:

0x0000ffff  /* The pause_time operand used in
                     * Send_Pause and flow-control
                     * handshakes.
                     */

Definition at line 366 of file sungem.h.

#define MAC_STIME 0x604CUL /* SlotTime Register */

Definition at line 308 of file sungem.h.

#define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/

Definition at line 301 of file sungem.h.

#define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */

Definition at line 416 of file sungem.h.

#define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */

Definition at line 413 of file sungem.h.

#define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */

Definition at line 415 of file sungem.h.

#define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */

Definition at line 414 of file sungem.h.

#define MAC_TXCFG_NBO 0x00000040 /* No Backoff */

Definition at line 419 of file sungem.h.

#define MAC_TXCFG_NFCS 0x00000100 /* No FCS */

Definition at line 421 of file sungem.h.

#define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */

Definition at line 417 of file sungem.h.

#define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */

Definition at line 418 of file sungem.h.

#define MAC_TXCFG_SD 0x00000080 /* Slow Down */

Definition at line 420 of file sungem.h.

#define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */

Definition at line 422 of file sungem.h.

#define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */

Definition at line 298 of file sungem.h.

#define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/

Definition at line 292 of file sungem.h.

#define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */

Definition at line 360 of file sungem.h.

#define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */

Definition at line 295 of file sungem.h.

#define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */

Definition at line 377 of file sungem.h.

#define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */

Definition at line 374 of file sungem.h.

#define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */

Definition at line 376 of file sungem.h.

#define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */

Definition at line 375 of file sungem.h.

#define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */

Definition at line 372 of file sungem.h.

#define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */

Definition at line 373 of file sungem.h.

#define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */

Definition at line 378 of file sungem.h.

#define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */

Definition at line 371 of file sungem.h.

#define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */

Definition at line 370 of file sungem.h.

#define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */

Definition at line 304 of file sungem.h.

#define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */

Definition at line 455 of file sungem.h.

#define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */

Definition at line 459 of file sungem.h.

#define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */

Definition at line 456 of file sungem.h.

#define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */

Definition at line 454 of file sungem.h.

#define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */

Definition at line 458 of file sungem.h.

#define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */

Definition at line 457 of file sungem.h.

#define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */

Definition at line 453 of file sungem.h.

#define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */

Definition at line 597 of file sungem.h.

#define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */

Definition at line 598 of file sungem.h.

#define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */

Definition at line 599 of file sungem.h.

#define MIF_CFG 0x6210UL /* MIF Configuration Register */

Definition at line 601 of file sungem.h.

#define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */

Definition at line 637 of file sungem.h.

#define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */

Definition at line 639 of file sungem.h.

#define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */

Definition at line 640 of file sungem.h.

#define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */

Definition at line 636 of file sungem.h.

#define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */

Definition at line 641 of file sungem.h.

#define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */

Definition at line 638 of file sungem.h.

#define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */

Definition at line 635 of file sungem.h.

#define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */

Definition at line 600 of file sungem.h.

#define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */

Definition at line 656 of file sungem.h.

#define MIF_FRAME_OP 0x30000000 /* OPcode */

Definition at line 651 of file sungem.h.

#define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */

Definition at line 652 of file sungem.h.

#define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */

Definition at line 653 of file sungem.h.

#define MIF_FRAME_ST 0xc0000000 /* STart of frame */

Definition at line 650 of file sungem.h.

#define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */

Definition at line 655 of file sungem.h.

#define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */

Definition at line 654 of file sungem.h.

#define MIF_MASK 0x6214UL /* MIF Mask Register */

Definition at line 602 of file sungem.h.

#define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */

Definition at line 604 of file sungem.h.

#define MIF_STATUS 0x6218UL /* MIF Status Register */

Definition at line 603 of file sungem.h.

#define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */

Definition at line 662 of file sungem.h.

#define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */

Definition at line 663 of file sungem.h.

#define MII_BCM5201_AUXMODE2 0x1B

Definition at line 773 of file sungem.h.

#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008

Definition at line 774 of file sungem.h.

#define MII_BCM5201_INTERRUPT 0x1A

Definition at line 770 of file sungem.h.

#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000

Definition at line 771 of file sungem.h.

#define MII_BCM5201_MULTIPHY 0x1E

Definition at line 776 of file sungem.h.

#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002

Definition at line 779 of file sungem.h.

#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008

Definition at line 780 of file sungem.h.

#define MII_BCM5400_AUXCONTROL 0x18

Definition at line 787 of file sungem.h.

#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004

Definition at line 788 of file sungem.h.

#define MII_BCM5400_AUXSTATUS 0x19

Definition at line 791 of file sungem.h.

#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700

Definition at line 792 of file sungem.h.

#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8

Definition at line 793 of file sungem.h.

#define MII_BCM5400_GB_CONTROL 0x09

Definition at line 783 of file sungem.h.

#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200

Definition at line 784 of file sungem.h.

#define NEXT_RX ( N ) (((N) + 1) & (RX_RING_SIZE - 1))

Definition at line 907 of file sungem.h.

#define NEXT_TX ( N ) (((N) + 1) & (TX_RING_SIZE - 1))

Definition at line 906 of file sungem.h.

#define PCS_CFG 0x9010UL /* PCS Configuration Register */

Definition at line 675 of file sungem.h.

#define PCS_CFG_ENABLE

Value:

0x00000001  /* Must be zero while changing
                     * PCS MII advertisement reg.
                     */

Definition at line 719 of file sungem.h.

#define PCS_CFG_JS

Value:

0x00000018  /* Jitter-study:
                     * 0 = normal operation
                     * 1 = high-frequency test pattern
                     * 2 = low-frequency test pattern
                     * 3 = reserved
                     */

Definition at line 722 of file sungem.h.

#define PCS_CFG_SDL 0x00000004 /* Signal detect active low */

Definition at line 721 of file sungem.h.

#define PCS_CFG_SDO 0x00000002 /* Signal detect override */

Definition at line 720 of file sungem.h.

#define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */

Definition at line 723 of file sungem.h.

#define PCS_DMODE 0x9050UL /* Datapath Mode Register */

Definition at line 678 of file sungem.h.

#define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */

Definition at line 732 of file sungem.h.

#define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */

Definition at line 734 of file sungem.h.

#define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */

Definition at line 733 of file sungem.h.

#define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */

Definition at line 731 of file sungem.h.

#define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */

Definition at line 677 of file sungem.h.

#define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */

Definition at line 728 of file sungem.h.

#define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */

Definition at line 673 of file sungem.h.

#define PCS_MIIADV_ACK 0x00004000 /* Read-only */

Definition at line 710 of file sungem.h.

#define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */

Definition at line 708 of file sungem.h.

#define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */

Definition at line 705 of file sungem.h.

#define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */

Definition at line 706 of file sungem.h.

#define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */

Definition at line 711 of file sungem.h.

#define PCS_MIIADV_RF 0x00003000 /* Remote Fault */

Definition at line 709 of file sungem.h.

#define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */

Definition at line 707 of file sungem.h.

#define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */

Definition at line 671 of file sungem.h.

#define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */

Definition at line 690 of file sungem.h.

#define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */

Definition at line 685 of file sungem.h.

#define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */

Definition at line 686 of file sungem.h.

#define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */

Definition at line 688 of file sungem.h.

#define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */

Definition at line 689 of file sungem.h.

#define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */

Definition at line 687 of file sungem.h.

#define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */

Definition at line 693 of file sungem.h.

#define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */

Definition at line 684 of file sungem.h.

#define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */

Definition at line 691 of file sungem.h.

#define PCS_MIICTRL_WB

Value:

0x00004000  /* Wrapback, loopback at 10-bit
                     * input side of Serialink
                     */

Definition at line 692 of file sungem.h.

#define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */

Definition at line 674 of file sungem.h.

#define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */

Definition at line 672 of file sungem.h.

#define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */

Definition at line 699 of file sungem.h.

#define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */

Definition at line 701 of file sungem.h.

#define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */

Definition at line 696 of file sungem.h.

#define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */

Definition at line 702 of file sungem.h.

#define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */

Definition at line 697 of file sungem.h.

#define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */

Definition at line 698 of file sungem.h.

#define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */

Definition at line 700 of file sungem.h.

#define PCS_SCTRL 0x9054UL /* Serialink Control Register */

Definition at line 679 of file sungem.h.

#define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */

Definition at line 743 of file sungem.h.

#define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */

Definition at line 741 of file sungem.h.

#define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */

Definition at line 742 of file sungem.h.

#define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */

Definition at line 740 of file sungem.h.

#define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */

Definition at line 745 of file sungem.h.

#define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */

Definition at line 747 of file sungem.h.

#define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */

Definition at line 746 of file sungem.h.

#define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */

Definition at line 744 of file sungem.h.

#define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */

Definition at line 749 of file sungem.h.

#define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */

Definition at line 748 of file sungem.h.

#define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */

Definition at line 676 of file sungem.h.

#define PCS_SOS 0x9058UL /* Shared Output Select Reg */

Definition at line 680 of file sungem.h.

#define PCS_SOS_PADDR 0x00000003 /* PROM Address */

Definition at line 755 of file sungem.h.

#define PCS_SSTATE 0x905CUL /* Serialink State Register */

Definition at line 681 of file sungem.h.

#define PROM_END 0x200000UL /* End of ROM */

Definition at line 760 of file sungem.h.

#define PROM_SIZE 0x0fffffUL /* Size of ROM */

Definition at line 759 of file sungem.h.

#define PROM_START 0x100000UL /* Expansion ROM run time access*/

Definition at line 758 of file sungem.h.

#define RX_BUF_ALLOC_SIZE ( gp ) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)

Definition at line 915 of file sungem.h.

#define RX_COPY_THRESHOLD 256

Definition at line 917 of file sungem.h.

#define RX_OFFSET 2

Definition at line 914 of file sungem.h.

#define RX_RING_SIZE 128

Definition at line 860 of file sungem.h.

#define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */

Definition at line 852 of file sungem.h.

#define RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */

Definition at line 853 of file sungem.h.

#define RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */

Definition at line 848 of file sungem.h.

#define RXDCTRL_FRESH ( gp )

Value:

((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \

RXDCTRL_OWN)

Definition at line 855 of file sungem.h.

#define RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */

Definition at line 850 of file sungem.h.

#define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */

Definition at line 851 of file sungem.h.

#define RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */

Definition at line 849 of file sungem.h.

#define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */

Definition at line 847 of file sungem.h.

#define RXDMA_BLANK 0x4108UL /* RX Blanking Register */

Definition at line 207 of file sungem.h.

#define RXDMA_BLANK_IPKTS

Value:

0x000001ff  /* RX_DONE asserted after this
                         * many packets received since
                         * previous RX_DONE.
                         */

Definition at line 277 of file sungem.h.

#define RXDMA_BLANK_ITIME

Value:

0x000ff000  /* RX_DONE asserted after this
                         * many clocks (measured in 2048
                         * PCI clocks) were counted since
                         * the previous RX_DONE.
                         */

Definition at line 278 of file sungem.h.

#define RXDMA_CFG 0x4000UL /* RX Configuration Register */

Definition at line 194 of file sungem.h.

#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128

Definition at line 889 of file sungem.h.

#define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */

Definition at line 229 of file sungem.h.

#define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */

Definition at line 216 of file sungem.h.

#define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */

Definition at line 228 of file sungem.h.

#define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */

Definition at line 230 of file sungem.h.

#define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */

Definition at line 232 of file sungem.h.

#define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */

Definition at line 235 of file sungem.h.

#define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */

Definition at line 233 of file sungem.h.

#define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */

Definition at line 236 of file sungem.h.

#define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */

Definition at line 234 of file sungem.h.

#define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */

Definition at line 231 of file sungem.h.

#define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */

Definition at line 217 of file sungem.h.

#define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */

Definition at line 220 of file sungem.h.

#define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */

Definition at line 223 of file sungem.h.

#define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */

Definition at line 221 of file sungem.h.

#define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */

Definition at line 224 of file sungem.h.

#define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */

Definition at line 218 of file sungem.h.

#define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */

Definition at line 225 of file sungem.h.

#define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */

Definition at line 222 of file sungem.h.

#define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */

Definition at line 219 of file sungem.h.

#define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */

Definition at line 226 of file sungem.h.

#define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */

Definition at line 227 of file sungem.h.

#define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */

Definition at line 196 of file sungem.h.

#define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */

Definition at line 195 of file sungem.h.

#define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */

Definition at line 212 of file sungem.h.

#define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */

Definition at line 211 of file sungem.h.

#define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */

Definition at line 210 of file sungem.h.

#define RXDMA_DONE 0x4104UL /* RX Completion Register */

Definition at line 206 of file sungem.h.

#define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */

Definition at line 204 of file sungem.h.

#define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */

Definition at line 203 of file sungem.h.

#define RXDMA_FADDR 0x410CUL /* RX FIFO Address */

Definition at line 208 of file sungem.h.

#define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */

Definition at line 199 of file sungem.h.

#define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */

Definition at line 198 of file sungem.h.

#define RXDMA_FSZ 0x4120UL /* RX FIFO Size */

Definition at line 213 of file sungem.h.

#define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */

Definition at line 209 of file sungem.h.

#define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */

Definition at line 197 of file sungem.h.

#define RXDMA_KICK 0x4100UL /* RX Kick Register */

Definition at line 205 of file sungem.h.

#define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */

Definition at line 200 of file sungem.h.

#define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */

Definition at line 202 of file sungem.h.

#define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */

Definition at line 250 of file sungem.h.

#define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */

Definition at line 251 of file sungem.h.

#define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */

Definition at line 201 of file sungem.h.

#define TX_BUFFS_AVAIL ( GP )

Value:

(((GP)->tx_old <= (GP)->tx_new) ?           \
      (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new :    \
      (GP)->tx_old - (GP)->tx_new - 1)

Definition at line 909 of file sungem.h.

#define TX_RING_SIZE 128

Definition at line 859 of file sungem.h.

#define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */

Definition at line 812 of file sungem.h.

#define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */

Definition at line 815 of file sungem.h.

#define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */

Definition at line 814 of file sungem.h.

#define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */

Definition at line 813 of file sungem.h.

#define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */

Definition at line 816 of file sungem.h.

#define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */

Definition at line 818 of file sungem.h.

#define TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */

Definition at line 819 of file sungem.h.

#define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */

Definition at line 817 of file sungem.h.

#define TXDMA_CFG 0x2004UL /* TX Configuration Register */

Definition at line 107 of file sungem.h.

#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128

Definition at line 867 of file sungem.h.

#define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */

Definition at line 146 of file sungem.h.

#define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */

Definition at line 158 of file sungem.h.

#define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */

Definition at line 157 of file sungem.h.

#define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/

Definition at line 159 of file sungem.h.

#define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */

Definition at line 147 of file sungem.h.

#define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */

Definition at line 150 of file sungem.h.

#define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */

Definition at line 153 of file sungem.h.

#define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */

Definition at line 151 of file sungem.h.

#define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */

Definition at line 154 of file sungem.h.

#define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */

Definition at line 148 of file sungem.h.

#define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */

Definition at line 155 of file sungem.h.

#define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */

Definition at line 152 of file sungem.h.

#define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */

Definition at line 149 of file sungem.h.

#define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */

Definition at line 156 of file sungem.h.

#define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */

Definition at line 109 of file sungem.h.

#define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */

Definition at line 108 of file sungem.h.

#define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */

Definition at line 123 of file sungem.h.

#define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */

Definition at line 122 of file sungem.h.

#define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */

Definition at line 121 of file sungem.h.

#define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */

Definition at line 117 of file sungem.h.

#define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */

Definition at line 116 of file sungem.h.

#define TXDMA_FADDR 0x2104UL /* TX FIFO Address */

Definition at line 119 of file sungem.h.

#define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */

Definition at line 112 of file sungem.h.

#define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */

Definition at line 113 of file sungem.h.

#define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */

Definition at line 111 of file sungem.h.

#define TXDMA_FSZ 0x2118UL /* TX FIFO Size */

Definition at line 124 of file sungem.h.

#define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */

Definition at line 120 of file sungem.h.

#define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */

Definition at line 110 of file sungem.h.

#define TXDMA_KICK 0x2000UL /* TX Kick Register */

Definition at line 106 of file sungem.h.

#define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */

Definition at line 114 of file sungem.h.

#define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */

Definition at line 115 of file sungem.h.

#define TXDMA_TXDONE 0x2100UL /* TX Completion Register */

Definition at line 118 of file sungem.h.

#define WOL_MATCH0 0x3000UL

Definition at line 173 of file sungem.h.

#define WOL_MATCH1 0x3004UL

Definition at line 174 of file sungem.h.

#define WOL_MATCH2 0x3008UL

Definition at line 175 of file sungem.h.

#define WOL_MCOUNT 0x300CUL

Definition at line 176 of file sungem.h.

#define WOL_MCOUNT_M 0x00000000 /* 0 << 8 */

Definition at line 182 of file sungem.h.

#define WOL_MCOUNT_N 0x00000010

Definition at line 181 of file sungem.h.

#define WOL_WAKECSR 0x3010UL

Definition at line 177 of file sungem.h.

#define WOL_WAKECSR_ENABLE 0x00000001

Definition at line 184 of file sungem.h.

#define WOL_WAKECSR_FILT_BCAST 0x00000020

Definition at line 189 of file sungem.h.

#define WOL_WAKECSR_FILT_MCAST 0x00000010

Definition at line 188 of file sungem.h.

#define WOL_WAKECSR_FILT_SEEN 0x00000040

Definition at line 190 of file sungem.h.

#define WOL_WAKECSR_FILT_UCAST 0x00000008

Definition at line 187 of file sungem.h.

#define WOL_WAKECSR_MII 0x00000002

Definition at line 185 of file sungem.h.

#define WOL_WAKECSR_SEEN 0x00000004

Definition at line 186 of file sungem.h.

Enumeration Type Documentation

enum gem_phy_type

Enumerator:

phy_mii_mdio0
phy_mii_mdio1
phy_serialink
phy_serdes

Definition at line 936 of file sungem.h.

enum link_state

Enumerator:

link_down
link_aneg
link_force_try
link_force_ret
link_force_ok
link_up
link_down
link_aneg
link_force_try
link_force_ret
link_force_ok
link_up

Definition at line 943 of file sungem.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation