29 #include <linux/errno.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/string.h>
34 #include <linux/slab.h>
36 #include <asm/div64.h>
41 #define REG0_INIT_VAL 0x23
68 struct i2c_msg msg [] = { { .
addr = state->
config->demod_address, .flags = 0, .buf = b0, .len = 1 },
69 { .addr = state->
config->demod_address, .flags =
I2C_M_RD, .buf = b1, .len = 1 } };
76 "(reg == 0x%02x, ret == %i)\n",
77 num, __func__, reg, ret);
85 struct i2c_msg msg = { .addr = state->
config->demod_address, .flags = 0, .buf =
buf, .len = 2 };
92 "(reg == 0x%02x, val == 0x%02x, ret == %i)\n",
93 num, __func__, reg, data, ret);
102 return tda10023_writereg(state, reg, data);
105 val=tda10023_readreg(state,reg);
108 return tda10023_writereg(state, reg, val);
126 tda10023_writebit(state,r,m,v);
133 u8 buf[2] = { 0x0f, 0xc0 };
138 printk(
"tda10023: lock tuner fails\n");
147 u8 buf[2] = { 0x0f, 0x40 };
152 printk(
"tda10023: unlock tuner fails\n");
160 reg0 |= state->
reg0 & 0x63;
162 tda10023_writereg (state, 0x00, reg0 & 0xfe);
163 tda10023_writereg (state, 0x00, reg0 | 0x01);
180 if (sr < (
u32)(sysclk_x_10/984)) {
183 }
else if (sr < (
u32)(sysclk_x_10/640)) {
186 }
else if (sr < (
u32)(sysclk_x_10/492)) {
189 }
else if (sr < (
u32)(sysclk_x_10/320)) {
192 }
else if (sr < (
u32)(sysclk_x_10/246)) {
195 }
else if (sr < (
u32)(sysclk_x_10/160)) {
198 }
else if (sr < (
u32)(sysclk_x_10/123)) {
203 BDRI = (state->
sysclk)*16;
220 dprintk(
"Symbolrate %i, BDR %i BDRI %i, NDEC %i\n",
221 sr, BDR, BDRI, NDEC);
222 tda10023_writebit (state, 0x03, 0xc0, NDEC<<6);
223 tda10023_writereg (state, 0x0a, BDR&255);
224 tda10023_writereg (state, 0x0b, (BDR>>8)&255);
225 tda10023_writereg (state, 0x0c, (BDR>>16)&31);
226 tda10023_writereg (state, 0x0d, BDRI);
227 tda10023_writereg (state, 0x3d, (SFIL<<7));
234 u8 tda10023_inittab[] = {
241 0x28, 0xff, (state->
pll_m-1),
243 0x29, 0xff, ((state->
pll_p-1)<<6)|(state->
pll_n-1),
285 dprintk(
"DVB: TDA10023(%d): init chip\n", fe->
dvb->num);
288 if (state->
config->deltaf) {
289 tda10023_inittab[80] = (state->
config->deltaf & 0xff);
290 tda10023_inittab[83] = (state->
config->deltaf >> 8);
293 if (state->
config->output_mode)
294 tda10023_inittab[95] = state->
config->output_mode;
296 tda10023_writetab(state, tda10023_inittab);
305 static int tda10023_set_parameters(
struct dvb_frontend *fe)
312 static const struct qam_params qam_params[] = {
314 [
QPSK] = { (5<<2), 0x78, 0x8c, 0x96, 0x78, 0x4c },
315 [
QAM_16] = { (0<<2), 0x87, 0xa2, 0x91, 0x8c, 0x57 },
316 [
QAM_32] = { (1<<2), 0x64, 0x74, 0x96, 0x8c, 0x57 },
317 [
QAM_64] = { (2<<2), 0x46, 0x43, 0x6a, 0x6a, 0x44 },
318 [
QAM_128] = { (3<<2), 0x36, 0x34, 0x7e, 0x78, 0x4c },
319 [
QAM_256] = { (4<<2), 0x26, 0x23, 0x6c, 0x5c, 0x3c },
352 if (fe->
ops.tuner_ops.set_params) {
353 fe->
ops.tuner_ops.set_params(fe);
354 if (fe->
ops.i2c_gate_ctrl) fe->
ops.i2c_gate_ctrl(fe, 0);
358 tda10023_writereg(state, 0x05, qam_params[qam].
lockthr);
359 tda10023_writereg(state, 0x08, qam_params[qam].
mseth);
360 tda10023_writereg(state, 0x09, qam_params[qam].
aref);
361 tda10023_writereg(state, 0xb4, qam_params[qam].
agcrefnyq);
362 tda10023_writereg(state, 0xb6, qam_params[qam].
eragnyq_thd);
364 tda10023_writereg(state, 0x04, (c->
inversion ? 0x12 : 0x32));
365 tda10023_writebit(state, 0x04, 0x60, (c->
inversion ? 0 : 0x20));
367 tda10023_writebit(state, 0x04, 0x40, 0x40);
370 tda10023_writebit(state, 0x3d, 0xfc, 0x03);
372 tda10023_writebit(state, 0x3d, 0xfc, 0x02);
374 tda10023_setup_reg0(state, qam_params[qam].qam);
390 sync = tda10023_readreg (state, 0x11);
408 a=tda10023_readreg(state, 0x14);
409 b=tda10023_readreg(state, 0x15);
410 c=tda10023_readreg(state, 0x16)&0xf;
411 tda10023_writebit (state, 0x10, 0xc0, 0x00);
413 *ber = a | (b<<8)| (c<<16);
417 static int tda10023_read_signal_strength(
struct dvb_frontend* fe,
u16* strength)
420 u8 ifgain=tda10023_readreg(state, 0x2f);
422 u16 gain = ((255-tda10023_readreg(state, 0x17))) + (255-ifgain)/16;
425 gain=gain+2*(gain-0x90);
429 *strength = (gain<<8)|gain;
437 u8 quality = ~tda10023_readreg(state, 0x18);
438 *snr = (quality << 8) | quality;
442 static int tda10023_read_ucblocks(
struct dvb_frontend* fe,
u32* ucblocks)
446 a= tda10023_readreg (state, 0x74);
447 b= tda10023_readreg (state, 0x75);
448 c= tda10023_readreg (state, 0x76);
449 d= tda10023_readreg (state, 0x77);
450 *ucblocks = a | (b<<8)|(c<<16)|(d<<24);
452 tda10023_writebit (state, 0x10, 0x20,0x00);
453 tda10023_writebit (state, 0x10, 0x20,0x20);
454 tda10023_writebit (state, 0x13, 0x01, 0x00);
459 static int tda10023_get_frontend(
struct dvb_frontend *fe)
466 sync = tda10023_readreg(state, 0x11);
467 afc = tda10023_readreg(state, 0x19);
468 inv = tda10023_readreg(state, 0x04);
472 printk(sync & 2 ?
"DVB: TDA10023(%d): AFC (%d) %dHz\n" :
473 "DVB: TDA10023(%d): [AFC (%d) %dHz]\n",
494 tda10023_writereg (state, 0x1b, 0x02);
495 tda10023_writereg (state, 0x00, 0x80);
535 tda10023_writereg (state, 0x00, 0x33);
537 if ((tda10023_readreg(state, 0x1a) & 0xf0) != 0x70)
goto error;
543 if (state->
config->xtal) {
550 state->
xtal = 28920000;
563 dprintk(
"DVB: TDA10023 %s: xtal:%d pll_m:%d pll_p:%d pll_n:%d\n",
578 .name =
"Philips TDA10023 DVB-C",
579 .frequency_stepsize = 62500,
580 .frequency_min = 47000000,
581 .frequency_max = 862000000,
582 .symbol_rate_min = 0,
583 .symbol_rate_max = 0,
590 .release = tda10023_release,
592 .init = tda10023_init,
593 .sleep = tda10023_sleep,
594 .i2c_gate_ctrl = tda10023_i2c_gate_ctrl,
596 .set_frontend = tda10023_set_parameters,
597 .get_frontend = tda10023_get_frontend,
598 .read_status = tda10023_read_status,
599 .read_ber = tda10023_read_ber,
600 .read_signal_strength = tda10023_read_signal_strength,
601 .read_snr = tda10023_read_snr,
602 .read_ucblocks = tda10023_read_ucblocks,