#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <mach/iomap.h>
#include "clock.h"
#include "fuse.h"
#include "tegra2_emc.h"
#include "tegra_cpu_car.h"

Macros
#define	RST_DEVICES 0x004

#define	RST_DEVICES_SET 0x300

#define	RST_DEVICES_CLR 0x304

#define	RST_DEVICES_NUM 3

#define	CLK_OUT_ENB 0x010

#define	CLK_OUT_ENB_SET 0x320

#define	CLK_OUT_ENB_CLR 0x324

#define	CLK_OUT_ENB_NUM 3

#define	CLK_MASK_ARM 0x44

#define	MISC_CLK_ENB 0x48

#define	OSC_CTRL 0x50

#define	OSC_CTRL_OSC_FREQ_MASK (3<<30)

#define	OSC_CTRL_OSC_FREQ_13MHZ (0<<30)

#define	OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)

#define	OSC_CTRL_OSC_FREQ_12MHZ (2<<30)

#define	OSC_CTRL_OSC_FREQ_26MHZ (3<<30)

#define	OSC_CTRL_MASK (0x3f2 \| OSC_CTRL_OSC_FREQ_MASK)

#define	OSC_FREQ_DET 0x58

#define	OSC_FREQ_DET_TRIG (1<<31)

#define	OSC_FREQ_DET_STATUS 0x5C

#define	OSC_FREQ_DET_BUSY (1<<31)

#define	OSC_FREQ_DET_CNT_MASK 0xFFFF

#define	PERIPH_CLK_SOURCE_I2S1 0x100

#define	PERIPH_CLK_SOURCE_EMC 0x19c

#define	PERIPH_CLK_SOURCE_OSC 0x1fc

#define	PERIPH_CLK_SOURCE_NUM ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)

#define	PERIPH_CLK_SOURCE_MASK (3<<30)

#define	PERIPH_CLK_SOURCE_SHIFT 30

#define	PERIPH_CLK_SOURCE_PWM_MASK (7<<28)

#define	PERIPH_CLK_SOURCE_PWM_SHIFT 28

#define	PERIPH_CLK_SOURCE_ENABLE (1<<28)

#define	PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF

#define	PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF

#define	PERIPH_CLK_SOURCE_DIV_SHIFT 0

#define	SDMMC_CLK_INT_FB_SEL (1 << 23)

#define	SDMMC_CLK_INT_FB_DLY_SHIFT 16

#define	SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)

#define	PLL_BASE 0x0

#define	PLL_BASE_BYPASS (1<<31)

#define	PLL_BASE_ENABLE (1<<30)

#define	PLL_BASE_REF_ENABLE (1<<29)

#define	PLL_BASE_OVERRIDE (1<<28)

#define	PLL_BASE_DIVP_MASK (0x7<<20)

#define	PLL_BASE_DIVP_SHIFT 20

#define	PLL_BASE_DIVN_MASK (0x3FF<<8)

#define	PLL_BASE_DIVN_SHIFT 8

#define	PLL_BASE_DIVM_MASK (0x1F)

#define	PLL_BASE_DIVM_SHIFT 0

#define	PLL_OUT_RATIO_MASK (0xFF<<8)

#define	PLL_OUT_RATIO_SHIFT 8

#define	PLL_OUT_OVERRIDE (1<<2)

#define	PLL_OUT_CLKEN (1<<1)

#define	PLL_OUT_RESET_DISABLE (1<<0)

#define	PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)

#define	PLL_MISC_DCCON_SHIFT 20

#define	PLL_MISC_CPCON_SHIFT 8

#define	PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)

#define	PLL_MISC_LFCON_SHIFT 4

#define	PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)

#define	PLL_MISC_VCOCON_SHIFT 0

#define	PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)

#define	PLLU_BASE_POST_DIV (1<<20)

#define	PLLD_MISC_CLKENABLE (1<<30)

#define	PLLD_MISC_DIV_RST (1<<23)

#define	PLLD_MISC_DCCON_SHIFT 12

#define	PLLE_MISC_READY (1 << 15)

#define	PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)

#define	PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)

#define	PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))

#define	SUPER_CLK_MUX 0x00

#define	SUPER_STATE_SHIFT 28

#define	SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)

#define	SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)

#define	SUPER_SOURCE_MASK 0xF

#define	SUPER_FIQ_SOURCE_SHIFT 12

#define	SUPER_IRQ_SOURCE_SHIFT 8

#define	SUPER_RUN_SOURCE_SHIFT 4

#define	SUPER_IDLE_SOURCE_SHIFT 0

#define	SUPER_CLK_DIVIDER 0x04

#define	BUS_CLK_DISABLE (1<<3)

#define	BUS_CLK_DIV_MASK 0x3

#define	PMC_CTRL 0x0

#define	PMC_CTRL_BLINK_ENB (1 << 7)

#define	PMC_DPD_PADS_ORIDE 0x1c

#define	PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)

#define	PMC_BLINK_TIMER_DATA_ON_SHIFT 0

#define	PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff

#define	PMC_BLINK_TIMER_ENB (1 << 15)

#define	PMC_BLINK_TIMER_DATA_OFF_SHIFT 16

#define	PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff

#define	TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c

#define	TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340

#define	TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344

#define	CPU_CLOCK(cpu) (0x1 << (8 + cpu))

#define	CPU_RESET(cpu) (0x1111ul << (cpu))

#define	clk_writel(value, reg) __raw_writel(value, reg_clk_base + (reg))

#define	clk_readl(reg) __raw_readl(reg_clk_base + (reg))

#define	pmc_writel(value, reg) __raw_writel(value, reg_pmc_base + (reg))

#define	pmc_readl(reg) __raw_readl(reg_pmc_base + (reg))

Functions
void	tegra2_cop_clk_reset (struct clk_hw *hw, bool assert)

void	tegra2_periph_clk_reset (struct clk_hw *hw, bool assert)

void __init	tegra20_cpu_car_ops_init (void)

Macro Definition Documentation

#define BUS_CLK_DISABLE (1<<3)

Definition at line 140 of file tegra20_clocks.c.

#define BUS_CLK_DIV_MASK 0x3

Definition at line 141 of file tegra20_clocks.c.

#define CLK_MASK_ARM 0x44

Definition at line 47 of file tegra20_clocks.c.

#define CLK_OUT_ENB 0x010

Definition at line 42 of file tegra20_clocks.c.

#define CLK_OUT_ENB_CLR 0x324

Definition at line 44 of file tegra20_clocks.c.

#define CLK_OUT_ENB_NUM 3

Definition at line 45 of file tegra20_clocks.c.

#define CLK_OUT_ENB_SET 0x320

Definition at line 43 of file tegra20_clocks.c.

#define clk_readl ( reg ) __raw_readl(reg_clk_base + (reg))

Definition at line 181 of file tegra20_clocks.c.

#define clk_writel	(	value,
		reg
	)	__raw_writel(value, reg_clk_base + (reg))

Definition at line 179 of file tegra20_clocks.c.

#define CPU_CLOCK ( cpu ) (0x1 << (8 + cpu))

Definition at line 160 of file tegra20_clocks.c.

#define CPU_RESET ( cpu ) (0x1111ul << (cpu))

Definition at line 161 of file tegra20_clocks.c.

#define MISC_CLK_ENB 0x48

Definition at line 48 of file tegra20_clocks.c.

#define OSC_CTRL 0x50

Definition at line 50 of file tegra20_clocks.c.

#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)

Definition at line 56 of file tegra20_clocks.c.

#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)

Definition at line 54 of file tegra20_clocks.c.

#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)

Definition at line 52 of file tegra20_clocks.c.

#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)

Definition at line 53 of file tegra20_clocks.c.

#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)

Definition at line 55 of file tegra20_clocks.c.

#define OSC_CTRL_OSC_FREQ_MASK (3<<30)

Definition at line 51 of file tegra20_clocks.c.

#define OSC_FREQ_DET 0x58

Definition at line 58 of file tegra20_clocks.c.

#define OSC_FREQ_DET_BUSY (1<<31)

Definition at line 62 of file tegra20_clocks.c.

#define OSC_FREQ_DET_CNT_MASK 0xFFFF

Definition at line 63 of file tegra20_clocks.c.

#define OSC_FREQ_DET_STATUS 0x5C

Definition at line 61 of file tegra20_clocks.c.

#define OSC_FREQ_DET_TRIG (1<<31)

Definition at line 59 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_DIV_SHIFT 0

Definition at line 78 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF

Definition at line 77 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF

Definition at line 76 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_EMC 0x19c

Definition at line 66 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_ENABLE (1<<28)

Definition at line 75 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_I2S1 0x100

Definition at line 65 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_MASK (3<<30)

Definition at line 71 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_NUM ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)

Definition at line 68 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_OSC 0x1fc

Definition at line 67 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)

Definition at line 73 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_PWM_SHIFT 28

Definition at line 74 of file tegra20_clocks.c.

#define PERIPH_CLK_SOURCE_SHIFT 30

Definition at line 72 of file tegra20_clocks.c.

#define PERIPH_CLK_TO_ENB_BIT ( c ) (1 << (c->u.periph.clk_num % 32))

Definition at line 122 of file tegra20_clocks.c.

#define PERIPH_CLK_TO_ENB_REG ( c ) ((c->u.periph.clk_num / 32) * 4)

Definition at line 120 of file tegra20_clocks.c.

#define PERIPH_CLK_TO_ENB_SET_REG ( c ) ((c->u.periph.clk_num / 32) * 8)

Definition at line 121 of file tegra20_clocks.c.

#define PLL_BASE 0x0

Definition at line 84 of file tegra20_clocks.c.

#define PLL_BASE_BYPASS (1<<31)

Definition at line 85 of file tegra20_clocks.c.

#define PLL_BASE_DIVM_MASK (0x1F)

Definition at line 93 of file tegra20_clocks.c.

#define PLL_BASE_DIVM_SHIFT 0

Definition at line 94 of file tegra20_clocks.c.

#define PLL_BASE_DIVN_MASK (0x3FF<<8)

Definition at line 91 of file tegra20_clocks.c.

#define PLL_BASE_DIVN_SHIFT 8

Definition at line 92 of file tegra20_clocks.c.

#define PLL_BASE_DIVP_MASK (0x7<<20)

Definition at line 89 of file tegra20_clocks.c.

#define PLL_BASE_DIVP_SHIFT 20

Definition at line 90 of file tegra20_clocks.c.

#define PLL_BASE_ENABLE (1<<30)

Definition at line 86 of file tegra20_clocks.c.

#define PLL_BASE_OVERRIDE (1<<28)

Definition at line 88 of file tegra20_clocks.c.

#define PLL_BASE_REF_ENABLE (1<<29)

Definition at line 87 of file tegra20_clocks.c.

#define PLL_MISC ( c ) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)

Definition at line 102 of file tegra20_clocks.c.

#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)

Definition at line 106 of file tegra20_clocks.c.

#define PLL_MISC_CPCON_SHIFT 8

Definition at line 105 of file tegra20_clocks.c.

#define PLL_MISC_DCCON_SHIFT 20

Definition at line 104 of file tegra20_clocks.c.

#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)

Definition at line 108 of file tegra20_clocks.c.

#define PLL_MISC_LFCON_SHIFT 4

Definition at line 107 of file tegra20_clocks.c.

#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)

Definition at line 110 of file tegra20_clocks.c.

#define PLL_MISC_VCOCON_SHIFT 0

Definition at line 109 of file tegra20_clocks.c.

#define PLL_OUT_CLKEN (1<<1)

Definition at line 99 of file tegra20_clocks.c.

#define PLL_OUT_OVERRIDE (1<<2)

Definition at line 98 of file tegra20_clocks.c.

#define PLL_OUT_RATIO_MASK (0xFF<<8)

Definition at line 96 of file tegra20_clocks.c.

#define PLL_OUT_RATIO_SHIFT 8

Definition at line 97 of file tegra20_clocks.c.

#define PLL_OUT_RESET_DISABLE (1<<0)

Definition at line 100 of file tegra20_clocks.c.

#define PLLD_MISC_CLKENABLE (1<<30)

Definition at line 114 of file tegra20_clocks.c.

#define PLLD_MISC_DCCON_SHIFT 12

Definition at line 116 of file tegra20_clocks.c.

#define PLLD_MISC_DIV_RST (1<<23)

Definition at line 115 of file tegra20_clocks.c.

#define PLLE_MISC_READY (1 << 15)

Definition at line 118 of file tegra20_clocks.c.

#define PLLU_BASE_POST_DIV (1<<20)

Definition at line 112 of file tegra20_clocks.c.

#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff

Definition at line 153 of file tegra20_clocks.c.

#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16

Definition at line 152 of file tegra20_clocks.c.

#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff

Definition at line 150 of file tegra20_clocks.c.

#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0

Definition at line 149 of file tegra20_clocks.c.

#define PMC_BLINK_TIMER_ENB (1 << 15)

Definition at line 151 of file tegra20_clocks.c.

#define PMC_CTRL 0x0

Definition at line 143 of file tegra20_clocks.c.

#define PMC_CTRL_BLINK_ENB (1 << 7)

Definition at line 144 of file tegra20_clocks.c.

#define PMC_DPD_PADS_ORIDE 0x1c

Definition at line 146 of file tegra20_clocks.c.

#define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)

Definition at line 147 of file tegra20_clocks.c.

#define pmc_readl ( reg ) __raw_readl(reg_pmc_base + (reg))

Definition at line 185 of file tegra20_clocks.c.

#define pmc_writel	(	value,
		reg
	)	__raw_writel(value, reg_pmc_base + (reg))

Definition at line 183 of file tegra20_clocks.c.

#define RST_DEVICES 0x004

Definition at line 37 of file tegra20_clocks.c.

#define RST_DEVICES_CLR 0x304

Definition at line 39 of file tegra20_clocks.c.

#define RST_DEVICES_NUM 3

Definition at line 40 of file tegra20_clocks.c.

#define RST_DEVICES_SET 0x300

Definition at line 38 of file tegra20_clocks.c.

#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)

Definition at line 82 of file tegra20_clocks.c.

#define SDMMC_CLK_INT_FB_DLY_SHIFT 16

Definition at line 81 of file tegra20_clocks.c.

#define SDMMC_CLK_INT_FB_SEL (1 << 23)

Definition at line 80 of file tegra20_clocks.c.

#define SUPER_CLK_DIVIDER 0x04

Definition at line 138 of file tegra20_clocks.c.

#define SUPER_CLK_MUX 0x00

Definition at line 124 of file tegra20_clocks.c.

#define SUPER_FIQ_SOURCE_SHIFT 12

Definition at line 133 of file tegra20_clocks.c.

#define SUPER_IDLE_SOURCE_SHIFT 0

Definition at line 136 of file tegra20_clocks.c.

#define SUPER_IRQ_SOURCE_SHIFT 8

Definition at line 134 of file tegra20_clocks.c.

#define SUPER_RUN_SOURCE_SHIFT 4

Definition at line 135 of file tegra20_clocks.c.

#define SUPER_SOURCE_MASK 0xF

Definition at line 132 of file tegra20_clocks.c.

#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)

Definition at line 131 of file tegra20_clocks.c.

#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)

Definition at line 128 of file tegra20_clocks.c.

#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)

Definition at line 130 of file tegra20_clocks.c.

#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)

Definition at line 126 of file tegra20_clocks.c.

#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)

Definition at line 129 of file tegra20_clocks.c.

#define SUPER_STATE_SHIFT 28

Definition at line 125 of file tegra20_clocks.c.

#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)

Definition at line 127 of file tegra20_clocks.c.

#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c

Definition at line 156 of file tegra20_clocks.c.

#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344

Definition at line 158 of file tegra20_clocks.c.

#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340

Definition at line 157 of file tegra20_clocks.c.

Function Documentation

void __init tegra20_cpu_car_ops_init ( void )

Definition at line 1621 of file tegra20_clocks.c.

void tegra2_cop_clk_reset	(	struct clk_hw *	hw,
		bool	assert
	)

Definition at line 417 of file tegra20_clocks.c.

void tegra2_periph_clk_reset	(	struct clk_hw *	hw,
		bool	assert
	)

Definition at line 1154 of file tegra20_clocks.c.

Variable Documentation

struct clk_ops tegra_audio_sync_clk_ops

Initial value:

= {
    .is_enabled = tegra20_audio_sync_clk_is_enabled,
    .enable = tegra20_audio_sync_clk_enable,
    .disable = tegra20_audio_sync_clk_disable,
    .set_parent = tegra20_audio_sync_clk_set_parent,
    .get_parent = tegra20_audio_sync_clk_get_parent,
}

Definition at line 1508 of file tegra20_clocks.c.

struct clk_ops tegra_blink_clk_ops

Initial value:

= {
    .is_enabled = tegra20_blink_clk_is_enabled,
    .enable = tegra20_blink_clk_enable,
    .disable = tegra20_blink_clk_disable,
    .set_rate = tegra20_blink_clk_set_rate,
    .round_rate = tegra20_blink_clk_round_rate,
    .recalc_rate = tegra20_blink_clk_recalc_rate,
}

Definition at line 663 of file tegra20_clocks.c.

struct clk_ops tegra_bus_ops

Initial value:

= {
    .is_enabled = tegra20_bus_clk_is_enabled,
    .enable = tegra20_bus_clk_enable,
    .disable = tegra20_bus_clk_disable,
    .set_rate = tegra20_bus_clk_set_rate,
    .round_rate = tegra20_bus_clk_round_rate,
    .recalc_rate = tegra20_bus_clk_recalc_rate,
}

Definition at line 537 of file tegra20_clocks.c.

struct clk_ops tegra_cdev_clk_ops

Initial value:

= {
    .is_enabled = tegra20_cdev_clk_is_enabled,
    .enable = tegra20_cdev_clk_enable,
    .disable = tegra20_cdev_clk_disable,
    .recalc_rate = tegra20_cdev_recalc_rate,
}

Definition at line 1558 of file tegra20_clocks.c.

struct clk_ops tegra_clk_32k_ops

Initial value:

= {
    .recalc_rate = tegra_clk_fixed_recalc_rate,
}

Definition at line 248 of file tegra20_clocks.c.

struct clk_ops tegra_clk_double_ops

Initial value:

= {
    .is_enabled = tegra20_clk_double_is_enabled,
    .enable = tegra20_periph_clk_enable,
    .disable = tegra20_periph_clk_disable,
    .set_rate = tegra20_clk_double_set_rate,
    .recalc_rate = tegra20_clk_double_recalc_rate,
    .round_rate = tegra20_clk_double_round_rate,
}

Definition at line 1451 of file tegra20_clocks.c.

struct clk_ops tegra_clk_m_ops

Initial value:

= {
    .init = tegra20_clk_m_init,
    .recalc_rate = tegra20_clk_m_recalc_rate,
}

Definition at line 286 of file tegra20_clocks.c.

struct clk_ops tegra_cop_ops

Initial value:

= {
    .get_parent = tegra20_cop_clk_get_parent,
}

Definition at line 411 of file tegra20_clocks.c.

struct clk_ops tegra_emc_clk_ops

Initial value:

= {
    .init = tegra20_emc_clk_init,
    .is_enabled = tegra20_periph_clk_is_enabled,
    .enable = tegra20_periph_clk_enable,
    .disable = tegra20_periph_clk_disable,
    .set_parent = tegra20_periph_clk_set_parent,
    .get_parent = tegra20_periph_clk_get_parent,
    .set_rate = tegra20_emc_clk_set_rate,
    .round_rate = tegra20_emc_clk_round_rate,
    .recalc_rate = tegra20_periph_clk_recalc_rate,
}

Definition at line 1388 of file tegra20_clocks.c.

struct clk_ops tegra_periph_clk_ops

Initial value:

= {
    .is_enabled = tegra20_periph_clk_is_enabled,
    .enable = tegra20_periph_clk_enable,
    .disable = tegra20_periph_clk_disable,
    .set_parent = tegra20_periph_clk_set_parent,
    .get_parent = tegra20_periph_clk_get_parent,
    .set_rate = tegra20_periph_clk_set_rate,
    .round_rate = tegra20_periph_clk_round_rate,
    .recalc_rate = tegra20_periph_clk_recalc_rate,
}

Definition at line 1314 of file tegra20_clocks.c.

struct clk_ops tegra_pll_div_ops

Initial value:

= {
    .is_enabled = tegra20_pll_div_clk_is_enabled,
    .enable = tegra20_pll_div_clk_enable,
    .disable = tegra20_pll_div_clk_disable,
    .set_rate = tegra20_pll_div_clk_set_rate,
    .round_rate = tegra20_pll_div_clk_round_rate,
    .recalc_rate = tegra20_pll_div_clk_recalc_rate,
}

Definition at line 1063 of file tegra20_clocks.c.

struct clk_ops tegra_pll_ops

Initial value:

= {
    .is_enabled = tegra20_pll_clk_is_enabled,
    .enable = tegra20_pll_clk_enable,
    .disable = tegra20_pll_clk_disable,
    .set_rate = tegra20_pll_clk_set_rate,
    .recalc_rate = tegra20_pll_clk_recalc_rate,
    .round_rate = tegra20_pll_clk_round_rate,
}

Definition at line 843 of file tegra20_clocks.c.

struct clk_ops tegra_plle_ops

Initial value:

= {
    .is_enabled = tegra20_pll_clk_is_enabled,
    .enable = tegra20_plle_clk_enable,
    .set_rate = tegra20_pll_clk_set_rate,
    .recalc_rate = tegra20_pll_clk_recalc_rate,
    .round_rate = tegra20_pll_clk_round_rate,
}

Definition at line 890 of file tegra20_clocks.c.

struct clk_ops tegra_pllx_ops

Initial value:

= {
    .init = tegra20_pllx_clk_init,
    .is_enabled = tegra20_pll_clk_is_enabled,
    .enable = tegra20_pll_clk_enable,
    .disable = tegra20_pll_clk_disable,
    .set_rate = tegra20_pll_clk_set_rate,
    .recalc_rate = tegra20_pll_clk_recalc_rate,
    .round_rate = tegra20_pll_clk_round_rate,
}

Definition at line 860 of file tegra20_clocks.c.

struct clk_ops tegra_super_ops

Initial value:

= {
    .is_enabled = tegra20_super_clk_is_enabled,
    .enable = tegra20_super_clk_enable,
    .disable = tegra20_super_clk_disable,
    .set_parent = tegra20_super_clk_set_parent,
    .get_parent = tegra20_super_clk_get_parent,
    .set_rate = tegra20_super_clk_set_rate,
    .round_rate = tegra20_super_clk_round_rate,
    .recalc_rate = tegra20_super_clk_recalc_rate,
}

Definition at line 376 of file tegra20_clocks.c.

struct clk_ops tegra_twd_ops

Initial value:

= {
    .recalc_rate = tegra20_twd_clk_recalc_rate,
}

Definition at line 402 of file tegra20_clocks.c.

Variables
struct clk_ops	tegra_clk_32k_ops

struct clk_ops	tegra_clk_m_ops

struct clk_ops	tegra_super_ops

struct clk_ops	tegra_twd_ops

struct clk_ops	tegra_cop_ops

struct clk_ops	tegra_bus_ops

struct clk_ops	tegra_blink_clk_ops

struct clk_ops	tegra_pll_ops

struct clk_ops	tegra_pllx_ops

struct clk_ops	tegra_plle_ops

struct clk_ops	tegra_pll_div_ops

struct clk_ops	tegra_periph_clk_ops

struct clk_ops	tegra_emc_clk_ops

struct clk_ops	tegra_clk_double_ops

struct clk_ops	tegra_audio_sync_clk_ops

struct clk_ops	tegra_cdev_clk_ops

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation