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Data Structures | Macros | Functions
ti_hecc.c File Reference
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
#include <linux/can/platform/ti_hecc.h>

Go to the source code of this file.

Data Structures

struct  ti_hecc_priv
 

Macros

#define DRV_NAME   "ti_hecc"
 
#define HECC_MODULE_VERSION   "0.7"
 
#define DRV_DESC   "TI High End CAN Controller Driver " HECC_MODULE_VERSION
 
#define HECC_MAX_MAILBOXES   32 /* hardware mailboxes - do not change */
 
#define MAX_TX_PRIO   0x3F /* hardware value - do not change */
 
#define HECC_MB_TX_SHIFT   2 /* as per table above */
 
#define HECC_MAX_TX_MBOX   BIT(HECC_MB_TX_SHIFT)
 
#define HECC_TX_PRIO_SHIFT   (HECC_MB_TX_SHIFT)
 
#define HECC_TX_PRIO_MASK   (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
 
#define HECC_TX_MB_MASK   (HECC_MAX_TX_MBOX - 1)
 
#define HECC_TX_MASK   ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
 
#define HECC_TX_MBOX_MASK   (~(BIT(HECC_MAX_TX_MBOX) - 1))
 
#define HECC_DEF_NAPI_WEIGHT   HECC_MAX_RX_MBOX
 
#define HECC_MAX_RX_MBOX   (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
 
#define HECC_RX_BUFFER_MBOX   12 /* as per table above */
 
#define HECC_RX_FIRST_MBOX   (HECC_MAX_MAILBOXES - 1)
 
#define HECC_RX_HIGH_MBOX_MASK   (~(BIT(HECC_RX_BUFFER_MBOX) - 1))
 
#define HECC_CANME   0x0 /* Mailbox enable */
 
#define HECC_CANMD   0x4 /* Mailbox direction */
 
#define HECC_CANTRS   0x8 /* Transmit request set */
 
#define HECC_CANTRR   0xC /* Transmit request */
 
#define HECC_CANTA   0x10 /* Transmission acknowledge */
 
#define HECC_CANAA   0x14 /* Abort acknowledge */
 
#define HECC_CANRMP   0x18 /* Receive message pending */
 
#define HECC_CANRML   0x1C /* Remote message lost */
 
#define HECC_CANRFP   0x20 /* Remote frame pending */
 
#define HECC_CANGAM   0x24 /* SECC only:Global acceptance mask */
 
#define HECC_CANMC   0x28 /* Master control */
 
#define HECC_CANBTC   0x2C /* Bit timing configuration */
 
#define HECC_CANES   0x30 /* Error and status */
 
#define HECC_CANTEC   0x34 /* Transmit error counter */
 
#define HECC_CANREC   0x38 /* Receive error counter */
 
#define HECC_CANGIF0   0x3C /* Global interrupt flag 0 */
 
#define HECC_CANGIM   0x40 /* Global interrupt mask */
 
#define HECC_CANGIF1   0x44 /* Global interrupt flag 1 */
 
#define HECC_CANMIM   0x48 /* Mailbox interrupt mask */
 
#define HECC_CANMIL   0x4C /* Mailbox interrupt level */
 
#define HECC_CANOPC   0x50 /* Overwrite protection control */
 
#define HECC_CANTIOC   0x54 /* Transmit I/O control */
 
#define HECC_CANRIOC   0x58 /* Receive I/O control */
 
#define HECC_CANLNT   0x5C /* HECC only: Local network time */
 
#define HECC_CANTOC   0x60 /* HECC only: Time-out control */
 
#define HECC_CANTOS   0x64 /* HECC only: Time-out status */
 
#define HECC_CANTIOCE   0x68 /* SCC only:Enhanced TX I/O control */
 
#define HECC_CANRIOCE   0x6C /* SCC only:Enhanced RX I/O control */
 
#define HECC_CANMID   0x0
 
#define HECC_CANMCF   0x4
 
#define HECC_CANMDL   0x8
 
#define HECC_CANMDH   0xC
 
#define HECC_SET_REG   0xFFFFFFFF
 
#define HECC_CANID_MASK   0x3FF /* 18 bits mask for extended id's */
 
#define HECC_CCE_WAIT_COUNT   100 /* Wait for ~1 sec for CCE bit */
 
#define HECC_CANMC_SCM   BIT(13) /* SCC compat mode */
 
#define HECC_CANMC_CCR   BIT(12) /* Change config request */
 
#define HECC_CANMC_PDR   BIT(11) /* Local Power down - for sleep mode */
 
#define HECC_CANMC_ABO   BIT(7) /* Auto Bus On */
 
#define HECC_CANMC_STM   BIT(6) /* Self test mode - loopback */
 
#define HECC_CANMC_SRES   BIT(5) /* Software reset */
 
#define HECC_CANTIOC_EN   BIT(3) /* Enable CAN TX I/O pin */
 
#define HECC_CANRIOC_EN   BIT(3) /* Enable CAN RX I/O pin */
 
#define HECC_CANMID_IDE   BIT(31) /* Extended frame format */
 
#define HECC_CANMID_AME   BIT(30) /* Acceptance mask enable */
 
#define HECC_CANMID_AAM   BIT(29) /* Auto answer mode */
 
#define HECC_CANES_FE   BIT(24) /* form error */
 
#define HECC_CANES_BE   BIT(23) /* bit error */
 
#define HECC_CANES_SA1   BIT(22) /* stuck at dominant error */
 
#define HECC_CANES_CRCE   BIT(21) /* CRC error */
 
#define HECC_CANES_SE   BIT(20) /* stuff bit error */
 
#define HECC_CANES_ACKE   BIT(19) /* ack error */
 
#define HECC_CANES_BO   BIT(18) /* Bus off status */
 
#define HECC_CANES_EP   BIT(17) /* Error passive status */
 
#define HECC_CANES_EW   BIT(16) /* Error warning status */
 
#define HECC_CANES_SMA   BIT(5) /* suspend mode ack */
 
#define HECC_CANES_CCE   BIT(4) /* Change config enabled */
 
#define HECC_CANES_PDA   BIT(3) /* Power down mode ack */
 
#define HECC_CANBTC_SAM   BIT(7) /* sample points */
 
#define HECC_BUS_ERROR
 
#define HECC_CANMCF_RTR   BIT(4) /* Remote transmit request */
 
#define HECC_CANGIF_MAIF   BIT(17) /* Message alarm interrupt */
 
#define HECC_CANGIF_TCOIF   BIT(16) /* Timer counter overflow int */
 
#define HECC_CANGIF_GMIF   BIT(15) /* Global mailbox interrupt */
 
#define HECC_CANGIF_AAIF   BIT(14) /* Abort ack interrupt */
 
#define HECC_CANGIF_WDIF   BIT(13) /* Write denied interrupt */
 
#define HECC_CANGIF_WUIF   BIT(12) /* Wake up interrupt */
 
#define HECC_CANGIF_RMLIF   BIT(11) /* Receive message lost interrupt */
 
#define HECC_CANGIF_BOIF   BIT(10) /* Bus off interrupt */
 
#define HECC_CANGIF_EPIF   BIT(9) /* Error passive interrupt */
 
#define HECC_CANGIF_WLIF   BIT(8) /* Warning level interrupt */
 
#define HECC_CANGIF_MBOX_MASK   0x1F /* Mailbox number mask */
 
#define HECC_CANGIM_I1EN   BIT(1) /* Int line 1 enable */
 
#define HECC_CANGIM_I0EN   BIT(0) /* Int line 0 enable */
 
#define HECC_CANGIM_DEF_MASK   0x700 /* only busoff/warning/passive */
 
#define HECC_CANGIM_SIL   BIT(2) /* system interrupts to int line 1 */
 
#define ti_hecc_suspend   NULL
 
#define ti_hecc_resume   NULL
 

Functions

 MODULE_VERSION (HECC_MODULE_VERSION)
 
 module_platform_driver (ti_hecc_driver)
 
 MODULE_AUTHOR ("Anant Gole <[email protected]>")
 
 MODULE_LICENSE ("GPL v2")
 
 MODULE_DESCRIPTION (DRV_DESC)
 

Macro Definition Documentation

#define DRV_DESC   "TI High End CAN Controller Driver " HECC_MODULE_VERSION

Definition at line 58 of file ti_hecc.c.

#define DRV_NAME   "ti_hecc"

Definition at line 55 of file ti_hecc.c.

#define HECC_BUS_ERROR
Value:
HECC_CANES_CRCE | HECC_CANES_SE |\
HECC_CANES_ACKE)

Definition at line 176 of file ti_hecc.c.

#define HECC_CANAA   0x14 /* Abort acknowledge */

Definition at line 113 of file ti_hecc.c.

#define HECC_CANBTC   0x2C /* Bit timing configuration */

Definition at line 119 of file ti_hecc.c.

#define HECC_CANBTC_SAM   BIT(7) /* sample points */

Definition at line 174 of file ti_hecc.c.

#define HECC_CANES   0x30 /* Error and status */

Definition at line 120 of file ti_hecc.c.

#define HECC_CANES_ACKE   BIT(19) /* ack error */

Definition at line 166 of file ti_hecc.c.

#define HECC_CANES_BE   BIT(23) /* bit error */

Definition at line 162 of file ti_hecc.c.

#define HECC_CANES_BO   BIT(18) /* Bus off status */

Definition at line 167 of file ti_hecc.c.

#define HECC_CANES_CCE   BIT(4) /* Change config enabled */

Definition at line 171 of file ti_hecc.c.

#define HECC_CANES_CRCE   BIT(21) /* CRC error */

Definition at line 164 of file ti_hecc.c.

#define HECC_CANES_EP   BIT(17) /* Error passive status */

Definition at line 168 of file ti_hecc.c.

#define HECC_CANES_EW   BIT(16) /* Error warning status */

Definition at line 169 of file ti_hecc.c.

#define HECC_CANES_FE   BIT(24) /* form error */

Definition at line 161 of file ti_hecc.c.

#define HECC_CANES_PDA   BIT(3) /* Power down mode ack */

Definition at line 172 of file ti_hecc.c.

#define HECC_CANES_SA1   BIT(22) /* stuck at dominant error */

Definition at line 163 of file ti_hecc.c.

#define HECC_CANES_SE   BIT(20) /* stuff bit error */

Definition at line 165 of file ti_hecc.c.

#define HECC_CANES_SMA   BIT(5) /* suspend mode ack */

Definition at line 170 of file ti_hecc.c.

#define HECC_CANGAM   0x24 /* SECC only:Global acceptance mask */

Definition at line 117 of file ti_hecc.c.

#define HECC_CANGIF0   0x3C /* Global interrupt flag 0 */

Definition at line 123 of file ti_hecc.c.

#define HECC_CANGIF1   0x44 /* Global interrupt flag 1 */

Definition at line 125 of file ti_hecc.c.

#define HECC_CANGIF_AAIF   BIT(14) /* Abort ack interrupt */

Definition at line 185 of file ti_hecc.c.

#define HECC_CANGIF_BOIF   BIT(10) /* Bus off interrupt */

Definition at line 189 of file ti_hecc.c.

#define HECC_CANGIF_EPIF   BIT(9) /* Error passive interrupt */

Definition at line 190 of file ti_hecc.c.

#define HECC_CANGIF_GMIF   BIT(15) /* Global mailbox interrupt */

Definition at line 184 of file ti_hecc.c.

#define HECC_CANGIF_MAIF   BIT(17) /* Message alarm interrupt */

Definition at line 182 of file ti_hecc.c.

#define HECC_CANGIF_MBOX_MASK   0x1F /* Mailbox number mask */

Definition at line 192 of file ti_hecc.c.

#define HECC_CANGIF_RMLIF   BIT(11) /* Receive message lost interrupt */

Definition at line 188 of file ti_hecc.c.

#define HECC_CANGIF_TCOIF   BIT(16) /* Timer counter overflow int */

Definition at line 183 of file ti_hecc.c.

#define HECC_CANGIF_WDIF   BIT(13) /* Write denied interrupt */

Definition at line 186 of file ti_hecc.c.

#define HECC_CANGIF_WLIF   BIT(8) /* Warning level interrupt */

Definition at line 191 of file ti_hecc.c.

#define HECC_CANGIF_WUIF   BIT(12) /* Wake up interrupt */

Definition at line 187 of file ti_hecc.c.

#define HECC_CANGIM   0x40 /* Global interrupt mask */

Definition at line 124 of file ti_hecc.c.

#define HECC_CANGIM_DEF_MASK   0x700 /* only busoff/warning/passive */

Definition at line 195 of file ti_hecc.c.

#define HECC_CANGIM_I0EN   BIT(0) /* Int line 0 enable */

Definition at line 194 of file ti_hecc.c.

#define HECC_CANGIM_I1EN   BIT(1) /* Int line 1 enable */

Definition at line 193 of file ti_hecc.c.

#define HECC_CANGIM_SIL   BIT(2) /* system interrupts to int line 1 */

Definition at line 196 of file ti_hecc.c.

#define HECC_CANID_MASK   0x3FF /* 18 bits mask for extended id's */

Definition at line 144 of file ti_hecc.c.

#define HECC_CANLNT   0x5C /* HECC only: Local network time */

Definition at line 131 of file ti_hecc.c.

#define HECC_CANMC   0x28 /* Master control */

Definition at line 118 of file ti_hecc.c.

#define HECC_CANMC_ABO   BIT(7) /* Auto Bus On */

Definition at line 150 of file ti_hecc.c.

#define HECC_CANMC_CCR   BIT(12) /* Change config request */

Definition at line 148 of file ti_hecc.c.

#define HECC_CANMC_PDR   BIT(11) /* Local Power down - for sleep mode */

Definition at line 149 of file ti_hecc.c.

#define HECC_CANMC_SCM   BIT(13) /* SCC compat mode */

Definition at line 147 of file ti_hecc.c.

#define HECC_CANMC_SRES   BIT(5) /* Software reset */

Definition at line 152 of file ti_hecc.c.

#define HECC_CANMC_STM   BIT(6) /* Self test mode - loopback */

Definition at line 151 of file ti_hecc.c.

#define HECC_CANMCF   0x4

Definition at line 139 of file ti_hecc.c.

#define HECC_CANMCF_RTR   BIT(4) /* Remote transmit request */

Definition at line 180 of file ti_hecc.c.

#define HECC_CANMD   0x4 /* Mailbox direction */

Definition at line 109 of file ti_hecc.c.

#define HECC_CANMDH   0xC

Definition at line 141 of file ti_hecc.c.

#define HECC_CANMDL   0x8

Definition at line 140 of file ti_hecc.c.

#define HECC_CANME   0x0 /* Mailbox enable */

Definition at line 108 of file ti_hecc.c.

#define HECC_CANMID   0x0

Definition at line 138 of file ti_hecc.c.

#define HECC_CANMID_AAM   BIT(29) /* Auto answer mode */

Definition at line 159 of file ti_hecc.c.

#define HECC_CANMID_AME   BIT(30) /* Acceptance mask enable */

Definition at line 158 of file ti_hecc.c.

#define HECC_CANMID_IDE   BIT(31) /* Extended frame format */

Definition at line 157 of file ti_hecc.c.

#define HECC_CANMIL   0x4C /* Mailbox interrupt level */

Definition at line 127 of file ti_hecc.c.

#define HECC_CANMIM   0x48 /* Mailbox interrupt mask */

Definition at line 126 of file ti_hecc.c.

#define HECC_CANOPC   0x50 /* Overwrite protection control */

Definition at line 128 of file ti_hecc.c.

#define HECC_CANREC   0x38 /* Receive error counter */

Definition at line 122 of file ti_hecc.c.

#define HECC_CANRFP   0x20 /* Remote frame pending */

Definition at line 116 of file ti_hecc.c.

#define HECC_CANRIOC   0x58 /* Receive I/O control */

Definition at line 130 of file ti_hecc.c.

#define HECC_CANRIOC_EN   BIT(3) /* Enable CAN RX I/O pin */

Definition at line 155 of file ti_hecc.c.

#define HECC_CANRIOCE   0x6C /* SCC only:Enhanced RX I/O control */

Definition at line 135 of file ti_hecc.c.

#define HECC_CANRML   0x1C /* Remote message lost */

Definition at line 115 of file ti_hecc.c.

#define HECC_CANRMP   0x18 /* Receive message pending */

Definition at line 114 of file ti_hecc.c.

#define HECC_CANTA   0x10 /* Transmission acknowledge */

Definition at line 112 of file ti_hecc.c.

#define HECC_CANTEC   0x34 /* Transmit error counter */

Definition at line 121 of file ti_hecc.c.

#define HECC_CANTIOC   0x54 /* Transmit I/O control */

Definition at line 129 of file ti_hecc.c.

#define HECC_CANTIOC_EN   BIT(3) /* Enable CAN TX I/O pin */

Definition at line 154 of file ti_hecc.c.

#define HECC_CANTIOCE   0x68 /* SCC only:Enhanced TX I/O control */

Definition at line 134 of file ti_hecc.c.

#define HECC_CANTOC   0x60 /* HECC only: Time-out control */

Definition at line 132 of file ti_hecc.c.

#define HECC_CANTOS   0x64 /* HECC only: Time-out status */

Definition at line 133 of file ti_hecc.c.

#define HECC_CANTRR   0xC /* Transmit request */

Definition at line 111 of file ti_hecc.c.

#define HECC_CANTRS   0x8 /* Transmit request set */

Definition at line 110 of file ti_hecc.c.

#define HECC_CCE_WAIT_COUNT   100 /* Wait for ~1 sec for CCE bit */

Definition at line 145 of file ti_hecc.c.

#define HECC_DEF_NAPI_WEIGHT   HECC_MAX_RX_MBOX

Definition at line 84 of file ti_hecc.c.

#define HECC_MAX_MAILBOXES   32 /* hardware mailboxes - do not change */

Definition at line 61 of file ti_hecc.c.

#define HECC_MAX_RX_MBOX   (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)

Definition at line 102 of file ti_hecc.c.

#define HECC_MAX_TX_MBOX   BIT(HECC_MB_TX_SHIFT)

Definition at line 77 of file ti_hecc.c.

#define HECC_MB_TX_SHIFT   2 /* as per table above */

Definition at line 76 of file ti_hecc.c.

#define HECC_MODULE_VERSION   "0.7"

Definition at line 56 of file ti_hecc.c.

#define HECC_RX_BUFFER_MBOX   12 /* as per table above */

Definition at line 103 of file ti_hecc.c.

#define HECC_RX_FIRST_MBOX   (HECC_MAX_MAILBOXES - 1)

Definition at line 104 of file ti_hecc.c.

#define HECC_RX_HIGH_MBOX_MASK   (~(BIT(HECC_RX_BUFFER_MBOX) - 1))

Definition at line 105 of file ti_hecc.c.

#define HECC_SET_REG   0xFFFFFFFF

Definition at line 143 of file ti_hecc.c.

#define HECC_TX_MASK   ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)

Definition at line 82 of file ti_hecc.c.

#define HECC_TX_MB_MASK   (HECC_MAX_TX_MBOX - 1)

Definition at line 81 of file ti_hecc.c.

#define HECC_TX_MBOX_MASK   (~(BIT(HECC_MAX_TX_MBOX) - 1))

Definition at line 83 of file ti_hecc.c.

#define HECC_TX_PRIO_MASK   (MAX_TX_PRIO << HECC_MB_TX_SHIFT)

Definition at line 80 of file ti_hecc.c.

#define HECC_TX_PRIO_SHIFT   (HECC_MB_TX_SHIFT)

Definition at line 79 of file ti_hecc.c.

#define MAX_TX_PRIO   0x3F /* hardware value - do not change */

Definition at line 62 of file ti_hecc.c.

#define ti_hecc_resume   NULL

Definition at line 1038 of file ti_hecc.c.

#define ti_hecc_suspend   NULL

Definition at line 1037 of file ti_hecc.c.

Function Documentation

MODULE_AUTHOR ( "Anant Gole <[email protected]>"  )
MODULE_DESCRIPTION ( DRV_DESC  )
MODULE_LICENSE ( "GPL v2 )
module_platform_driver ( ti_hecc_driver  )
MODULE_VERSION ( HECC_MODULE_VERSION  )