Linux Kernel
3.7.1
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#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
#include <linux/can/platform/ti_hecc.h>
Go to the source code of this file.
Data Structures | |
struct | ti_hecc_priv |
Macros | |
#define | DRV_NAME "ti_hecc" |
#define | HECC_MODULE_VERSION "0.7" |
#define | DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION |
#define | HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ |
#define | MAX_TX_PRIO 0x3F /* hardware value - do not change */ |
#define | HECC_MB_TX_SHIFT 2 /* as per table above */ |
#define | HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) |
#define | HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) |
#define | HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) |
#define | HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) |
#define | HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) |
#define | HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1)) |
#define | HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX |
#define | HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) |
#define | HECC_RX_BUFFER_MBOX 12 /* as per table above */ |
#define | HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) |
#define | HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1)) |
#define | HECC_CANME 0x0 /* Mailbox enable */ |
#define | HECC_CANMD 0x4 /* Mailbox direction */ |
#define | HECC_CANTRS 0x8 /* Transmit request set */ |
#define | HECC_CANTRR 0xC /* Transmit request */ |
#define | HECC_CANTA 0x10 /* Transmission acknowledge */ |
#define | HECC_CANAA 0x14 /* Abort acknowledge */ |
#define | HECC_CANRMP 0x18 /* Receive message pending */ |
#define | HECC_CANRML 0x1C /* Remote message lost */ |
#define | HECC_CANRFP 0x20 /* Remote frame pending */ |
#define | HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ |
#define | HECC_CANMC 0x28 /* Master control */ |
#define | HECC_CANBTC 0x2C /* Bit timing configuration */ |
#define | HECC_CANES 0x30 /* Error and status */ |
#define | HECC_CANTEC 0x34 /* Transmit error counter */ |
#define | HECC_CANREC 0x38 /* Receive error counter */ |
#define | HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ |
#define | HECC_CANGIM 0x40 /* Global interrupt mask */ |
#define | HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ |
#define | HECC_CANMIM 0x48 /* Mailbox interrupt mask */ |
#define | HECC_CANMIL 0x4C /* Mailbox interrupt level */ |
#define | HECC_CANOPC 0x50 /* Overwrite protection control */ |
#define | HECC_CANTIOC 0x54 /* Transmit I/O control */ |
#define | HECC_CANRIOC 0x58 /* Receive I/O control */ |
#define | HECC_CANLNT 0x5C /* HECC only: Local network time */ |
#define | HECC_CANTOC 0x60 /* HECC only: Time-out control */ |
#define | HECC_CANTOS 0x64 /* HECC only: Time-out status */ |
#define | HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ |
#define | HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ |
#define | HECC_CANMID 0x0 |
#define | HECC_CANMCF 0x4 |
#define | HECC_CANMDL 0x8 |
#define | HECC_CANMDH 0xC |
#define | HECC_SET_REG 0xFFFFFFFF |
#define | HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ |
#define | HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ |
#define | HECC_CANMC_SCM BIT(13) /* SCC compat mode */ |
#define | HECC_CANMC_CCR BIT(12) /* Change config request */ |
#define | HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ |
#define | HECC_CANMC_ABO BIT(7) /* Auto Bus On */ |
#define | HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ |
#define | HECC_CANMC_SRES BIT(5) /* Software reset */ |
#define | HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ |
#define | HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ |
#define | HECC_CANMID_IDE BIT(31) /* Extended frame format */ |
#define | HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ |
#define | HECC_CANMID_AAM BIT(29) /* Auto answer mode */ |
#define | HECC_CANES_FE BIT(24) /* form error */ |
#define | HECC_CANES_BE BIT(23) /* bit error */ |
#define | HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ |
#define | HECC_CANES_CRCE BIT(21) /* CRC error */ |
#define | HECC_CANES_SE BIT(20) /* stuff bit error */ |
#define | HECC_CANES_ACKE BIT(19) /* ack error */ |
#define | HECC_CANES_BO BIT(18) /* Bus off status */ |
#define | HECC_CANES_EP BIT(17) /* Error passive status */ |
#define | HECC_CANES_EW BIT(16) /* Error warning status */ |
#define | HECC_CANES_SMA BIT(5) /* suspend mode ack */ |
#define | HECC_CANES_CCE BIT(4) /* Change config enabled */ |
#define | HECC_CANES_PDA BIT(3) /* Power down mode ack */ |
#define | HECC_CANBTC_SAM BIT(7) /* sample points */ |
#define | HECC_BUS_ERROR |
#define | HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ |
#define | HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ |
#define | HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ |
#define | HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ |
#define | HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ |
#define | HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ |
#define | HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ |
#define | HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ |
#define | HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ |
#define | HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ |
#define | HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ |
#define | HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ |
#define | HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ |
#define | HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ |
#define | HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ |
#define | HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ |
#define | ti_hecc_suspend NULL |
#define | ti_hecc_resume NULL |
Functions | |
MODULE_VERSION (HECC_MODULE_VERSION) | |
module_platform_driver (ti_hecc_driver) | |
MODULE_AUTHOR ("Anant Gole <[email protected]>") | |
MODULE_LICENSE ("GPL v2") | |
MODULE_DESCRIPTION (DRV_DESC) | |
#define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION |
#define HECC_BUS_ERROR |
#define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ |
#define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ |
#define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ |
#define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ |
#define HECC_CANLNT 0x5C /* HECC only: Local network time */ |
#define HECC_CANOPC 0x50 /* Overwrite protection control */ |
#define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ |
#define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ |
#define HECC_CANTOC 0x60 /* HECC only: Time-out control */ |
#define HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX |
#define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ |
#define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) |
#define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) |
#define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) |
#define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1)) |
#define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) |
#define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) |
#define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1)) |
#define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) |
#define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) |
#define MAX_TX_PRIO 0x3F /* hardware value - do not change */ |
MODULE_AUTHOR | ( | "Anant Gole <[email protected]>" | ) |
MODULE_DESCRIPTION | ( | DRV_DESC | ) |
MODULE_LICENSE | ( | "GPL v2" | ) |
module_platform_driver | ( | ti_hecc_driver | ) |
MODULE_VERSION | ( | HECC_MODULE_VERSION | ) |