Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
u8500_clk.c
Go to the documentation of this file.
1 /*
2  * Clock definitions for u8500 platform.
3  *
4  * Copyright (C) 2012 ST-Ericsson SA
5  * Author: Ulf Hansson <[email protected]>
6  *
7  * License terms: GNU General Public License (GPL) version 2
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/mfd/dbx500-prcmu.h>
14 #include <linux/platform_data/clk-ux500.h>
15 
16 #include "clk.h"
17 
18 void u8500_clk_init(void)
19 {
20  struct prcmu_fw_version *fw_version;
21  const char *sgaclk_parent = NULL;
22  struct clk *clk;
23 
24  /* Clock sources */
25  clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
26  CLK_IS_ROOT|CLK_IGNORE_UNUSED);
27  clk_register_clkdev(clk, "soc0_pll", NULL);
28 
29  clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
30  CLK_IS_ROOT|CLK_IGNORE_UNUSED);
31  clk_register_clkdev(clk, "soc1_pll", NULL);
32 
33  clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
34  CLK_IS_ROOT|CLK_IGNORE_UNUSED);
35  clk_register_clkdev(clk, "ddr_pll", NULL);
36 
37  /* FIXME: Add sys, ulp and int clocks here. */
38 
39  clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
40  CLK_IS_ROOT|CLK_IGNORE_UNUSED,
41  32768);
42  clk_register_clkdev(clk, "clk32k", NULL);
43  clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
44 
45  /* PRCMU clocks */
46  fw_version = prcmu_get_fw_version();
47  if (fw_version != NULL) {
48  switch (fw_version->project) {
49  case PRCMU_FW_PROJECT_U8500_C2:
50  case PRCMU_FW_PROJECT_U8520:
51  case PRCMU_FW_PROJECT_U8420:
52  sgaclk_parent = "soc0_pll";
53  break;
54  default:
55  break;
56  }
57  }
58 
59  if (sgaclk_parent)
60  clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
61  PRCMU_SGACLK, 0);
62  else
63  clk = clk_reg_prcmu_gate("sgclk", NULL,
64  PRCMU_SGACLK, CLK_IS_ROOT);
65  clk_register_clkdev(clk, NULL, "mali");
66 
67  clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
68  clk_register_clkdev(clk, NULL, "UART");
69 
70  clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
71  clk_register_clkdev(clk, NULL, "MSP02");
72 
73  clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
74  clk_register_clkdev(clk, NULL, "MSP1");
75 
76  clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
77  clk_register_clkdev(clk, NULL, "I2C");
78 
79  clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
80  clk_register_clkdev(clk, NULL, "slim");
81 
82  clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
83  clk_register_clkdev(clk, NULL, "PERIPH1");
84 
85  clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
86  clk_register_clkdev(clk, NULL, "PERIPH2");
87 
88  clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
89  clk_register_clkdev(clk, NULL, "PERIPH3");
90 
91  clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
92  clk_register_clkdev(clk, NULL, "PERIPH5");
93 
94  clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
95  clk_register_clkdev(clk, NULL, "PERIPH6");
96 
97  clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
98  clk_register_clkdev(clk, NULL, "PERIPH7");
99 
100  clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
101  CLK_IS_ROOT|CLK_SET_RATE_GATE);
102  clk_register_clkdev(clk, NULL, "lcd");
103  clk_register_clkdev(clk, "lcd", "mcde");
104 
105  clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
106  clk_register_clkdev(clk, NULL, "bml");
107 
108  clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
109  CLK_IS_ROOT|CLK_SET_RATE_GATE);
110 
111  clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
112  CLK_IS_ROOT|CLK_SET_RATE_GATE);
113 
114  clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
115  CLK_IS_ROOT|CLK_SET_RATE_GATE);
116  clk_register_clkdev(clk, NULL, "hdmi");
117  clk_register_clkdev(clk, "hdmi", "mcde");
118 
119  clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
120  clk_register_clkdev(clk, NULL, "apeat");
121 
122  clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
123  CLK_IS_ROOT);
124  clk_register_clkdev(clk, NULL, "apetrace");
125 
126  clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
127  clk_register_clkdev(clk, NULL, "mcde");
128  clk_register_clkdev(clk, "mcde", "mcde");
129  clk_register_clkdev(clk, "dsisys", "dsilink.0");
130  clk_register_clkdev(clk, "dsisys", "dsilink.1");
131  clk_register_clkdev(clk, "dsisys", "dsilink.2");
132 
133  clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
134  CLK_IS_ROOT);
135  clk_register_clkdev(clk, NULL, "ipi2");
136 
137  clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
138  CLK_IS_ROOT);
139  clk_register_clkdev(clk, NULL, "dsialt");
140 
141  clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
142  clk_register_clkdev(clk, NULL, "dma40.0");
143 
144  clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
145  clk_register_clkdev(clk, NULL, "b2r2");
146  clk_register_clkdev(clk, NULL, "b2r2_core");
147  clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
148 
149  clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
150  CLK_IS_ROOT|CLK_SET_RATE_GATE);
151  clk_register_clkdev(clk, NULL, "tv");
152  clk_register_clkdev(clk, "tv", "mcde");
153 
154  clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
155  clk_register_clkdev(clk, NULL, "SSP");
156 
157  clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
158  clk_register_clkdev(clk, NULL, "rngclk");
159 
160  clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
161  clk_register_clkdev(clk, NULL, "uicc");
162 
163  /*
164  * FIXME: The MTU clocks might need some kind of "parent muxed join"
165  * and these have no K-clocks. For now, we ignore the missing
166  * connection to the corresponding P-clocks, p6_mtu0_clk and
167  * p6_mtu1_clk. Instead timclk is used which is the valid parent.
168  */
169  clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
170  clk_register_clkdev(clk, NULL, "mtu0");
171  clk_register_clkdev(clk, NULL, "mtu1");
172 
173  clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
174  clk_register_clkdev(clk, NULL, "sdmmc");
175 
176 
177  clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
178  PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
179  clk_register_clkdev(clk, "dsihs2", "mcde");
180  clk_register_clkdev(clk, "dsihs2", "dsilink.2");
181 
182 
183  clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
184  PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
185  clk_register_clkdev(clk, "dsihs0", "mcde");
186  clk_register_clkdev(clk, "dsihs0", "dsilink.0");
187 
188  clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
189  PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
190  clk_register_clkdev(clk, "dsihs1", "mcde");
191  clk_register_clkdev(clk, "dsihs1", "dsilink.1");
192 
193  clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
194  PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
195  clk_register_clkdev(clk, "dsilp0", "dsilink.0");
196  clk_register_clkdev(clk, "dsilp0", "mcde");
197 
198  clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
199  PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
200  clk_register_clkdev(clk, "dsilp1", "dsilink.1");
201  clk_register_clkdev(clk, "dsilp1", "mcde");
202 
203  clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
204  PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
205  clk_register_clkdev(clk, "dsilp2", "dsilink.2");
206  clk_register_clkdev(clk, "dsilp2", "mcde");
207 
208  clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
209  CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
210  CLK_IGNORE_UNUSED);
211  clk_register_clkdev(clk, NULL, "smp_twd");
212 
213  /*
214  * FIXME: Add special handled PRCMU clocks here:
215  * 1. clk_arm, use PRCMU_ARMCLK.
216  * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
217  * 3. ab9540_clkout1yuv, see clkout0yuv
218  */
219 
220  /* PRCC P-clocks */
221  clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
222  BIT(0), 0);
223  clk_register_clkdev(clk, "apb_pclk", "uart0");
224 
225  clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
226  BIT(1), 0);
227  clk_register_clkdev(clk, "apb_pclk", "uart1");
228 
229  clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
230  BIT(2), 0);
231  clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
232 
233  clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
234  BIT(3), 0);
235  clk_register_clkdev(clk, "apb_pclk", "msp0");
236  clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
237 
238  clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
239  BIT(4), 0);
240  clk_register_clkdev(clk, "apb_pclk", "msp1");
241  clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
242 
243  clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
244  BIT(5), 0);
245  clk_register_clkdev(clk, "apb_pclk", "sdi0");
246 
247  clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
248  BIT(6), 0);
249  clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
250 
251  clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
252  BIT(7), 0);
253  clk_register_clkdev(clk, NULL, "spi3");
254 
255  clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
256  BIT(8), 0);
257  clk_register_clkdev(clk, "apb_pclk", "slimbus0");
258 
259  clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
260  BIT(9), 0);
261  clk_register_clkdev(clk, NULL, "gpio.0");
262  clk_register_clkdev(clk, NULL, "gpio.1");
263  clk_register_clkdev(clk, NULL, "gpioblock0");
264 
265  clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
266  BIT(10), 0);
267  clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
268 
269  clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
270  BIT(11), 0);
271  clk_register_clkdev(clk, "apb_pclk", "msp3");
272  clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
273 
274  clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
275  BIT(0), 0);
276  clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
277 
278  clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
279  BIT(1), 0);
280  clk_register_clkdev(clk, NULL, "spi2");
281 
282  clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
283  BIT(2), 0);
284  clk_register_clkdev(clk, NULL, "spi1");
285 
286  clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
287  BIT(3), 0);
288  clk_register_clkdev(clk, NULL, "pwl");
289 
290  clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
291  BIT(4), 0);
292  clk_register_clkdev(clk, "apb_pclk", "sdi4");
293 
294  clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
295  BIT(5), 0);
296  clk_register_clkdev(clk, "apb_pclk", "msp2");
297  clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
298 
299  clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
300  BIT(6), 0);
301  clk_register_clkdev(clk, "apb_pclk", "sdi1");
302 
303  clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
304  BIT(7), 0);
305  clk_register_clkdev(clk, "apb_pclk", "sdi3");
306 
307  clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
308  BIT(8), 0);
309  clk_register_clkdev(clk, NULL, "spi0");
310 
311  clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
312  BIT(9), 0);
313  clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
314 
315  clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
316  BIT(10), 0);
317  clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
318 
319  clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
320  BIT(11), 0);
321  clk_register_clkdev(clk, NULL, "gpio.6");
322  clk_register_clkdev(clk, NULL, "gpio.7");
323  clk_register_clkdev(clk, NULL, "gpioblock1");
324 
325  clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
326  BIT(12), 0);
327 
328  clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
329  BIT(0), 0);
330  clk_register_clkdev(clk, NULL, "fsmc");
331 
332  clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
333  BIT(1), 0);
334  clk_register_clkdev(clk, "apb_pclk", "ssp0");
335 
336  clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
337  BIT(2), 0);
338  clk_register_clkdev(clk, "apb_pclk", "ssp1");
339 
340  clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
341  BIT(3), 0);
342  clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
343 
344  clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
345  BIT(4), 0);
346  clk_register_clkdev(clk, "apb_pclk", "sdi2");
347 
348  clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
349  BIT(5), 0);
350 
351  clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
352  BIT(6), 0);
353  clk_register_clkdev(clk, "apb_pclk", "uart2");
354 
355  clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
356  BIT(7), 0);
357  clk_register_clkdev(clk, "apb_pclk", "sdi5");
358 
359  clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
360  BIT(8), 0);
361  clk_register_clkdev(clk, NULL, "gpio.2");
362  clk_register_clkdev(clk, NULL, "gpio.3");
363  clk_register_clkdev(clk, NULL, "gpio.4");
364  clk_register_clkdev(clk, NULL, "gpio.5");
365  clk_register_clkdev(clk, NULL, "gpioblock2");
366 
367  clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
368  BIT(0), 0);
369  clk_register_clkdev(clk, "usb", "musb-ux500.0");
370 
371  clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
372  BIT(1), 0);
373  clk_register_clkdev(clk, NULL, "gpio.8");
374  clk_register_clkdev(clk, NULL, "gpioblock3");
375 
376  clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
377  BIT(0), 0);
378 
379  clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
380  BIT(1), 0);
381  clk_register_clkdev(clk, NULL, "cryp0");
382  clk_register_clkdev(clk, NULL, "cryp1");
383 
384  clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
385  BIT(2), 0);
386  clk_register_clkdev(clk, NULL, "hash0");
387 
388  clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
389  BIT(3), 0);
390  clk_register_clkdev(clk, NULL, "pka");
391 
392  clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
393  BIT(4), 0);
394  clk_register_clkdev(clk, NULL, "hash1");
395 
396  clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
397  BIT(5), 0);
398  clk_register_clkdev(clk, NULL, "cfgreg");
399 
400  clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
401  BIT(6), 0);
402  clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
403  BIT(7), 0);
404 
405  /* PRCC K-clocks
406  *
407  * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
408  * by enabling just the K-clock, even if it is not a valid parent to
409  * the K-clock. Until drivers get fixed we might need some kind of
410  * "parent muxed join".
411  */
412 
413  /* Periph1 */
414  clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
415  U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
416  clk_register_clkdev(clk, NULL, "uart0");
417 
418  clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
419  U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
420  clk_register_clkdev(clk, NULL, "uart1");
421 
422  clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
423  U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
424  clk_register_clkdev(clk, NULL, "nmk-i2c.1");
425 
426  clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
427  U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
428  clk_register_clkdev(clk, NULL, "msp0");
429  clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
430 
431  clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
432  U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
433  clk_register_clkdev(clk, NULL, "msp1");
434  clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
435 
436  clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
437  U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
438  clk_register_clkdev(clk, NULL, "sdi0");
439 
440  clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
441  U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
442  clk_register_clkdev(clk, NULL, "nmk-i2c.2");
443 
444  clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
445  U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);
446  clk_register_clkdev(clk, NULL, "slimbus0");
447 
448  clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
449  U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
450  clk_register_clkdev(clk, NULL, "nmk-i2c.4");
451 
452  clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
453  U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
454  clk_register_clkdev(clk, NULL, "msp3");
455  clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
456 
457  /* Periph2 */
458  clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
459  U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
460  clk_register_clkdev(clk, NULL, "nmk-i2c.3");
461 
462  clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
463  U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
464  clk_register_clkdev(clk, NULL, "sdi4");
465 
466  clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
467  U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
468  clk_register_clkdev(clk, NULL, "msp2");
469  clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
470 
471  clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
472  U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
473  clk_register_clkdev(clk, NULL, "sdi1");
474 
475  clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
476  U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
477  clk_register_clkdev(clk, NULL, "sdi3");
478 
479  /* Note that rate is received from parent. */
480  clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
481  U8500_CLKRST2_BASE, BIT(6),
482  CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
483  clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
484  U8500_CLKRST2_BASE, BIT(7),
485  CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
486 
487  /* Periph3 */
488  clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
489  U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
490  clk_register_clkdev(clk, NULL, "ssp0");
491 
492  clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
493  U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
494  clk_register_clkdev(clk, NULL, "ssp1");
495 
496  clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
497  U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
498  clk_register_clkdev(clk, NULL, "nmk-i2c.0");
499 
500  clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
501  U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
502  clk_register_clkdev(clk, NULL, "sdi2");
503 
504  clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
505  U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
506 
507  clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
508  U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
509  clk_register_clkdev(clk, NULL, "uart2");
510 
511  clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
512  U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
513  clk_register_clkdev(clk, NULL, "sdi5");
514 
515  /* Periph6 */
516  clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
517  U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
518 
519 }
Generated on Thu Jan 10 2013 13:28:27 for Linux Kernel by   doxygen 1.8.2