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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | MAX_CRAM_SIZE (1 << 18) /* 2^18 words */ |
| #define | RAM_INCREMENT 1024 /* check in 4 kB increments */ |
| #define | uPD98401_PORTS 0x24 /* probably more ? */ |
| #define | uPD98401_OPEN_CHAN 0x20000000 /* open channel */ |
| #define | uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */ |
| #define | uPD98401_CHAN_ADDR_SHIFT 3 |
| #define | uPD98401_CLOSE_CHAN 0x24000000 /* close channel */ |
| #define | uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */ |
| #define | uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */ |
| #define | uPD98401_TX_READY 0x30000000 /* TX ready */ |
| #define | uPD98401_ADD_BAT 0x34000000 /* add batches */ |
| #define | uPD98401_POOL 0x000f0000 /* pool number */ |
| #define | uPD98401_POOL_SHIFT 16 |
| #define | uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */ |
| #define | uPD98401_NOP 0x3f000000 /* NOP */ |
| #define | uPD98401_IND_ACC 0x00000000 /* Indirect Access */ |
| #define | uPD98401_IA_RW 0x10000000 /* Read/Write (0 W, 1 R) */ |
| #define | uPD98401_IA_B3 0x08000000 /* Byte select, 1 enable */ |
| #define | uPD98401_IA_B2 0x04000000 |
| #define | uPD98401_IA_B1 0x02000000 |
| #define | uPD98401_IA_B0 0x01000000 |
| #define | uPD98401_IA_BALL 0x0f000000 /* whole longword */ |
| #define | uPD98401_IA_TGT 0x000c0000 /* Target */ |
| #define | uPD98401_IA_TGT_SHIFT 18 |
| #define | uPD98401_IA_TGT_CM 0 /* - Control Memory */ |
| #define | uPD98401_IA_TGT_SAR 1 /* - uPD98401 registers */ |
| #define | uPD98401_IA_TGT_PHY 3 /* - PHY device */ |
| #define | uPD98401_IA_ADDR 0x0003ffff |
| #define | uPD98401_BUSY 0x80000000 /* SAR is busy */ |
| #define | uPD98401_LOCKED 0x40000000 /* SAR is locked by other CPU */ |
| #define | uPD98401_AAL5_UINFO 0xffff0000 /* user-supplied information */ |
| #define | uPD98401_AAL5_UINFO_SHIFT 16 |
| #define | uPD98401_AAL5_SIZE 0x0000ffff /* PDU size (in _CELLS_ !!) */ |
| #define | uPD98401_AAL5_CHAN 0x7fff0000 /* Channel number */ |
| #define | uPD98401_AAL5_CHAN_SHIFT 16 |
| #define | uPD98401_AAL5_ERR 0x00008000 /* Error indication */ |
| #define | uPD98401_AAL5_CI 0x00004000 /* Congestion Indication */ |
| #define | uPD98401_AAL5_CLP 0x00002000 /* CLP (>= 1 cell had CLP=1) */ |
| #define | uPD98401_AAL5_ES 0x00000f00 /* Error Status */ |
| #define | uPD98401_AAL5_ES_SHIFT 8 |
| #define | uPD98401_AAL5_ES_NONE 0 /* No error */ |
| #define | uPD98401_AAL5_ES_FREE 1 /* Receiver free buf underflow */ |
| #define | uPD98401_AAL5_ES_FIFO 2 /* Receiver FIFO overrun */ |
| #define | uPD98401_AAL5_ES_TOOBIG 3 /* Maximum length violation */ |
| #define | uPD98401_AAL5_ES_CRC 4 /* CRC error */ |
| #define | uPD98401_AAL5_ES_ABORT 5 /* User abort */ |
| #define | uPD98401_AAL5_ES_LENGTH 6 /* Length violation */ |
| #define | uPD98401_AAL5_ES_T1 7 /* T1 error (timeout) */ |
| #define | uPD98401_AAL5_ES_DEACT 8 /* Deactivated with DEACT_CHAN */ |
| #define | uPD98401_AAL5_POOL 0x0000001f /* Free buffer pool number */ |
| #define | uPD98401_RAW_UINFO uPD98401_AAL5_UINFO |
| #define | uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT |
| #define | uPD98401_RAW_HEC 0x000000ff /* HEC */ |
| #define | uPD98401_RAW_CHAN uPD98401_AAL5_CHAN |
| #define | uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT |
| #define | uPD98401_TXI_CONN 0x7fff0000 /* Connection Number */ |
| #define | uPD98401_TXI_CONN_SHIFT 16 |
| #define | uPD98401_TXI_ACTIVE 0x00008000 /* Channel remains active */ |
| #define | uPD98401_TXI_PQP 0x00007fff /* Packet Queue Pointer */ |
| #define | uPD98401_GMR 0x00 /* General Mode Register */ |
| #define | uPD98401_GSR 0x01 /* General Status Register */ |
| #define | uPD98401_IMR 0x02 /* Interrupt Mask Register */ |
| #define | uPD98401_RQU 0x03 /* Receive Queue Underrun */ |
| #define | uPD98401_RQA 0x04 /* Receive Queue Alert */ |
| #define | uPD98401_ADDR 0x05 /* Last Burst Address */ |
| #define | uPD98401_VER 0x06 /* Version Number */ |
| #define | uPD98401_SWR 0x07 /* Software Reset */ |
| #define | uPD98401_CMR 0x08 /* Command Register */ |
| #define | uPD98401_CMR_L 0x09 /* Command Register and Lock/Unlock */ |
| #define | uPD98401_CER 0x0a /* Command Extension Register */ |
| #define | uPD98401_CER_L 0x0b /* Command Ext Reg and Lock/Unlock */ |
| #define | uPD98401_MSH(n) (0x10+(n)) /* Mailbox n Start Address High */ |
| #define | uPD98401_MSL(n) (0x14+(n)) /* Mailbox n Start Address High */ |
| #define | uPD98401_MBA(n) (0x18+(n)) /* Mailbox n Bottom Address */ |
| #define | uPD98401_MTA(n) (0x1c+(n)) /* Mailbox n Tail Address */ |
| #define | uPD98401_MWA(n) (0x20+(n)) /* Mailbox n Write Address */ |
| #define | uPD98401_GMR_ONE 0x80000000 /* Must be set to one */ |
| #define | uPD98401_GMR_SLM 0x40000000 /* Address mode (0 word, 1 byte) */ |
| #define | uPD98401_GMR_CPE 0x00008000 /* Control Memory Parity Enable */ |
| #define | uPD98401_GMR_LP 0x00004000 /* Loopback */ |
| #define | uPD98401_GMR_WA 0x00002000 /* Early Bus Write Abort/RDY */ |
| #define | uPD98401_GMR_RA 0x00001000 /* Early Read Abort/RDY */ |
| #define | uPD98401_GMR_SZ 0x00000f00 /* Burst Size Enable */ |
| #define | uPD98401_BURST16 0x00000800 /* 16-word burst */ |
| #define | uPD98401_BURST8 0x00000400 /* 8-word burst */ |
| #define | uPD98401_BURST4 0x00000200 /* 4-word burst */ |
| #define | uPD98401_BURST2 0x00000100 /* 2-word burst */ |
| #define | uPD98401_GMR_AD 0x00000080 /* Address (burst resolution) Disable */ |
| #define | uPD98401_GMR_BO 0x00000040 /* Byte Order (0 little, 1 big) */ |
| #define | uPD98401_GMR_PM 0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/ |
| #define | uPD98401_GMR_PC 0x00000010 /* Bus Parity Control (0even,1odd) */ |
| #define | uPD98401_GMR_BPE 0x00000008 /* Bus Parity Enable */ |
| #define | uPD98401_GMR_DR 0x00000004 /* Receive Drop Mode (0drop,1don't)*/ |
| #define | uPD98401_GMR_SE 0x00000002 /* Shapers Enable */ |
| #define | uPD98401_GMR_RE 0x00000001 /* Receiver Enable */ |
| #define | uPD98401_INT_PI 0x80000000 /* PHY interrupt */ |
| #define | uPD98401_INT_RQA 0x40000000 /* Receive Queue Alert */ |
| #define | uPD98401_INT_RQU 0x20000000 /* Receive Queue Underrun */ |
| #define | uPD98401_INT_RD 0x10000000 /* Receiver Deactivated */ |
| #define | uPD98401_INT_SPE 0x08000000 /* System Parity Error */ |
| #define | uPD98401_INT_CPE 0x04000000 /* Control Memory Parity Error */ |
| #define | uPD98401_INT_SBE 0x02000000 /* System Bus Error */ |
| #define | uPD98401_INT_IND 0x01000000 /* Initialization Done */ |
| #define | uPD98401_INT_RCR 0x0000ff00 /* Raw Cell Received */ |
| #define | uPD98401_INT_RCR_SHIFT 8 |
| #define | uPD98401_INT_MF 0x000000f0 /* Mailbox Full */ |
| #define | uPD98401_INT_MF_SHIFT 4 |
| #define | uPD98401_INT_MM 0x0000000f /* Mailbox Modified */ |
| #define | uPD98401_MAJOR 0x0000ff00 /* Major revision */ |
| #define | uPD98401_MAJOR_SHIFT 8 |
| #define | uPD98401_MINOR 0x000000ff /* Minor revision */ |
| #define | uPD98401_IM(n) (0x40000+(n)) /* Scheduler n I and M */ |
| #define | uPD98401_X(n) (0x40010+(n)) /* Scheduler n X */ |
| #define | uPD98401_Y(n) (0x40020+(n)) /* Scheduler n Y */ |
| #define | uPD98401_PC(n) (0x40030+(n)) /* Scheduler n P, C, p and c */ |
| #define | uPD98401_PS(n) (0x40040+(n)) /* Scheduler n priority and status */ |
| #define | uPD98401_IM_I 0xff000000 /* I */ |
| #define | uPD98401_IM_I_SHIFT 24 |
| #define | uPD98401_IM_M 0x00ffffff /* M */ |
| #define | uPD98401_PC_P 0xff000000 /* P */ |
| #define | uPD98401_PC_P_SHIFT 24 |
| #define | uPD98401_PC_C 0x00ff0000 /* C */ |
| #define | uPD98401_PC_C_SHIFT 16 |
| #define | uPD98401_PC_p 0x0000ff00 /* p */ |
| #define | uPD98401_PC_p_SHIFT 8 |
| #define | uPD98401_PC_c 0x000000ff /* c */ |
| #define | uPD98401_PS_PRIO 0xf0 /* Priority level (0 high, 15 low) */ |
| #define | uPD98401_PS_PRIO_SHIFT 4 |
| #define | uPD98401_PS_S 0x08 /* Scan - must be 0 (internal) */ |
| #define | uPD98401_PS_R 0x04 /* Round Robin (internal) */ |
| #define | uPD98401_PS_A 0x02 /* Active (internal) */ |
| #define | uPD98401_PS_E 0x01 /* Enabled */ |
| #define | uPD98401_TOS 0x40100 /* Top of Stack Control Memory Address */ |
| #define | uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */ |
| #define | uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */ |
| #define | uPD98401_T1R 0x40300 /* T1 Register */ |
| #define | uPD98401_VRR 0x40301 /* VPI/VCI Reduction Register/Recv. Shutdown */ |
| #define | uPD98401_TSR 0x40302 /* Time-Stamp Register */ |
| #define | uPD98401_VRR_SDM 0x80000000 /* Shutdown Mode */ |
| #define | uPD98401_VRR_SHIFT 0x000f0000 /* VPI/VCI Shift */ |
| #define | uPD98401_VRR_SHIFT_SHIFT 16 |
| #define | uPD98401_VRR_MASK 0x0000ffff /* VPI/VCI mask */ |
| #define | uPD98401_TXPD_SIZE 16 /* descriptor size (in bytes) */ |
| #define | uPD98401_TXPD_V 0x80000000 /* Valid bit */ |
| #define | uPD98401_TXPD_DP 0x40000000 /* Descriptor (1) or Pointer (0) */ |
| #define | uPD98401_TXPD_SM 0x20000000 /* Single (1) or Multiple (0) */ |
| #define | uPD98401_TXPD_CLPM 0x18000000 /* CLP mode */ |
| #define | uPD98401_CLPM_0 0 /* 00 CLP = 0 */ |
| #define | uPD98401_CLPM_1 3 /* 11 CLP = 1 */ |
| #define | uPD98401_CLPM_LAST 1 /* 01 CLP unless last cell */ |
| #define | uPD98401_TXPD_CLPM_SHIFT 27 |
| #define | uPD98401_TXPD_PTI 0x07000000 /* PTI pattern */ |
| #define | uPD98401_TXPD_PTI_SHIFT 24 |
| #define | uPD98401_TXPD_GFC 0x00f00000 /* GFC pattern */ |
| #define | uPD98401_TXPD_GFC_SHIFT 20 |
| #define | uPD98401_TXPD_C10 0x00040000 /* insert CRC-10 */ |
| #define | uPD98401_TXPD_AAL5 0x00020000 /* AAL5 processing */ |
| #define | uPD98401_TXPD_MB 0x00010000 /* TX mailbox number */ |
| #define | uPD98401_TXPD_UU 0x0000ff00 /* CPCS-UU */ |
| #define | uPD98401_TXPD_UU_SHIFT 8 |
| #define | uPD98401_TXPD_CPI 0x000000ff /* CPI */ |
| #define | uPD98401_TXBD_SIZE 8 /* descriptor size (in bytes) */ |
| #define | uPD98401_TXBD_LAST 0x80000000 /* last buffer in packet */ |
| #define | uPD98401_TXVC_L 0x80000000 /* last buffer */ |
| #define | uPD98401_TXVC_SHP 0x0f000000 /* shaper number */ |
| #define | uPD98401_TXVC_SHP_SHIFT 24 |
| #define | uPD98401_TXVC_VPI 0x00ff0000 /* VPI */ |
| #define | uPD98401_TXVC_VPI_SHIFT 16 |
| #define | uPD98401_TXVC_VCI 0x0000ffff /* VCI */ |
| #define | uPD98401_TXVC_QRP 6 /* Queue Read Pointer is in word 6 */ |
| #define | uPD98401_RXFP_ALERT 0x70000000 /* low water mark */ |
| #define | uPD98401_RXFP_ALERT_SHIFT 28 |
| #define | uPD98401_RXFP_BFSZ 0x0f000000 /* buffer size, 64*2^n */ |
| #define | uPD98401_RXFP_BFSZ_SHIFT 24 |
| #define | uPD98401_RXFP_BTSZ 0x00ff0000 /* batch size, n+1 */ |
| #define | uPD98401_RXFP_BTSZ_SHIFT 16 |
| #define | uPD98401_RXFP_REMAIN 0x0000ffff /* remaining batches in pool */ |
| #define | uPD98401_RXVC_BTSZ 0xff000000 /* remaining free buffers in batch */ |
| #define | uPD98401_RXVC_BTSZ_SHIFT 24 |
| #define | uPD98401_RXVC_MB 0x00200000 /* RX mailbox number */ |
| #define | uPD98401_RXVC_POOL 0x001f0000 /* free buffer pool number */ |
| #define | uPD98401_RXVC_POOL_SHIFT 16 |
| #define | uPD98401_RXVC_UINFO 0x0000ffff /* user-supplied information */ |
| #define | uPD98401_RXVC_T1 0xffff0000 /* T1 timestamp */ |
| #define | uPD98401_RXVC_T1_SHIFT 16 |
| #define | uPD98401_RXVC_PR 0x00008000 /* Packet Reception, 1 if busy */ |
| #define | uPD98401_RXVC_DR 0x00004000 /* FIFO Drop */ |
| #define | uPD98401_RXVC_OD 0x00001000 /* Drop OAM cells */ |
| #define | uPD98401_RXVC_AR 0x00000800 /* AAL5 or raw cell; 1 if AAL5 */ |
| #define | uPD98401_RXVC_MAXSEG 0x000007ff /* max number of segments per PDU */ |
| #define | uPD98401_RXVC_REM 0xfffe0000 /* remaining words in curr buffer */ |
| #define | uPD98401_RXVC_REM_SHIFT 17 |
| #define | uPD98401_RXVC_CLP 0x00010000 /* CLP received */ |
| #define | uPD98401_RXVC_BFA 0x00008000 /* Buffer Assigned */ |
| #define | uPD98401_RXVC_BTA 0x00004000 /* Batch Assigned */ |
| #define | uPD98401_RXVC_CI 0x00002000 /* Congestion Indication */ |
| #define | uPD98401_RXVC_DD 0x00001000 /* Dropping incoming cells */ |
| #define | uPD98401_RXVC_DP 0x00000800 /* like PR ? */ |
| #define | uPD98401_RXVC_CURSEG 0x000007ff /* Current Segment count */ |
| #define | uPD98401_RXLT_ENBL 0x8000 /* Enable */ |
| #define MAX_CRAM_SIZE (1 << 18) /* 2^18 words */ |
Definition at line 10 of file uPD98401.h.
Definition at line 11 of file uPD98401.h.
| #define uPD98401_AAL5_CHAN 0x7fff0000 /* Channel number */ |
Definition at line 61 of file uPD98401.h.
| #define uPD98401_AAL5_CHAN_SHIFT 16 |
Definition at line 62 of file uPD98401.h.
| #define uPD98401_AAL5_CI 0x00004000 /* Congestion Indication */ |
Definition at line 64 of file uPD98401.h.
| #define uPD98401_AAL5_CLP 0x00002000 /* CLP (>= 1 cell had CLP=1) */ |
Definition at line 65 of file uPD98401.h.
| #define uPD98401_AAL5_ERR 0x00008000 /* Error indication */ |
Definition at line 63 of file uPD98401.h.
| #define uPD98401_AAL5_ES 0x00000f00 /* Error Status */ |
Definition at line 66 of file uPD98401.h.
| #define uPD98401_AAL5_ES_ABORT 5 /* User abort */ |
Definition at line 73 of file uPD98401.h.
Definition at line 72 of file uPD98401.h.
| #define uPD98401_AAL5_ES_DEACT 8 /* Deactivated with DEACT_CHAN */ |
Definition at line 76 of file uPD98401.h.
Definition at line 70 of file uPD98401.h.
Definition at line 69 of file uPD98401.h.
| #define uPD98401_AAL5_ES_LENGTH 6 /* Length violation */ |
Definition at line 74 of file uPD98401.h.
Definition at line 68 of file uPD98401.h.
| #define uPD98401_AAL5_ES_SHIFT 8 |
Definition at line 67 of file uPD98401.h.
Definition at line 75 of file uPD98401.h.
| #define uPD98401_AAL5_ES_TOOBIG 3 /* Maximum length violation */ |
Definition at line 71 of file uPD98401.h.
| #define uPD98401_AAL5_POOL 0x0000001f /* Free buffer pool number */ |
Definition at line 77 of file uPD98401.h.
| #define uPD98401_AAL5_SIZE 0x0000ffff /* PDU size (in _CELLS_ !!) */ |
Definition at line 60 of file uPD98401.h.
| #define uPD98401_AAL5_UINFO 0xffff0000 /* user-supplied information */ |
Definition at line 58 of file uPD98401.h.
| #define uPD98401_AAL5_UINFO_SHIFT 16 |
Definition at line 59 of file uPD98401.h.
| #define uPD98401_ADD_BAT 0x34000000 /* add batches */ |
Definition at line 27 of file uPD98401.h.
| #define uPD98401_ADDR 0x05 /* Last Burst Address */ |
Definition at line 101 of file uPD98401.h.
| #define uPD98401_BURST16 0x00000800 /* 16-word burst */ |
Definition at line 123 of file uPD98401.h.
| #define uPD98401_BURST2 0x00000100 /* 2-word burst */ |
Definition at line 126 of file uPD98401.h.
| #define uPD98401_BURST4 0x00000200 /* 4-word burst */ |
Definition at line 125 of file uPD98401.h.
| #define uPD98401_BURST8 0x00000400 /* 8-word burst */ |
Definition at line 124 of file uPD98401.h.
| #define uPD98401_BUSY 0x80000000 /* SAR is busy */ |
Definition at line 50 of file uPD98401.h.
| #define uPD98401_CER 0x0a /* Command Extension Register */ |
Definition at line 106 of file uPD98401.h.
| #define uPD98401_CER_L 0x0b /* Command Ext Reg and Lock/Unlock */ |
Definition at line 107 of file uPD98401.h.
| #define uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */ |
Definition at line 21 of file uPD98401.h.
| #define uPD98401_CHAN_ADDR_SHIFT 3 |
Definition at line 22 of file uPD98401.h.
| #define uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */ |
Definition at line 24 of file uPD98401.h.
| #define uPD98401_CLOSE_CHAN 0x24000000 /* close channel */ |
Definition at line 23 of file uPD98401.h.
| #define uPD98401_CLPM_0 0 /* 00 CLP = 0 */ |
Definition at line 211 of file uPD98401.h.
| #define uPD98401_CLPM_1 3 /* 11 CLP = 1 */ |
Definition at line 212 of file uPD98401.h.
| #define uPD98401_CLPM_LAST 1 /* 01 CLP unless last cell */ |
Definition at line 213 of file uPD98401.h.
| #define uPD98401_CMR 0x08 /* Command Register */ |
Definition at line 104 of file uPD98401.h.
| #define uPD98401_CMR_L 0x09 /* Command Register and Lock/Unlock */ |
Definition at line 105 of file uPD98401.h.
| #define uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */ |
Definition at line 25 of file uPD98401.h.
| #define uPD98401_GMR 0x00 /* General Mode Register */ |
Definition at line 96 of file uPD98401.h.
| #define uPD98401_GMR_AD 0x00000080 /* Address (burst resolution) Disable */ |
Definition at line 127 of file uPD98401.h.
| #define uPD98401_GMR_BO 0x00000040 /* Byte Order (0 little, 1 big) */ |
Definition at line 128 of file uPD98401.h.
| #define uPD98401_GMR_BPE 0x00000008 /* Bus Parity Enable */ |
Definition at line 131 of file uPD98401.h.
| #define uPD98401_GMR_CPE 0x00008000 /* Control Memory Parity Enable */ |
Definition at line 118 of file uPD98401.h.
| #define uPD98401_GMR_DR 0x00000004 /* Receive Drop Mode (0drop,1don't)*/ |
Definition at line 132 of file uPD98401.h.
| #define uPD98401_GMR_LP 0x00004000 /* Loopback */ |
Definition at line 119 of file uPD98401.h.
| #define uPD98401_GMR_ONE 0x80000000 /* Must be set to one */ |
Definition at line 116 of file uPD98401.h.
| #define uPD98401_GMR_PC 0x00000010 /* Bus Parity Control (0even,1odd) */ |
Definition at line 130 of file uPD98401.h.
| #define uPD98401_GMR_PM 0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/ |
Definition at line 129 of file uPD98401.h.
| #define uPD98401_GMR_RA 0x00001000 /* Early Read Abort/RDY */ |
Definition at line 121 of file uPD98401.h.
| #define uPD98401_GMR_RE 0x00000001 /* Receiver Enable */ |
Definition at line 134 of file uPD98401.h.
| #define uPD98401_GMR_SE 0x00000002 /* Shapers Enable */ |
Definition at line 133 of file uPD98401.h.
| #define uPD98401_GMR_SLM 0x40000000 /* Address mode (0 word, 1 byte) */ |
Definition at line 117 of file uPD98401.h.
| #define uPD98401_GMR_SZ 0x00000f00 /* Burst Size Enable */ |
Definition at line 122 of file uPD98401.h.
| #define uPD98401_GMR_WA 0x00002000 /* Early Bus Write Abort/RDY */ |
Definition at line 120 of file uPD98401.h.
| #define uPD98401_GSR 0x01 /* General Status Register */ |
Definition at line 97 of file uPD98401.h.
| #define uPD98401_IA_ADDR 0x0003ffff |
Definition at line 44 of file uPD98401.h.
| #define uPD98401_IA_B0 0x01000000 |
Definition at line 37 of file uPD98401.h.
| #define uPD98401_IA_B1 0x02000000 |
Definition at line 36 of file uPD98401.h.
| #define uPD98401_IA_B2 0x04000000 |
Definition at line 35 of file uPD98401.h.
| #define uPD98401_IA_B3 0x08000000 /* Byte select, 1 enable */ |
Definition at line 34 of file uPD98401.h.
| #define uPD98401_IA_BALL 0x0f000000 /* whole longword */ |
Definition at line 38 of file uPD98401.h.
| #define uPD98401_IA_RW 0x10000000 /* Read/Write (0 W, 1 R) */ |
Definition at line 33 of file uPD98401.h.
| #define uPD98401_IA_TGT 0x000c0000 /* Target */ |
Definition at line 39 of file uPD98401.h.
Definition at line 41 of file uPD98401.h.
Definition at line 43 of file uPD98401.h.
| #define uPD98401_IA_TGT_SAR 1 /* - uPD98401 registers */ |
Definition at line 42 of file uPD98401.h.
| #define uPD98401_IA_TGT_SHIFT 18 |
Definition at line 40 of file uPD98401.h.
| #define uPD98401_IM | ( | n | ) | (0x40000+(n)) /* Scheduler n I and M */ |
Definition at line 160 of file uPD98401.h.
| #define uPD98401_IM_I 0xff000000 /* I */ |
Definition at line 167 of file uPD98401.h.
| #define uPD98401_IM_I_SHIFT 24 |
Definition at line 168 of file uPD98401.h.
| #define uPD98401_IM_M 0x00ffffff /* M */ |
Definition at line 169 of file uPD98401.h.
| #define uPD98401_IMR 0x02 /* Interrupt Mask Register */ |
Definition at line 98 of file uPD98401.h.
| #define uPD98401_IND_ACC 0x00000000 /* Indirect Access */ |
Definition at line 32 of file uPD98401.h.
| #define uPD98401_INT_CPE 0x04000000 /* Control Memory Parity Error */ |
Definition at line 142 of file uPD98401.h.
| #define uPD98401_INT_IND 0x01000000 /* Initialization Done */ |
Definition at line 144 of file uPD98401.h.
| #define uPD98401_INT_MF 0x000000f0 /* Mailbox Full */ |
Definition at line 147 of file uPD98401.h.
| #define uPD98401_INT_MF_SHIFT 4 |
Definition at line 148 of file uPD98401.h.
| #define uPD98401_INT_MM 0x0000000f /* Mailbox Modified */ |
Definition at line 149 of file uPD98401.h.
| #define uPD98401_INT_PI 0x80000000 /* PHY interrupt */ |
Definition at line 137 of file uPD98401.h.
| #define uPD98401_INT_RCR 0x0000ff00 /* Raw Cell Received */ |
Definition at line 145 of file uPD98401.h.
| #define uPD98401_INT_RCR_SHIFT 8 |
Definition at line 146 of file uPD98401.h.
| #define uPD98401_INT_RD 0x10000000 /* Receiver Deactivated */ |
Definition at line 140 of file uPD98401.h.
| #define uPD98401_INT_RQA 0x40000000 /* Receive Queue Alert */ |
Definition at line 138 of file uPD98401.h.
| #define uPD98401_INT_RQU 0x20000000 /* Receive Queue Underrun */ |
Definition at line 139 of file uPD98401.h.
| #define uPD98401_INT_SBE 0x02000000 /* System Bus Error */ |
Definition at line 143 of file uPD98401.h.
| #define uPD98401_INT_SPE 0x08000000 /* System Parity Error */ |
Definition at line 141 of file uPD98401.h.
| #define uPD98401_LOCKED 0x40000000 /* SAR is locked by other CPU */ |
Definition at line 51 of file uPD98401.h.
| #define uPD98401_MAJOR 0x0000ff00 /* Major revision */ |
Definition at line 152 of file uPD98401.h.
| #define uPD98401_MAJOR_SHIFT 8 |
Definition at line 153 of file uPD98401.h.
| #define uPD98401_MBA | ( | n | ) | (0x18+(n)) /* Mailbox n Bottom Address */ |
Definition at line 111 of file uPD98401.h.
| #define uPD98401_MINOR 0x000000ff /* Minor revision */ |
Definition at line 154 of file uPD98401.h.
| #define uPD98401_MSH | ( | n | ) | (0x10+(n)) /* Mailbox n Start Address High */ |
Definition at line 109 of file uPD98401.h.
| #define uPD98401_MSL | ( | n | ) | (0x14+(n)) /* Mailbox n Start Address High */ |
Definition at line 110 of file uPD98401.h.
| #define uPD98401_MTA | ( | n | ) | (0x1c+(n)) /* Mailbox n Tail Address */ |
Definition at line 112 of file uPD98401.h.
| #define uPD98401_MWA | ( | n | ) | (0x20+(n)) /* Mailbox n Write Address */ |
Definition at line 113 of file uPD98401.h.
| #define uPD98401_NOP 0x3f000000 /* NOP */ |
Definition at line 31 of file uPD98401.h.
| #define uPD98401_OPEN_CHAN 0x20000000 /* open channel */ |
Definition at line 20 of file uPD98401.h.
| #define uPD98401_PC | ( | n | ) | (0x40030+(n)) /* Scheduler n P, C, p and c */ |
Definition at line 163 of file uPD98401.h.
| #define uPD98401_PC_C 0x00ff0000 /* C */ |
Definition at line 174 of file uPD98401.h.
| #define uPD98401_PC_c 0x000000ff /* c */ |
Definition at line 178 of file uPD98401.h.
| #define uPD98401_PC_C_SHIFT 16 |
Definition at line 175 of file uPD98401.h.
| #define uPD98401_PC_P 0xff000000 /* P */ |
Definition at line 172 of file uPD98401.h.
| #define uPD98401_PC_p 0x0000ff00 /* p */ |
Definition at line 176 of file uPD98401.h.
| #define uPD98401_PC_P_SHIFT 24 |
Definition at line 173 of file uPD98401.h.
| #define uPD98401_PC_p_SHIFT 8 |
Definition at line 177 of file uPD98401.h.
| #define uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */ |
Definition at line 190 of file uPD98401.h.
| #define uPD98401_POOL 0x000f0000 /* pool number */ |
Definition at line 28 of file uPD98401.h.
| #define uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */ |
Definition at line 30 of file uPD98401.h.
| #define uPD98401_POOL_SHIFT 16 |
Definition at line 29 of file uPD98401.h.
| #define uPD98401_PORTS 0x24 /* probably more ? */ |
Definition at line 13 of file uPD98401.h.
| #define uPD98401_PS | ( | n | ) | (0x40040+(n)) /* Scheduler n priority and status */ |
Definition at line 164 of file uPD98401.h.
| #define uPD98401_PS_A 0x02 /* Active (internal) */ |
Definition at line 185 of file uPD98401.h.
| #define uPD98401_PS_E 0x01 /* Enabled */ |
Definition at line 186 of file uPD98401.h.
| #define uPD98401_PS_PRIO 0xf0 /* Priority level (0 high, 15 low) */ |
Definition at line 181 of file uPD98401.h.
| #define uPD98401_PS_PRIO_SHIFT 4 |
Definition at line 182 of file uPD98401.h.
| #define uPD98401_PS_R 0x04 /* Round Robin (internal) */ |
Definition at line 184 of file uPD98401.h.
| #define uPD98401_PS_S 0x08 /* Scan - must be 0 (internal) */ |
Definition at line 183 of file uPD98401.h.
| #define uPD98401_RAW_CHAN uPD98401_AAL5_CHAN |
Definition at line 83 of file uPD98401.h.
| #define uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT |
Definition at line 84 of file uPD98401.h.
| #define uPD98401_RAW_HEC 0x000000ff /* HEC */ |
Definition at line 82 of file uPD98401.h.
| #define uPD98401_RAW_UINFO uPD98401_AAL5_UINFO |
Definition at line 80 of file uPD98401.h.
| #define uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT |
Definition at line 81 of file uPD98401.h.
| #define uPD98401_RQA 0x04 /* Receive Queue Alert */ |
Definition at line 100 of file uPD98401.h.
| #define uPD98401_RQU 0x03 /* Receive Queue Underrun */ |
Definition at line 99 of file uPD98401.h.
| #define uPD98401_RXFP_ALERT 0x70000000 /* low water mark */ |
Definition at line 251 of file uPD98401.h.
| #define uPD98401_RXFP_ALERT_SHIFT 28 |
Definition at line 252 of file uPD98401.h.
| #define uPD98401_RXFP_BFSZ 0x0f000000 /* buffer size, 64*2^n */ |
Definition at line 253 of file uPD98401.h.
| #define uPD98401_RXFP_BFSZ_SHIFT 24 |
Definition at line 254 of file uPD98401.h.
| #define uPD98401_RXFP_BTSZ 0x00ff0000 /* batch size, n+1 */ |
Definition at line 255 of file uPD98401.h.
| #define uPD98401_RXFP_BTSZ_SHIFT 16 |
Definition at line 256 of file uPD98401.h.
| #define uPD98401_RXFP_REMAIN 0x0000ffff /* remaining batches in pool */ |
Definition at line 257 of file uPD98401.h.
| #define uPD98401_RXLT_ENBL 0x8000 /* Enable */ |
Definition at line 290 of file uPD98401.h.
| #define uPD98401_RXVC_AR 0x00000800 /* AAL5 or raw cell; 1 if AAL5 */ |
Definition at line 274 of file uPD98401.h.
| #define uPD98401_RXVC_BFA 0x00008000 /* Buffer Assigned */ |
Definition at line 279 of file uPD98401.h.
| #define uPD98401_RXVC_BTA 0x00004000 /* Batch Assigned */ |
Definition at line 280 of file uPD98401.h.
| #define uPD98401_RXVC_BTSZ 0xff000000 /* remaining free buffers in batch */ |
Definition at line 263 of file uPD98401.h.
| #define uPD98401_RXVC_BTSZ_SHIFT 24 |
Definition at line 264 of file uPD98401.h.
| #define uPD98401_RXVC_CI 0x00002000 /* Congestion Indication */ |
Definition at line 281 of file uPD98401.h.
| #define uPD98401_RXVC_CLP 0x00010000 /* CLP received */ |
Definition at line 278 of file uPD98401.h.
| #define uPD98401_RXVC_CURSEG 0x000007ff /* Current Segment count */ |
Definition at line 284 of file uPD98401.h.
| #define uPD98401_RXVC_DD 0x00001000 /* Dropping incoming cells */ |
Definition at line 282 of file uPD98401.h.
| #define uPD98401_RXVC_DP 0x00000800 /* like PR ? */ |
Definition at line 283 of file uPD98401.h.
| #define uPD98401_RXVC_DR 0x00004000 /* FIFO Drop */ |
Definition at line 272 of file uPD98401.h.
| #define uPD98401_RXVC_MAXSEG 0x000007ff /* max number of segments per PDU */ |
Definition at line 275 of file uPD98401.h.
| #define uPD98401_RXVC_MB 0x00200000 /* RX mailbox number */ |
Definition at line 265 of file uPD98401.h.
| #define uPD98401_RXVC_OD 0x00001000 /* Drop OAM cells */ |
Definition at line 273 of file uPD98401.h.
| #define uPD98401_RXVC_POOL 0x001f0000 /* free buffer pool number */ |
Definition at line 266 of file uPD98401.h.
| #define uPD98401_RXVC_POOL_SHIFT 16 |
Definition at line 267 of file uPD98401.h.
| #define uPD98401_RXVC_PR 0x00008000 /* Packet Reception, 1 if busy */ |
Definition at line 271 of file uPD98401.h.
| #define uPD98401_RXVC_REM 0xfffe0000 /* remaining words in curr buffer */ |
Definition at line 276 of file uPD98401.h.
| #define uPD98401_RXVC_REM_SHIFT 17 |
Definition at line 277 of file uPD98401.h.
| #define uPD98401_RXVC_T1 0xffff0000 /* T1 timestamp */ |
Definition at line 269 of file uPD98401.h.
| #define uPD98401_RXVC_T1_SHIFT 16 |
Definition at line 270 of file uPD98401.h.
| #define uPD98401_RXVC_UINFO 0x0000ffff /* user-supplied information */ |
Definition at line 268 of file uPD98401.h.
| #define uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */ |
Definition at line 189 of file uPD98401.h.
| #define uPD98401_SWR 0x07 /* Software Reset */ |
Definition at line 103 of file uPD98401.h.
| #define uPD98401_T1R 0x40300 /* T1 Register */ |
Definition at line 191 of file uPD98401.h.
| #define uPD98401_TOS 0x40100 /* Top of Stack Control Memory Address */ |
Definition at line 188 of file uPD98401.h.
| #define uPD98401_TSR 0x40302 /* Time-Stamp Register */ |
Definition at line 193 of file uPD98401.h.
| #define uPD98401_TX_READY 0x30000000 /* TX ready */ |
Definition at line 26 of file uPD98401.h.
| #define uPD98401_TXBD_LAST 0x80000000 /* last buffer in packet */ |
Definition at line 232 of file uPD98401.h.
| #define uPD98401_TXBD_SIZE 8 /* descriptor size (in bytes) */ |
Definition at line 230 of file uPD98401.h.
| #define uPD98401_TXI_ACTIVE 0x00008000 /* Channel remains active */ |
Definition at line 89 of file uPD98401.h.
| #define uPD98401_TXI_CONN 0x7fff0000 /* Connection Number */ |
Definition at line 87 of file uPD98401.h.
| #define uPD98401_TXI_CONN_SHIFT 16 |
Definition at line 88 of file uPD98401.h.
| #define uPD98401_TXI_PQP 0x00007fff /* Packet Queue Pointer */ |
Definition at line 90 of file uPD98401.h.
| #define uPD98401_TXPD_AAL5 0x00020000 /* AAL5 processing */ |
Definition at line 220 of file uPD98401.h.
| #define uPD98401_TXPD_C10 0x00040000 /* insert CRC-10 */ |
Definition at line 219 of file uPD98401.h.
| #define uPD98401_TXPD_CLPM 0x18000000 /* CLP mode */ |
Definition at line 210 of file uPD98401.h.
| #define uPD98401_TXPD_CLPM_SHIFT 27 |
Definition at line 214 of file uPD98401.h.
| #define uPD98401_TXPD_CPI 0x000000ff /* CPI */ |
Definition at line 224 of file uPD98401.h.
| #define uPD98401_TXPD_DP 0x40000000 /* Descriptor (1) or Pointer (0) */ |
Definition at line 208 of file uPD98401.h.
| #define uPD98401_TXPD_GFC 0x00f00000 /* GFC pattern */ |
Definition at line 217 of file uPD98401.h.
| #define uPD98401_TXPD_GFC_SHIFT 20 |
Definition at line 218 of file uPD98401.h.
| #define uPD98401_TXPD_MB 0x00010000 /* TX mailbox number */ |
Definition at line 221 of file uPD98401.h.
| #define uPD98401_TXPD_PTI 0x07000000 /* PTI pattern */ |
Definition at line 215 of file uPD98401.h.
| #define uPD98401_TXPD_PTI_SHIFT 24 |
Definition at line 216 of file uPD98401.h.
| #define uPD98401_TXPD_SIZE 16 /* descriptor size (in bytes) */ |
Definition at line 205 of file uPD98401.h.
| #define uPD98401_TXPD_SM 0x20000000 /* Single (1) or Multiple (0) */ |
Definition at line 209 of file uPD98401.h.
| #define uPD98401_TXPD_UU 0x0000ff00 /* CPCS-UU */ |
Definition at line 222 of file uPD98401.h.
| #define uPD98401_TXPD_UU_SHIFT 8 |
Definition at line 223 of file uPD98401.h.
| #define uPD98401_TXPD_V 0x80000000 /* Valid bit */ |
Definition at line 207 of file uPD98401.h.
| #define uPD98401_TXVC_L 0x80000000 /* last buffer */ |
Definition at line 239 of file uPD98401.h.
Definition at line 245 of file uPD98401.h.
| #define uPD98401_TXVC_SHP 0x0f000000 /* shaper number */ |
Definition at line 240 of file uPD98401.h.
| #define uPD98401_TXVC_SHP_SHIFT 24 |
Definition at line 241 of file uPD98401.h.
| #define uPD98401_TXVC_VCI 0x0000ffff /* VCI */ |
Definition at line 244 of file uPD98401.h.
| #define uPD98401_TXVC_VPI 0x00ff0000 /* VPI */ |
Definition at line 242 of file uPD98401.h.
| #define uPD98401_TXVC_VPI_SHIFT 16 |
Definition at line 243 of file uPD98401.h.
| #define uPD98401_VER 0x06 /* Version Number */ |
Definition at line 102 of file uPD98401.h.
| #define uPD98401_VRR 0x40301 /* VPI/VCI Reduction Register/Recv. Shutdown */ |
Definition at line 192 of file uPD98401.h.
| #define uPD98401_VRR_MASK 0x0000ffff /* VPI/VCI mask */ |
Definition at line 199 of file uPD98401.h.
| #define uPD98401_VRR_SDM 0x80000000 /* Shutdown Mode */ |
Definition at line 196 of file uPD98401.h.
| #define uPD98401_VRR_SHIFT 0x000f0000 /* VPI/VCI Shift */ |
Definition at line 197 of file uPD98401.h.
| #define uPD98401_VRR_SHIFT_SHIFT 16 |
Definition at line 198 of file uPD98401.h.
| #define uPD98401_X | ( | n | ) | (0x40010+(n)) /* Scheduler n X */ |
Definition at line 161 of file uPD98401.h.
| #define uPD98401_Y | ( | n | ) | (0x40020+(n)) /* Scheduler n Y */ |
Definition at line 162 of file uPD98401.h.
1.8.2