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| #define | PCI_CLASS_WIRELESS_IRDA 0x0d00 |
| |
| #define | PCI_CLASS_SUBCLASS_MASK 0xffff |
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| #define | DMA_MASK_USED_BY_HW 0xffffffff |
| |
| #define | DMA_MASK_MSTRPAGE 0x00ffffff |
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| #define | MSTRPAGE_VALUE (DMA_MASK_MSTRPAGE >> 24) |
| |
| #define | IRINTR_INT_MASK (IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT) |
| |
| #define | MAX_RING_DESCR 64 /* tx, rx rings may contain up to 64 descr each */ |
| |
| #define | RINGPTR_RX_MASK (MAX_RING_DESCR-1) |
| |
| #define | RINGPTR_TX_MASK ((MAX_RING_DESCR-1)<<8) |
| |
| #define | RINGPTR_GET_RX(p) ((p)&RINGPTR_RX_MASK) |
| |
| #define | RINGPTR_GET_TX(p) (((p)&RINGPTR_TX_MASK)>>8) |
| |
| #define | BUS_TO_RINGBASE(p) (((p)>>10)&0x3fff) |
| |
| #define | SIZE_TO_BITS(num) ((((num)-1)>>2)&0x0f) |
| |
| #define | TX_RX_TO_RINGSIZE(tx, rx) ((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8)) |
| |
| #define | RINGSIZE_TO_RXSIZE(rs) ((((rs)&0x0f00)>>6)+4) |
| |
| #define | RINGSIZE_TO_TXSIZE(rs) ((((rs)&0xf000)>>10)+4) |
| |
| #define | IRENABLE_MASK 0xff00 /* Read mask */ |
| |
| #define | PHYCTL_BAUD_SHIFT 10 |
| |
| #define | PHYCTL_BAUD_MASK 0xfc00 |
| |
| #define | PHYCTL_PLSWID_SHIFT 5 |
| |
| #define | PHYCTL_PLSWID_MASK 0x03e0 |
| |
| #define | PHYCTL_PREAMB_SHIFT 0 |
| |
| #define | PHYCTL_PREAMB_MASK 0x001f |
| |
| #define | PHYCTL_TO_BAUD(bwp) (((bwp)&PHYCTL_BAUD_MASK)>>PHYCTL_BAUD_SHIFT) |
| |
| #define | PHYCTL_TO_PLSWID(bwp) (((bwp)&PHYCTL_PLSWID_MASK)>>PHYCTL_PLSWID_SHIFT) |
| |
| #define | PHYCTL_TO_PREAMB(bwp) (((bwp)&PHYCTL_PREAMB_MASK)>>PHYCTL_PREAMB_SHIFT) |
| |
| #define | BWP_TO_PHYCTL(b, w, p) |
| |
| #define | BAUD_BITS(br) ((115200/(br))-1) |
| |
| #define | PHYCTL_SIR(br, ws, cs) BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0) |
| |
| #define | PHYCTL_MIR(cs) BWP_TO_PHYCTL(0,((cs)?9:10),1) |
| |
| #define | PHYCTL_FIR BWP_TO_PHYCTL(0,0,15) |
| |
| #define | MAX_PACKET_LENGTH 0x0fff |
| |
| #define | IRDA_MTU 2048 |
| |
| #define | IRLAP_SKB_ALLOCSIZE (1+1+IRDA_MTU) |
| |
| #define | XFER_BUF_SIZE MAX_PACKET_LENGTH |
| |
| #define | RCVBCNT_MASK 0x0fff |
| |
| #define | rd_addr rd_u.addr |
| |
| #define | rd_status rd_u.rd_s.status |
| |
| #define | RD_ACTIVE 0x80 /* descriptor owned by hw (both TX,RX) */ |
| |
| #define | RD_TX_DISCRC 0x40 /* do not send CRC (for SIR) */ |
| |
| #define | RD_TX_BADCRC 0x20 /* force a bad CRC */ |
| |
| #define | RD_TX_PULSE 0x10 /* send indication pulse after this frame (MIR/FIR) */ |
| |
| #define | RD_TX_FRCEUND 0x08 /* force underrun */ |
| |
| #define | RD_TX_CLRENTX 0x04 /* clear ENTX after this frame */ |
| |
| #define | RD_TX_UNDRN 0x01 /* TX fifo underrun (probably PCI problem) */ |
| |
| #define | RD_RX_PHYERR 0x40 /* physical encoding error */ |
| |
| #define | RD_RX_CRCERR 0x20 /* CRC error (MIR/FIR) */ |
| |
| #define | RD_RX_LENGTH 0x10 /* frame exceeds buffer length */ |
| |
| #define | RD_RX_OVER 0x08 /* RX fifo overrun (probably PCI problem) */ |
| |
| #define | RD_RX_SIRBAD 0x04 /* EOF missing: BOF follows BOF (SIR, filtered) */ |
| |
| #define | RD_RX_ERROR 0x7c /* any error in received frame */ |
| |
| #define | HW_RING_AREA_SIZE (2 * MAX_RING_DESCR * sizeof(struct ring_descr_hw)) |
| |
| #define | VLSI_TX_DROP 0x0001 |
| |
| #define | VLSI_TX_FIFO 0x0002 |
| |
| #define | VLSI_RX_DROP 0x0100 |
| |
| #define | VLSI_RX_OVER 0x0200 |
| |
| #define | VLSI_RX_LENGTH 0x0400 |
| |
| #define | VLSI_RX_FRAME 0x0800 |
| |
| #define | VLSI_RX_CRC 0x1000 |
| |
|
| enum | vlsi_pci_regs { VLSI_PCI_CLKCTL = 0x40,
VLSI_PCI_MSTRPAGE = 0x41,
VLSI_PCI_IRMISC = 0x42
} |
| |
| enum | vlsi_pci_clkctl {
CLKCTL_PD_INV = 0x04,
CLKCTL_LOCK = 0x40,
CLKCTL_EXTCLK = 0x20,
CLKCTL_XCKSEL = 0x10,
CLKCTL_CLKSTP = 0x80,
CLKCTL_WAKE = 0x08
} |
| |
| enum | vlsi_pci_irmisc {
IRMISC_IRRAIL = 0x40,
IRMISC_IRPD = 0x08,
IRMISC_UARTTST = 0x80,
IRMISC_UARTEN = 0x04,
IRMISC_UARTSEL_3f8 = 0x00,
IRMISC_UARTSEL_2f8 = 0x01,
IRMISC_UARTSEL_3e8 = 0x02,
IRMISC_UARTSEL_2e8 = 0x03
} |
| |
| enum | vlsi_pio_regs {
VLSI_PIO_IRINTR = 0x00,
VLSI_PIO_RINGPTR = 0x02,
VLSI_PIO_RINGBASE = 0x04,
VLSI_PIO_RINGSIZE = 0x06,
VLSI_PIO_PROMPT = 0x08,
VLSI_PIO_IRCFG = 0x10,
VLSI_PIO_SIRFLAG = 0x12,
VLSI_PIO_IRENABLE = 0x14,
VLSI_PIO_PHYCTL = 0x16,
VLSI_PIO_NPHYCTL = 0x18,
VLSI_PIO_MAXPKT = 0x1a,
VLSI_PIO_RCVBCNT = 0x1c
} |
| |
| enum | vlsi_pio_irintr {
IRINTR_ACTEN = 0x80,
IRINTR_ACTIVITY = 0x40,
IRINTR_RPKTEN = 0x20,
IRINTR_RPKTINT = 0x10,
IRINTR_TPKTEN = 0x08,
IRINTR_TPKTINT = 0x04,
IRINTR_OE_EN = 0x02,
IRINTR_OE_INT = 0x01
} |
| |
| enum | vlsi_pio_ircfg {
IRCFG_LOOP = 0x4000,
IRCFG_ENTX = 0x1000,
IRCFG_ENRX = 0x0800,
IRCFG_MSTR = 0x0400,
IRCFG_RXANY = 0x0200,
IRCFG_CRC16 = 0x0080,
IRCFG_FIR = 0x0040,
IRCFG_MIR = 0x0020,
IRCFG_SIR = 0x0010,
IRCFG_SIRFILT = 0x0008,
IRCFG_SIRTEST = 0x0004,
IRCFG_TXPOL = 0x0002,
IRCFG_RXPOL = 0x0001
} |
| |
| enum | vlsi_pio_irenable {
IRENABLE_PHYANDCLOCK = 0x8000,
IRENABLE_CFGER = 0x4000,
IRENABLE_FIR_ON = 0x2000,
IRENABLE_MIR_ON = 0x1000,
IRENABLE_SIR_ON = 0x0800,
IRENABLE_ENTXST = 0x0400,
IRENABLE_ENRXST = 0x0200,
IRENABLE_CRC16_ON = 0x0100
} |
| |
1.8.2