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wm8955.c
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1 /*
2  * wm8955.c -- WM8955 ALSA SoC Audio driver
3  *
4  * Copyright 2009 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <[email protected]>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <sound/wm8955.h>
29 
30 #include "wm8955.h"
31 
32 #define WM8955_NUM_SUPPLIES 4
33 static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
34  "DCVDD",
35  "DBVDD",
36  "HPVDD",
37  "AVDD",
38 };
39 
40 /* codec private data */
41 struct wm8955_priv {
42  struct regmap *regmap;
43 
44  unsigned int mclk_rate;
45 
46  int deemph;
47  int fs;
48 
49  struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
50 };
51 
52 static const struct reg_default wm8955_reg_defaults[] = {
53  { 2, 0x0079 }, /* R2 - LOUT1 volume */
54  { 3, 0x0079 }, /* R3 - ROUT1 volume */
55  { 5, 0x0008 }, /* R5 - DAC Control */
56  { 7, 0x000A }, /* R7 - Audio Interface */
57  { 8, 0x0000 }, /* R8 - Sample Rate */
58  { 10, 0x00FF }, /* R10 - Left DAC volume */
59  { 11, 0x00FF }, /* R11 - Right DAC volume */
60  { 12, 0x000F }, /* R12 - Bass control */
61  { 13, 0x000F }, /* R13 - Treble control */
62  { 23, 0x00C1 }, /* R23 - Additional control (1) */
63  { 24, 0x0000 }, /* R24 - Additional control (2) */
64  { 25, 0x0000 }, /* R25 - Power Management (1) */
65  { 26, 0x0000 }, /* R26 - Power Management (2) */
66  { 27, 0x0000 }, /* R27 - Additional Control (3) */
67  { 34, 0x0050 }, /* R34 - Left out Mix (1) */
68  { 35, 0x0050 }, /* R35 - Left out Mix (2) */
69  { 36, 0x0050 }, /* R36 - Right out Mix (1) */
70  { 37, 0x0050 }, /* R37 - Right Out Mix (2) */
71  { 38, 0x0050 }, /* R38 - Mono out Mix (1) */
72  { 39, 0x0050 }, /* R39 - Mono out Mix (2) */
73  { 40, 0x0079 }, /* R40 - LOUT2 volume */
74  { 41, 0x0079 }, /* R41 - ROUT2 volume */
75  { 42, 0x0079 }, /* R42 - MONOOUT volume */
76  { 43, 0x0000 }, /* R43 - Clocking / PLL */
77  { 44, 0x0103 }, /* R44 - PLL Control 1 */
78  { 45, 0x0024 }, /* R45 - PLL Control 2 */
79  { 46, 0x01BA }, /* R46 - PLL Control 3 */
80  { 59, 0x0000 }, /* R59 - PLL Control 4 */
81 };
82 
83 static bool wm8955_writeable(struct device *dev, unsigned int reg)
84 {
85  switch (reg) {
86  case WM8955_LOUT1_VOLUME:
87  case WM8955_ROUT1_VOLUME:
88  case WM8955_DAC_CONTROL:
89  case WM8955_AUDIO_INTERFACE:
90  case WM8955_SAMPLE_RATE:
91  case WM8955_LEFT_DAC_VOLUME:
92  case WM8955_RIGHT_DAC_VOLUME:
93  case WM8955_BASS_CONTROL:
94  case WM8955_TREBLE_CONTROL:
95  case WM8955_RESET:
96  case WM8955_ADDITIONAL_CONTROL_1:
97  case WM8955_ADDITIONAL_CONTROL_2:
98  case WM8955_POWER_MANAGEMENT_1:
99  case WM8955_POWER_MANAGEMENT_2:
100  case WM8955_ADDITIONAL_CONTROL_3:
101  case WM8955_LEFT_OUT_MIX_1:
102  case WM8955_LEFT_OUT_MIX_2:
103  case WM8955_RIGHT_OUT_MIX_1:
104  case WM8955_RIGHT_OUT_MIX_2:
105  case WM8955_MONO_OUT_MIX_1:
106  case WM8955_MONO_OUT_MIX_2:
107  case WM8955_LOUT2_VOLUME:
108  case WM8955_ROUT2_VOLUME:
109  case WM8955_MONOOUT_VOLUME:
110  case WM8955_CLOCKING_PLL:
111  case WM8955_PLL_CONTROL_1:
112  case WM8955_PLL_CONTROL_2:
113  case WM8955_PLL_CONTROL_3:
114  case WM8955_PLL_CONTROL_4:
115  return true;
116  default:
117  return false;
118  }
119 }
120 
121 static bool wm8955_volatile(struct device *dev, unsigned int reg)
122 {
123  switch (reg) {
124  case WM8955_RESET:
125  return true;
126  default:
127  return false;
128  }
129 }
130 
131 static int wm8955_reset(struct snd_soc_codec *codec)
132 {
133  return snd_soc_write(codec, WM8955_RESET, 0);
134 }
135 
136 struct pll_factors {
137  int n;
138  int k;
139  int outdiv;
140 };
141 
142 /* The size in bits of the FLL divide multiplied by 10
143  * to allow rounding later */
144 #define FIXED_FLL_SIZE ((1 << 22) * 10)
145 
146 static int wm8995_pll_factors(struct device *dev,
147  int Fref, int Fout, struct pll_factors *pll)
148 {
149  u64 Kpart;
150  unsigned int K, Ndiv, Nmod, target;
151 
152  dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
153 
154  /* The oscilator should run at should be 90-100MHz, and
155  * there's a divide by 4 plus an optional divide by 2 in the
156  * output path to generate the system clock. The clock table
157  * is sortd so we should always generate a suitable target. */
158  target = Fout * 4;
159  if (target < 90000000) {
160  pll->outdiv = 1;
161  target *= 2;
162  } else {
163  pll->outdiv = 0;
164  }
165 
166  WARN_ON(target < 90000000 || target > 100000000);
167 
168  dev_dbg(dev, "Fvco=%dHz\n", target);
169 
170  /* Now, calculate N.K */
171  Ndiv = target / Fref;
172 
173  pll->n = Ndiv;
174  Nmod = target % Fref;
175  dev_dbg(dev, "Nmod=%d\n", Nmod);
176 
177  /* Calculate fractional part - scale up so we can round. */
178  Kpart = FIXED_FLL_SIZE * (long long)Nmod;
179 
180  do_div(Kpart, Fref);
181 
182  K = Kpart & 0xFFFFFFFF;
183 
184  if ((K % 10) >= 5)
185  K += 5;
186 
187  /* Move down to proper range now rounding is done */
188  pll->k = K / 10;
189 
190  dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
191 
192  return 0;
193 }
194 
195 /* Lookup table specifying SRATE (table 25 in datasheet); some of the
196  * output frequencies have been rounded to the standard frequencies
197  * they are intended to match where the error is slight. */
198 static struct {
199  int mclk;
200  int fs;
201  int usb;
202  int sr;
203 } clock_cfgs[] = {
204  { 18432000, 8000, 0, 3, },
205  { 18432000, 12000, 0, 9, },
206  { 18432000, 16000, 0, 11, },
207  { 18432000, 24000, 0, 29, },
208  { 18432000, 32000, 0, 13, },
209  { 18432000, 48000, 0, 1, },
210  { 18432000, 96000, 0, 15, },
211 
212  { 16934400, 8018, 0, 19, },
213  { 16934400, 11025, 0, 25, },
214  { 16934400, 22050, 0, 27, },
215  { 16934400, 44100, 0, 17, },
216  { 16934400, 88200, 0, 31, },
217 
218  { 12000000, 8000, 1, 2, },
219  { 12000000, 11025, 1, 25, },
220  { 12000000, 12000, 1, 8, },
221  { 12000000, 16000, 1, 10, },
222  { 12000000, 22050, 1, 27, },
223  { 12000000, 24000, 1, 28, },
224  { 12000000, 32000, 1, 12, },
225  { 12000000, 44100, 1, 17, },
226  { 12000000, 48000, 1, 0, },
227  { 12000000, 88200, 1, 31, },
228  { 12000000, 96000, 1, 14, },
229 
230  { 12288000, 8000, 0, 2, },
231  { 12288000, 12000, 0, 8, },
232  { 12288000, 16000, 0, 10, },
233  { 12288000, 24000, 0, 28, },
234  { 12288000, 32000, 0, 12, },
235  { 12288000, 48000, 0, 0, },
236  { 12288000, 96000, 0, 14, },
237 
238  { 12289600, 8018, 0, 18, },
239  { 12289600, 11025, 0, 24, },
240  { 12289600, 22050, 0, 26, },
241  { 11289600, 44100, 0, 16, },
242  { 11289600, 88200, 0, 31, },
243 };
244 
245 static int wm8955_configure_clocking(struct snd_soc_codec *codec)
246 {
247  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
248  int i, ret, val;
249  int clocking = 0;
250  int srate = 0;
251  int sr = -1;
252  struct pll_factors pll;
253 
254  /* If we're not running a sample rate currently just pick one */
255  if (wm8955->fs == 0)
256  wm8955->fs = 8000;
257 
258  /* Can we generate an exact output? */
259  for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
260  if (wm8955->fs != clock_cfgs[i].fs)
261  continue;
262  sr = i;
263 
264  if (wm8955->mclk_rate == clock_cfgs[i].mclk)
265  break;
266  }
267 
268  /* We should never get here with an unsupported sample rate */
269  if (sr == -1) {
270  dev_err(codec->dev, "Sample rate %dHz unsupported\n",
271  wm8955->fs);
272  WARN_ON(sr == -1);
273  return -EINVAL;
274  }
275 
276  if (i == ARRAY_SIZE(clock_cfgs)) {
277  /* If we can't generate the right clock from MCLK then
278  * we should configure the PLL to supply us with an
279  * appropriate clock.
280  */
281  clocking |= WM8955_MCLKSEL;
282 
283  /* Use the last divider configuration we saw for the
284  * sample rate. */
285  ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
286  clock_cfgs[sr].mclk, &pll);
287  if (ret != 0) {
288  dev_err(codec->dev,
289  "Unable to generate %dHz from %dHz MCLK\n",
290  wm8955->fs, wm8955->mclk_rate);
291  return -EINVAL;
292  }
293 
294  snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
295  WM8955_N_MASK | WM8955_K_21_18_MASK,
296  (pll.n << WM8955_N_SHIFT) |
297  pll.k >> 18);
298  snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
299  WM8955_K_17_9_MASK,
300  (pll.k >> 9) & WM8955_K_17_9_MASK);
301  snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
302  WM8955_K_8_0_MASK,
303  pll.k & WM8955_K_8_0_MASK);
304  if (pll.k)
305  snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
306  WM8955_KEN, WM8955_KEN);
307  else
308  snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
309  WM8955_KEN, 0);
310 
311  if (pll.outdiv)
312  val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
313  else
314  val = WM8955_PLL_RB;
315 
316  /* Now start the PLL running */
317  snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
318  WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
319  snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
320  WM8955_PLLEN, WM8955_PLLEN);
321  }
322 
323  srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
324 
325  snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
326  WM8955_USB | WM8955_SR_MASK, srate);
327  snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
328  WM8955_MCLKSEL, clocking);
329 
330  return 0;
331 }
332 
333 static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
334  struct snd_kcontrol *kcontrol, int event)
335 {
336  struct snd_soc_codec *codec = w->codec;
337  int ret = 0;
338 
339  /* Always disable the clocks - if we're doing reconfiguration this
340  * avoids misclocking.
341  */
342  snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
343  WM8955_DIGENB, 0);
344  snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
345  WM8955_PLL_RB | WM8955_PLLEN, 0);
346 
347  switch (event) {
348  case SND_SOC_DAPM_POST_PMD:
349  break;
350  case SND_SOC_DAPM_PRE_PMU:
351  ret = wm8955_configure_clocking(codec);
352  break;
353  default:
354  ret = -EINVAL;
355  break;
356  }
357 
358  return ret;
359 }
360 
361 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
362 
363 static int wm8955_set_deemph(struct snd_soc_codec *codec)
364 {
365  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
366  int val, i, best;
367 
368  /* If we're using deemphasis select the nearest available sample
369  * rate.
370  */
371  if (wm8955->deemph) {
372  best = 1;
373  for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
374  if (abs(deemph_settings[i] - wm8955->fs) <
375  abs(deemph_settings[best] - wm8955->fs))
376  best = i;
377  }
378 
379  val = best << WM8955_DEEMPH_SHIFT;
380  } else {
381  val = 0;
382  }
383 
384  dev_dbg(codec->dev, "Set deemphasis %d\n", val);
385 
386  return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
387  WM8955_DEEMPH_MASK, val);
388 }
389 
390 static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
391  struct snd_ctl_elem_value *ucontrol)
392 {
393  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
394  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
395 
396  ucontrol->value.enumerated.item[0] = wm8955->deemph;
397  return 0;
398 }
399 
400 static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
401  struct snd_ctl_elem_value *ucontrol)
402 {
403  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
404  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
405  int deemph = ucontrol->value.enumerated.item[0];
406 
407  if (deemph > 1)
408  return -EINVAL;
409 
410  wm8955->deemph = deemph;
411 
412  return wm8955_set_deemph(codec);
413 }
414 
415 static const char *bass_mode_text[] = {
416  "Linear", "Adaptive",
417 };
418 
419 static const struct soc_enum bass_mode =
420  SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
421 
422 static const char *bass_cutoff_text[] = {
423  "Low", "High"
424 };
425 
426 static const struct soc_enum bass_cutoff =
427  SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
428 
429 static const char *treble_cutoff_text[] = {
430  "High", "Low"
431 };
432 
433 static const struct soc_enum treble_cutoff =
434  SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
435 
436 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
437 static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
438 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
439 static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
440 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
441 static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
442 
443 static const struct snd_kcontrol_new wm8955_snd_controls[] = {
444 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
445  WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
446 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
447  atten_tlv),
448 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
449  wm8955_get_deemph, wm8955_put_deemph),
450 
451 SOC_ENUM("Bass Mode", bass_mode),
452 SOC_ENUM("Bass Cutoff", bass_cutoff),
453 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
454 
455 SOC_ENUM("Treble Cutoff", treble_cutoff),
456 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
457 
458 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
459  bypass_tlv),
460 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
461  bypass_tlv),
462 
463 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
464  bypass_tlv),
465 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
466  bypass_tlv),
467 
468 /* Not a stereo pair so they line up with the DAPM switches */
469 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
470  mono_tlv),
471 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
472  mono_tlv),
473 
474 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
475  WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
476 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
477  WM8955_ROUT1_VOLUME, 7, 1, 0),
478 
479 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
480  WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
481 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
482  WM8955_ROUT2_VOLUME, 7, 1, 0),
483 
484 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
485 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
486 };
487 
488 static const struct snd_kcontrol_new lmixer[] = {
489 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
490 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
491 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
492 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
493 };
494 
495 static const struct snd_kcontrol_new rmixer[] = {
496 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
497 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
498 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
499 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
500 };
501 
502 static const struct snd_kcontrol_new mmixer[] = {
503 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
504 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
505 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
506 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
507 };
508 
509 static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
510 SND_SOC_DAPM_INPUT("MONOIN-"),
511 SND_SOC_DAPM_INPUT("MONOIN+"),
512 SND_SOC_DAPM_INPUT("LINEINR"),
513 SND_SOC_DAPM_INPUT("LINEINL"),
514 
515 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
516 
517 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
518  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
519 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
520 
521 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
522 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
523 
524 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
525 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
526 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
527 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
528 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
529 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
530 
531 /* The names are chosen to make the control names nice */
532 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
533  lmixer, ARRAY_SIZE(lmixer)),
534 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
535  rmixer, ARRAY_SIZE(rmixer)),
536 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
537  mmixer, ARRAY_SIZE(mmixer)),
538 
539 SND_SOC_DAPM_OUTPUT("LOUT1"),
540 SND_SOC_DAPM_OUTPUT("ROUT1"),
541 SND_SOC_DAPM_OUTPUT("LOUT2"),
542 SND_SOC_DAPM_OUTPUT("ROUT2"),
543 SND_SOC_DAPM_OUTPUT("MONOOUT"),
544 SND_SOC_DAPM_OUTPUT("OUT3"),
545 };
546 
547 static const struct snd_soc_dapm_route wm8955_dapm_routes[] = {
548  { "DACL", NULL, "SYSCLK" },
549  { "DACR", NULL, "SYSCLK" },
550 
551  { "Mono Input", NULL, "MONOIN-" },
552  { "Mono Input", NULL, "MONOIN+" },
553 
554  { "Left", "Playback Switch", "DACL" },
555  { "Left", "Right Playback Switch", "DACR" },
556  { "Left", "Bypass Switch", "LINEINL" },
557  { "Left", "Mono Switch", "Mono Input" },
558 
559  { "Right", "Playback Switch", "DACR" },
560  { "Right", "Left Playback Switch", "DACL" },
561  { "Right", "Bypass Switch", "LINEINR" },
562  { "Right", "Mono Switch", "Mono Input" },
563 
564  { "Mono", "Left Playback Switch", "DACL" },
565  { "Mono", "Right Playback Switch", "DACR" },
566  { "Mono", "Left Bypass Switch", "LINEINL" },
567  { "Mono", "Right Bypass Switch", "LINEINR" },
568 
569  { "LOUT1 PGA", NULL, "Left" },
570  { "LOUT1", NULL, "TSDEN" },
571  { "LOUT1", NULL, "LOUT1 PGA" },
572 
573  { "ROUT1 PGA", NULL, "Right" },
574  { "ROUT1", NULL, "TSDEN" },
575  { "ROUT1", NULL, "ROUT1 PGA" },
576 
577  { "LOUT2 PGA", NULL, "Left" },
578  { "LOUT2", NULL, "TSDEN" },
579  { "LOUT2", NULL, "LOUT2 PGA" },
580 
581  { "ROUT2 PGA", NULL, "Right" },
582  { "ROUT2", NULL, "TSDEN" },
583  { "ROUT2", NULL, "ROUT2 PGA" },
584 
585  { "MOUT PGA", NULL, "Mono" },
586  { "MONOOUT", NULL, "MOUT PGA" },
587 
588  /* OUT3 not currently implemented */
589  { "OUT3", NULL, "OUT3 PGA" },
590 };
591 
592 static int wm8955_hw_params(struct snd_pcm_substream *substream,
593  struct snd_pcm_hw_params *params,
594  struct snd_soc_dai *dai)
595 {
596  struct snd_soc_codec *codec = dai->codec;
597  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
598  int ret;
599  int wl;
600 
601  switch (params_format(params)) {
602  case SNDRV_PCM_FORMAT_S16_LE:
603  wl = 0;
604  break;
605  case SNDRV_PCM_FORMAT_S20_3LE:
606  wl = 0x4;
607  break;
608  case SNDRV_PCM_FORMAT_S24_LE:
609  wl = 0x8;
610  break;
611  case SNDRV_PCM_FORMAT_S32_LE:
612  wl = 0xc;
613  break;
614  default:
615  return -EINVAL;
616  }
617  snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
618  WM8955_WL_MASK, wl);
619 
620  wm8955->fs = params_rate(params);
621  wm8955_set_deemph(codec);
622 
623  /* If the chip is clocked then disable the clocks and force a
624  * reconfiguration, otherwise DAPM will power up the
625  * clocks for us later. */
626  ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
627  if (ret < 0)
628  return ret;
629  if (ret & WM8955_DIGENB) {
630  snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
631  WM8955_DIGENB, 0);
632  snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
633  WM8955_PLL_RB | WM8955_PLLEN, 0);
634 
635  wm8955_configure_clocking(codec);
636  }
637 
638  return 0;
639 }
640 
641 
642 static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
643  unsigned int freq, int dir)
644 {
645  struct snd_soc_codec *codec = dai->codec;
646  struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
647  int div;
648 
649  switch (clk_id) {
650  case WM8955_CLK_MCLK:
651  if (freq > 15000000) {
652  priv->mclk_rate = freq /= 2;
653  div = WM8955_MCLKDIV2;
654  } else {
655  priv->mclk_rate = freq;
656  div = 0;
657  }
658 
659  snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
660  WM8955_MCLKDIV2, div);
661  break;
662 
663  default:
664  return -EINVAL;
665  }
666 
667  dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
668 
669  return 0;
670 }
671 
672 static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
673 {
674  struct snd_soc_codec *codec = dai->codec;
675  u16 aif = 0;
676 
677  switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
678  case SND_SOC_DAIFMT_CBS_CFS:
679  break;
680  case SND_SOC_DAIFMT_CBM_CFM:
681  aif |= WM8955_MS;
682  break;
683  default:
684  return -EINVAL;
685  }
686 
687  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
688  case SND_SOC_DAIFMT_DSP_B:
689  aif |= WM8955_LRP;
690  case SND_SOC_DAIFMT_DSP_A:
691  aif |= 0x3;
692  break;
693  case SND_SOC_DAIFMT_I2S:
694  aif |= 0x2;
695  break;
696  case SND_SOC_DAIFMT_RIGHT_J:
697  break;
698  case SND_SOC_DAIFMT_LEFT_J:
699  aif |= 0x1;
700  break;
701  default:
702  return -EINVAL;
703  }
704 
705  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
706  case SND_SOC_DAIFMT_DSP_A:
707  case SND_SOC_DAIFMT_DSP_B:
708  /* frame inversion not valid for DSP modes */
709  switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
710  case SND_SOC_DAIFMT_NB_NF:
711  break;
712  case SND_SOC_DAIFMT_IB_NF:
713  aif |= WM8955_BCLKINV;
714  break;
715  default:
716  return -EINVAL;
717  }
718  break;
719 
720  case SND_SOC_DAIFMT_I2S:
721  case SND_SOC_DAIFMT_RIGHT_J:
722  case SND_SOC_DAIFMT_LEFT_J:
723  switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
724  case SND_SOC_DAIFMT_NB_NF:
725  break;
726  case SND_SOC_DAIFMT_IB_IF:
727  aif |= WM8955_BCLKINV | WM8955_LRP;
728  break;
729  case SND_SOC_DAIFMT_IB_NF:
730  aif |= WM8955_BCLKINV;
731  break;
732  case SND_SOC_DAIFMT_NB_IF:
733  aif |= WM8955_LRP;
734  break;
735  default:
736  return -EINVAL;
737  }
738  break;
739  default:
740  return -EINVAL;
741  }
742 
743  snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
744  WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
745  WM8955_LRP, aif);
746 
747  return 0;
748 }
749 
750 
751 static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
752 {
753  struct snd_soc_codec *codec = codec_dai->codec;
754  int val;
755 
756  if (mute)
757  val = WM8955_DACMU;
758  else
759  val = 0;
760 
761  snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
762 
763  return 0;
764 }
765 
766 static int wm8955_set_bias_level(struct snd_soc_codec *codec,
767  enum snd_soc_bias_level level)
768 {
769  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
770  int ret;
771 
772  switch (level) {
773  case SND_SOC_BIAS_ON:
774  break;
775 
776  case SND_SOC_BIAS_PREPARE:
777  /* VMID resistance 2*50k */
778  snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
779  WM8955_VMIDSEL_MASK,
780  0x1 << WM8955_VMIDSEL_SHIFT);
781 
782  /* Default bias current */
783  snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
784  WM8955_VSEL_MASK,
785  0x2 << WM8955_VSEL_SHIFT);
786  break;
787 
788  case SND_SOC_BIAS_STANDBY:
789  if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
790  ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
791  wm8955->supplies);
792  if (ret != 0) {
793  dev_err(codec->dev,
794  "Failed to enable supplies: %d\n",
795  ret);
796  return ret;
797  }
798 
799  regcache_sync(wm8955->regmap);
800 
801  /* Enable VREF and VMID */
802  snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
803  WM8955_VREF |
804  WM8955_VMIDSEL_MASK,
805  WM8955_VREF |
806  0x3 << WM8955_VREF_SHIFT);
807 
808  /* Let VMID ramp */
809  msleep(500);
810 
811  /* High resistance VROI to maintain outputs */
812  snd_soc_update_bits(codec,
813  WM8955_ADDITIONAL_CONTROL_3,
814  WM8955_VROI, WM8955_VROI);
815  }
816 
817  /* Maintain VMID with 2*250k */
818  snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
819  WM8955_VMIDSEL_MASK,
820  0x2 << WM8955_VMIDSEL_SHIFT);
821 
822  /* Minimum bias current */
823  snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
824  WM8955_VSEL_MASK, 0);
825  break;
826 
827  case SND_SOC_BIAS_OFF:
828  /* Low resistance VROI to help discharge */
829  snd_soc_update_bits(codec,
830  WM8955_ADDITIONAL_CONTROL_3,
831  WM8955_VROI, 0);
832 
833  /* Turn off VMID and VREF */
834  snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
835  WM8955_VREF |
836  WM8955_VMIDSEL_MASK, 0);
837 
838  regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
839  wm8955->supplies);
840  break;
841  }
842  codec->dapm.bias_level = level;
843  return 0;
844 }
845 
846 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
847 
848 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
849  SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
850 
851 static const struct snd_soc_dai_ops wm8955_dai_ops = {
852  .set_sysclk = wm8955_set_sysclk,
853  .set_fmt = wm8955_set_fmt,
854  .hw_params = wm8955_hw_params,
855  .digital_mute = wm8955_digital_mute,
856 };
857 
858 static struct snd_soc_dai_driver wm8955_dai = {
859  .name = "wm8955-hifi",
860  .playback = {
861  .stream_name = "Playback",
862  .channels_min = 2,
863  .channels_max = 2,
864  .rates = WM8955_RATES,
865  .formats = WM8955_FORMATS,
866  },
867  .ops = &wm8955_dai_ops,
868 };
869 
870 #ifdef CONFIG_PM
871 static int wm8955_suspend(struct snd_soc_codec *codec)
872 {
873  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
874 
875  wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
876 
877  regcache_mark_dirty(wm8955->regmap);
878 
879  return 0;
880 }
881 
882 static int wm8955_resume(struct snd_soc_codec *codec)
883 {
884  wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
885 
886  return 0;
887 }
888 #else
889 #define wm8955_suspend NULL
890 #define wm8955_resume NULL
891 #endif
892 
893 static int wm8955_probe(struct snd_soc_codec *codec)
894 {
895  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
896  struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
897  int ret, i;
898 
899  codec->control_data = wm8955->regmap;
900 
901  ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
902  if (ret != 0) {
903  dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
904  return ret;
905  }
906 
907  for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
908  wm8955->supplies[i].supply = wm8955_supply_names[i];
909 
910  ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
911  wm8955->supplies);
912  if (ret != 0) {
913  dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
914  return ret;
915  }
916 
917  ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
918  wm8955->supplies);
919  if (ret != 0) {
920  dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
921  goto err_get;
922  }
923 
924  ret = wm8955_reset(codec);
925  if (ret < 0) {
926  dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
927  goto err_enable;
928  }
929 
930  /* Change some default settings - latch VU and enable ZC */
931  snd_soc_update_bits(codec, WM8955_LEFT_DAC_VOLUME,
932  WM8955_LDVU, WM8955_LDVU);
933  snd_soc_update_bits(codec, WM8955_RIGHT_DAC_VOLUME,
934  WM8955_RDVU, WM8955_RDVU);
935  snd_soc_update_bits(codec, WM8955_LOUT1_VOLUME,
936  WM8955_LO1VU | WM8955_LO1ZC,
937  WM8955_LO1VU | WM8955_LO1ZC);
938  snd_soc_update_bits(codec, WM8955_ROUT1_VOLUME,
939  WM8955_RO1VU | WM8955_RO1ZC,
940  WM8955_RO1VU | WM8955_RO1ZC);
941  snd_soc_update_bits(codec, WM8955_LOUT2_VOLUME,
942  WM8955_LO2VU | WM8955_LO2ZC,
943  WM8955_LO2VU | WM8955_LO2ZC);
944  snd_soc_update_bits(codec, WM8955_ROUT2_VOLUME,
945  WM8955_RO2VU | WM8955_RO2ZC,
946  WM8955_RO2VU | WM8955_RO2ZC);
947  snd_soc_update_bits(codec, WM8955_MONOOUT_VOLUME,
948  WM8955_MOZC, WM8955_MOZC);
949 
950  /* Also enable adaptive bass boost by default */
951  snd_soc_update_bits(codec, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
952 
953  /* Set platform data values */
954  if (pdata) {
955  if (pdata->out2_speaker)
956  snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_2,
957  WM8955_ROUT2INV, WM8955_ROUT2INV);
958 
959  if (pdata->monoin_diff)
960  snd_soc_update_bits(codec, WM8955_MONO_OUT_MIX_1,
961  WM8955_DMEN, WM8955_DMEN);
962  }
963 
964  wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
965 
966  /* Bias level configuration will have done an extra enable */
967  regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
968 
969  return 0;
970 
971 err_enable:
972  regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
973 err_get:
974  regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
975  return ret;
976 }
977 
978 static int wm8955_remove(struct snd_soc_codec *codec)
979 {
980  struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
981 
982  wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
983  regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
984  return 0;
985 }
986 
987 static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
988  .probe = wm8955_probe,
989  .remove = wm8955_remove,
990  .suspend = wm8955_suspend,
991  .resume = wm8955_resume,
992  .set_bias_level = wm8955_set_bias_level,
993 
994  .controls = wm8955_snd_controls,
995  .num_controls = ARRAY_SIZE(wm8955_snd_controls),
996  .dapm_widgets = wm8955_dapm_widgets,
997  .num_dapm_widgets = ARRAY_SIZE(wm8955_dapm_widgets),
998  .dapm_routes = wm8955_dapm_routes,
999  .num_dapm_routes = ARRAY_SIZE(wm8955_dapm_routes),
1000 };
1001 
1002 static const struct regmap_config wm8955_regmap = {
1003  .reg_bits = 7,
1004  .val_bits = 9,
1005 
1006  .max_register = WM8955_MAX_REGISTER,
1007  .volatile_reg = wm8955_volatile,
1008  .writeable_reg = wm8955_writeable,
1009 
1010  .cache_type = REGCACHE_RBTREE,
1011  .reg_defaults = wm8955_reg_defaults,
1012  .num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults),
1013 };
1014 
1015 static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
1016  const struct i2c_device_id *id)
1017 {
1018  struct wm8955_priv *wm8955;
1019  int ret;
1020 
1021  wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv),
1022  GFP_KERNEL);
1023  if (wm8955 == NULL)
1024  return -ENOMEM;
1025 
1026  wm8955->regmap = regmap_init_i2c(i2c, &wm8955_regmap);
1027  if (IS_ERR(wm8955->regmap)) {
1028  ret = PTR_ERR(wm8955->regmap);
1029  dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1030  ret);
1031  return ret;
1032  }
1033 
1034  i2c_set_clientdata(i2c, wm8955);
1035 
1036  ret = snd_soc_register_codec(&i2c->dev,
1037  &soc_codec_dev_wm8955, &wm8955_dai, 1);
1038  if (ret != 0)
1039  goto err;
1040 
1041  return ret;
1042 
1043 err:
1044  regmap_exit(wm8955->regmap);
1045  return ret;
1046 }
1047 
1048 static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1049 {
1050  struct wm8955_priv *wm8955 = i2c_get_clientdata(client);
1051 
1052  snd_soc_unregister_codec(&client->dev);
1053  regmap_exit(wm8955->regmap);
1054 
1055  return 0;
1056 }
1057 
1058 static const struct i2c_device_id wm8955_i2c_id[] = {
1059  { "wm8955", 0 },
1060  { }
1061 };
1062 MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1063 
1064 static struct i2c_driver wm8955_i2c_driver = {
1065  .driver = {
1066  .name = "wm8955",
1067  .owner = THIS_MODULE,
1068  },
1069  .probe = wm8955_i2c_probe,
1070  .remove = __devexit_p(wm8955_i2c_remove),
1071  .id_table = wm8955_i2c_id,
1072 };
1073 
1074 module_i2c_driver(wm8955_i2c_driver);
1075 
1076 MODULE_DESCRIPTION("ASoC WM8955 driver");
1077 MODULE_AUTHOR("Mark Brown <[email protected]>");
1078 MODULE_LICENSE("GPL");
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