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| #define | FIRMWARE_9600 "yam/9600.bin" |
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| #define | FIRMWARE_1200 "yam/1200.bin" |
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| #define | YAM_9600 1 |
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| #define | YAM_1200 2 |
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| #define | NR_PORTS 4 |
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| #define | YAM_MAGIC 0xF10A7654 |
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| #define | TX_OFF 0 |
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| #define | TX_HEAD 1 |
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| #define | TX_DATA 2 |
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| #define | TX_CRC1 3 |
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| #define | TX_CRC2 4 |
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| #define | TX_TAIL 5 |
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| #define | YAM_MAX_FRAME 1024 |
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| #define | DEFAULT_BITRATE 9600 /* bps */ |
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| #define | DEFAULT_HOLDD 10 /* sec */ |
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| #define | DEFAULT_TXD 300 /* ms */ |
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| #define | DEFAULT_TXTAIL 10 /* ms */ |
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| #define | DEFAULT_SLOT 100 /* ms */ |
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| #define | DEFAULT_PERS 64 /* 0->255 */ |
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| #define | RBR(iobase) (iobase+0) |
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| #define | THR(iobase) (iobase+0) |
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| #define | IER(iobase) (iobase+1) |
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| #define | IIR(iobase) (iobase+2) |
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| #define | FCR(iobase) (iobase+2) |
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| #define | LCR(iobase) (iobase+3) |
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| #define | MCR(iobase) (iobase+4) |
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| #define | LSR(iobase) (iobase+5) |
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| #define | MSR(iobase) (iobase+6) |
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| #define | SCR(iobase) (iobase+7) |
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| #define | DLL(iobase) (iobase+0) |
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| #define | DLM(iobase) (iobase+1) |
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| #define | YAM_EXTENT 8 |
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| #define | IIR_NOPEND 1 |
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| #define | IIR_MSR 0 |
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| #define | IIR_TX 2 |
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| #define | IIR_RX 4 |
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| #define | IIR_LSR 6 |
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| #define | IIR_TIMEOUT 12 /* Fifo mode only */ |
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| #define | IIR_MASK 0x0F |
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| #define | IER_RX 1 /* enable rx interrupt */ |
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| #define | IER_TX 2 /* enable tx interrupt */ |
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| #define | IER_LSR 4 /* enable line status interrupts */ |
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| #define | IER_MSR 8 /* enable modem status interrupts */ |
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| #define | MCR_DTR 0x01 /* DTR output */ |
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| #define | MCR_RTS 0x02 /* RTS output */ |
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| #define | MCR_OUT1 0x04 /* OUT1 output (not accessible in RS232) */ |
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| #define | MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */ |
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| #define | MCR_LOOP 0x10 /* Loopback enable */ |
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| #define | MSR_DCTS 0x01 /* Delta CTS input */ |
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| #define | MSR_DDSR 0x02 /* Delta DSR */ |
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| #define | MSR_DRIN 0x04 /* Delta RI */ |
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| #define | MSR_DDCD 0x08 /* Delta DCD */ |
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| #define | MSR_CTS 0x10 /* CTS input */ |
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| #define | MSR_DSR 0x20 /* DSR input */ |
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| #define | MSR_RING 0x40 /* RI input */ |
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| #define | MSR_DCD 0x80 /* DCD input */ |
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| #define | LSR_RXC 0x01 |
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| #define | LSR_OE 0x02 |
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| #define | LSR_PE 0x04 |
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| #define | LSR_FE 0x08 |
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| #define | LSR_BREAK 0x10 |
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| #define | LSR_THRE 0x20 |
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| #define | LSR_TSRE 0x40 |
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| #define | LCR_DLAB 0x80 |
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| #define | LCR_BREAK 0x40 |
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| #define | LCR_PZERO 0x28 |
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| #define | LCR_PEVEN 0x18 |
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| #define | LCR_PODD 0x08 |
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| #define | LCR_STOP1 0x00 |
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| #define | LCR_STOP2 0x04 |
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| #define | LCR_BIT5 0x00 |
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| #define | LCR_BIT6 0x02 |
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| #define | LCR_BIT7 0x01 |
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| #define | LCR_BIT8 0x03 |
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| #define | TX_RDY MSR_DCTS /* transmitter ready to send */ |
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| #define | RX_DCD MSR_DCD /* carrier detect */ |
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| #define | RX_FLAG MSR_RING /* hdlc flag received */ |
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| #define | FPGA_DONE MSR_DSR /* FPGA is configured */ |
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| #define | PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */ |
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| #define | PTT_OFF (MCR_DTR|MCR_OUT2) /* release PTT */ |
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| #define | ENABLE_RXINT IER_RX /* enable uart rx interrupt during rx */ |
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| #define | ENABLE_TXINT IER_MSR /* enable uart ms interrupt during tx */ |
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| #define | ENABLE_RTXINT (IER_RX|IER_MSR) /* full duplex operations */ |
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1.8.2