1.7.6.1Copyright © 2003-2014 University of Illinois at Urbana-Champaign. All Rights Reserved.
LLVM API Documentation
00001 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 00010 #include "llvm/MC/MCDisassembler.h" 00011 #include "MCTargetDesc/ARMAddressingModes.h" 00012 #include "MCTargetDesc/ARMBaseInfo.h" 00013 #include "MCTargetDesc/ARMMCExpr.h" 00014 #include "llvm/MC/MCContext.h" 00015 #include "llvm/MC/MCExpr.h" 00016 #include "llvm/MC/MCFixedLenDisassembler.h" 00017 #include "llvm/MC/MCInst.h" 00018 #include "llvm/MC/MCInstrDesc.h" 00019 #include "llvm/MC/MCSubtargetInfo.h" 00020 #include "llvm/Support/Debug.h" 00021 #include "llvm/Support/ErrorHandling.h" 00022 #include "llvm/Support/LEB128.h" 00023 #include "llvm/Support/MemoryObject.h" 00024 #include "llvm/Support/TargetRegistry.h" 00025 #include "llvm/Support/raw_ostream.h" 00026 #include <vector> 00027 00028 using namespace llvm; 00029 00030 #define DEBUG_TYPE "arm-disassembler" 00031 00032 typedef MCDisassembler::DecodeStatus DecodeStatus; 00033 00034 namespace { 00035 // Handles the condition code status of instructions in IT blocks 00036 class ITStatus 00037 { 00038 public: 00039 // Returns the condition code for instruction in IT block 00040 unsigned getITCC() { 00041 unsigned CC = ARMCC::AL; 00042 if (instrInITBlock()) 00043 CC = ITStates.back(); 00044 return CC; 00045 } 00046 00047 // Advances the IT block state to the next T or E 00048 void advanceITState() { 00049 ITStates.pop_back(); 00050 } 00051 00052 // Returns true if the current instruction is in an IT block 00053 bool instrInITBlock() { 00054 return !ITStates.empty(); 00055 } 00056 00057 // Returns true if current instruction is the last instruction in an IT block 00058 bool instrLastInITBlock() { 00059 return ITStates.size() == 1; 00060 } 00061 00062 // Called when decoding an IT instruction. Sets the IT state for the following 00063 // instructions that for the IT block. Firstcond and Mask correspond to the 00064 // fields in the IT instruction encoding. 00065 void setITState(char Firstcond, char Mask) { 00066 // (3 - the number of trailing zeros) is the number of then / else. 00067 unsigned CondBit0 = Firstcond & 1; 00068 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 00069 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 00070 assert(NumTZ <= 3 && "Invalid IT mask!"); 00071 // push condition codes onto the stack the correct order for the pops 00072 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 00073 bool T = ((Mask >> Pos) & 1) == CondBit0; 00074 if (T) 00075 ITStates.push_back(CCBits); 00076 else 00077 ITStates.push_back(CCBits ^ 1); 00078 } 00079 ITStates.push_back(CCBits); 00080 } 00081 00082 private: 00083 std::vector<unsigned char> ITStates; 00084 }; 00085 } 00086 00087 namespace { 00088 /// ARMDisassembler - ARM disassembler for all ARM platforms. 00089 class ARMDisassembler : public MCDisassembler { 00090 public: 00091 /// Constructor - Initializes the disassembler. 00092 /// 00093 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 00094 MCDisassembler(STI, Ctx) { 00095 } 00096 00097 ~ARMDisassembler() { 00098 } 00099 00100 /// getInstruction - See MCDisassembler. 00101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 00102 const MemoryObject ®ion, uint64_t address, 00103 raw_ostream &vStream, 00104 raw_ostream &cStream) const override; 00105 }; 00106 00107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 00108 class ThumbDisassembler : public MCDisassembler { 00109 public: 00110 /// Constructor - Initializes the disassembler. 00111 /// 00112 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 00113 MCDisassembler(STI, Ctx) { 00114 } 00115 00116 ~ThumbDisassembler() { 00117 } 00118 00119 /// getInstruction - See MCDisassembler. 00120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 00121 const MemoryObject ®ion, uint64_t address, 00122 raw_ostream &vStream, 00123 raw_ostream &cStream) const override; 00124 00125 private: 00126 mutable ITStatus ITBlock; 00127 DecodeStatus AddThumbPredicate(MCInst&) const; 00128 void UpdateThumbVFPPredicate(MCInst&) const; 00129 }; 00130 } 00131 00132 static bool Check(DecodeStatus &Out, DecodeStatus In) { 00133 switch (In) { 00134 case MCDisassembler::Success: 00135 // Out stays the same. 00136 return true; 00137 case MCDisassembler::SoftFail: 00138 Out = In; 00139 return true; 00140 case MCDisassembler::Fail: 00141 Out = In; 00142 return false; 00143 } 00144 llvm_unreachable("Invalid DecodeStatus!"); 00145 } 00146 00147 00148 // Forward declare these because the autogenerated code will reference them. 00149 // Definitions are further down. 00150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00151 uint64_t Address, const void *Decoder); 00152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 00153 unsigned RegNo, uint64_t Address, 00154 const void *Decoder); 00155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 00156 unsigned RegNo, uint64_t Address, 00157 const void *Decoder); 00158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00159 uint64_t Address, const void *Decoder); 00160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00161 uint64_t Address, const void *Decoder); 00162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00163 uint64_t Address, const void *Decoder); 00164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 00165 uint64_t Address, const void *Decoder); 00166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 00167 uint64_t Address, const void *Decoder); 00168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 00169 uint64_t Address, const void *Decoder); 00170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 00171 uint64_t Address, const void *Decoder); 00172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 00173 unsigned RegNo, 00174 uint64_t Address, 00175 const void *Decoder); 00176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 00177 uint64_t Address, const void *Decoder); 00178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 00179 uint64_t Address, const void *Decoder); 00180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 00181 unsigned RegNo, uint64_t Address, 00182 const void *Decoder); 00183 00184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 00185 uint64_t Address, const void *Decoder); 00186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 00187 uint64_t Address, const void *Decoder); 00188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 00189 uint64_t Address, const void *Decoder); 00190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 00191 uint64_t Address, const void *Decoder); 00192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 00193 uint64_t Address, const void *Decoder); 00194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 00195 uint64_t Address, const void *Decoder); 00196 00197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 00198 uint64_t Address, const void *Decoder); 00199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 00200 uint64_t Address, const void *Decoder); 00201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 00202 unsigned Insn, 00203 uint64_t Address, 00204 const void *Decoder); 00205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 00206 uint64_t Address, const void *Decoder); 00207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 00208 uint64_t Address, const void *Decoder); 00209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 00210 uint64_t Address, const void *Decoder); 00211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 00212 uint64_t Address, const void *Decoder); 00213 00214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 00215 unsigned Insn, 00216 uint64_t Adddress, 00217 const void *Decoder); 00218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 00219 uint64_t Address, const void *Decoder); 00220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 00221 uint64_t Address, const void *Decoder); 00222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 00223 uint64_t Address, const void *Decoder); 00224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 00225 uint64_t Address, const void *Decoder); 00226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 00227 uint64_t Address, const void *Decoder); 00228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 00229 uint64_t Address, const void *Decoder); 00230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 00231 uint64_t Address, const void *Decoder); 00232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 00233 uint64_t Address, const void *Decoder); 00234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 00235 uint64_t Address, const void *Decoder); 00236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 00237 uint64_t Address, const void *Decoder); 00238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 00239 uint64_t Address, const void *Decoder); 00240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 00241 uint64_t Address, const void *Decoder); 00242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 00243 uint64_t Address, const void *Decoder); 00244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 00245 uint64_t Address, const void *Decoder); 00246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 00247 uint64_t Address, const void *Decoder); 00248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 00249 uint64_t Address, const void *Decoder); 00250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 00251 uint64_t Address, const void *Decoder); 00252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 00253 uint64_t Address, const void *Decoder); 00254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 00255 uint64_t Address, const void *Decoder); 00256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 00257 uint64_t Address, const void *Decoder); 00258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 00259 uint64_t Address, const void *Decoder); 00260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 00261 uint64_t Address, const void *Decoder); 00262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 00263 uint64_t Address, const void *Decoder); 00264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 00265 uint64_t Address, const void *Decoder); 00266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 00267 uint64_t Address, const void *Decoder); 00268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 00269 uint64_t Address, const void *Decoder); 00270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 00271 uint64_t Address, const void *Decoder); 00272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 00273 uint64_t Address, const void *Decoder); 00274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 00275 uint64_t Address, const void *Decoder); 00276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 00277 uint64_t Address, const void *Decoder); 00278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 00279 uint64_t Address, const void *Decoder); 00280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 00281 uint64_t Address, const void *Decoder); 00282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 00283 uint64_t Address, const void *Decoder); 00284 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 00285 uint64_t Address, const void *Decoder); 00286 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 00287 uint64_t Address, const void *Decoder); 00288 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 00289 uint64_t Address, const void *Decoder); 00290 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 00291 uint64_t Address, const void *Decoder); 00292 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 00293 uint64_t Address, const void *Decoder); 00294 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 00295 uint64_t Address, const void *Decoder); 00296 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 00297 uint64_t Address, const void *Decoder); 00298 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 00299 uint64_t Address, const void *Decoder); 00300 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 00301 uint64_t Address, const void *Decoder); 00302 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 00303 uint64_t Address, const void *Decoder); 00304 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 00305 uint64_t Address, const void *Decoder); 00306 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 00307 uint64_t Address, const void *Decoder); 00308 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 00309 uint64_t Address, const void *Decoder); 00310 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 00311 uint64_t Address, const void *Decoder); 00312 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 00313 uint64_t Address, const void *Decoder); 00314 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 00315 uint64_t Address, const void *Decoder); 00316 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 00317 uint64_t Address, const void *Decoder); 00318 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 00319 uint64_t Address, const void *Decoder); 00320 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 00321 uint64_t Address, const void *Decoder); 00322 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 00323 uint64_t Address, const void *Decoder); 00324 00325 00326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 00327 uint64_t Address, const void *Decoder); 00328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 00329 uint64_t Address, const void *Decoder); 00330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 00331 uint64_t Address, const void *Decoder); 00332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 00333 uint64_t Address, const void *Decoder); 00334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 00335 uint64_t Address, const void *Decoder); 00336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 00337 uint64_t Address, const void *Decoder); 00338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 00339 uint64_t Address, const void *Decoder); 00340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 00341 uint64_t Address, const void *Decoder); 00342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 00343 uint64_t Address, const void *Decoder); 00344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 00345 uint64_t Address, const void *Decoder); 00346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 00347 uint64_t Address, const void* Decoder); 00348 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 00349 uint64_t Address, const void* Decoder); 00350 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 00351 uint64_t Address, const void* Decoder); 00352 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 00353 uint64_t Address, const void* Decoder); 00354 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 00355 uint64_t Address, const void *Decoder); 00356 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 00357 uint64_t Address, const void *Decoder); 00358 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 00359 uint64_t Address, const void *Decoder); 00360 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 00361 uint64_t Address, const void *Decoder); 00362 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 00363 uint64_t Address, const void *Decoder); 00364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 00365 uint64_t Address, const void *Decoder); 00366 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 00367 uint64_t Address, const void *Decoder); 00368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 00369 uint64_t Address, const void *Decoder); 00370 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 00371 uint64_t Address, const void *Decoder); 00372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 00373 uint64_t Address, const void *Decoder); 00374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 00375 uint64_t Address, const void *Decoder); 00376 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 00377 uint64_t Address, const void *Decoder); 00378 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 00379 uint64_t Address, const void *Decoder); 00380 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 00381 uint64_t Address, const void *Decoder); 00382 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 00383 uint64_t Address, const void *Decoder); 00384 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 00385 uint64_t Address, const void *Decoder); 00386 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 00387 uint64_t Address, const void *Decoder); 00388 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 00389 uint64_t Address, const void *Decoder); 00390 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 00391 uint64_t Address, const void *Decoder); 00392 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 00393 uint64_t Address, const void *Decoder); 00394 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 00395 uint64_t Address, const void *Decoder); 00396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 00397 uint64_t Address, const void *Decoder); 00398 00399 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 00400 uint64_t Address, const void *Decoder); 00401 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 00402 uint64_t Address, const void *Decoder); 00403 #include "ARMGenDisassemblerTables.inc" 00404 00405 static MCDisassembler *createARMDisassembler(const Target &T, 00406 const MCSubtargetInfo &STI, 00407 MCContext &Ctx) { 00408 return new ARMDisassembler(STI, Ctx); 00409 } 00410 00411 static MCDisassembler *createThumbDisassembler(const Target &T, 00412 const MCSubtargetInfo &STI, 00413 MCContext &Ctx) { 00414 return new ThumbDisassembler(STI, Ctx); 00415 } 00416 00417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 00418 const MemoryObject &Region, 00419 uint64_t Address, 00420 raw_ostream &os, 00421 raw_ostream &cs) const { 00422 CommentStream = &cs; 00423 00424 uint8_t bytes[4]; 00425 00426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 00427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 00428 00429 // We want to read exactly 4 bytes of data. 00430 if (Region.readBytes(Address, 4, bytes) == -1) { 00431 Size = 0; 00432 return MCDisassembler::Fail; 00433 } 00434 00435 // Encoded as a small-endian 32-bit word in the stream. 00436 uint32_t insn = (bytes[3] << 24) | 00437 (bytes[2] << 16) | 00438 (bytes[1] << 8) | 00439 (bytes[0] << 0); 00440 00441 // Calling the auto-generated decoder function. 00442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 00443 Address, this, STI); 00444 if (result != MCDisassembler::Fail) { 00445 Size = 4; 00446 return result; 00447 } 00448 00449 // VFP and NEON instructions, similarly, are shared between ARM 00450 // and Thumb modes. 00451 MI.clear(); 00452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 00453 if (result != MCDisassembler::Fail) { 00454 Size = 4; 00455 return result; 00456 } 00457 00458 MI.clear(); 00459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); 00460 if (result != MCDisassembler::Fail) { 00461 Size = 4; 00462 return result; 00463 } 00464 00465 MI.clear(); 00466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 00467 this, STI); 00468 if (result != MCDisassembler::Fail) { 00469 Size = 4; 00470 // Add a fake predicate operand, because we share these instruction 00471 // definitions with Thumb2 where these instructions are predicable. 00472 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 00473 return MCDisassembler::Fail; 00474 return result; 00475 } 00476 00477 MI.clear(); 00478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 00479 this, STI); 00480 if (result != MCDisassembler::Fail) { 00481 Size = 4; 00482 // Add a fake predicate operand, because we share these instruction 00483 // definitions with Thumb2 where these instructions are predicable. 00484 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 00485 return MCDisassembler::Fail; 00486 return result; 00487 } 00488 00489 MI.clear(); 00490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 00491 this, STI); 00492 if (result != MCDisassembler::Fail) { 00493 Size = 4; 00494 // Add a fake predicate operand, because we share these instruction 00495 // definitions with Thumb2 where these instructions are predicable. 00496 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 00497 return MCDisassembler::Fail; 00498 return result; 00499 } 00500 00501 MI.clear(); 00502 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address, 00503 this, STI); 00504 if (result != MCDisassembler::Fail) { 00505 Size = 4; 00506 return result; 00507 } 00508 00509 MI.clear(); 00510 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address, 00511 this, STI); 00512 if (result != MCDisassembler::Fail) { 00513 Size = 4; 00514 return result; 00515 } 00516 00517 MI.clear(); 00518 Size = 0; 00519 return MCDisassembler::Fail; 00520 } 00521 00522 namespace llvm { 00523 extern const MCInstrDesc ARMInsts[]; 00524 } 00525 00526 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 00527 /// immediate Value in the MCInst. The immediate Value has had any PC 00528 /// adjustment made by the caller. If the instruction is a branch instruction 00529 /// then isBranch is true, else false. If the getOpInfo() function was set as 00530 /// part of the setupForSymbolicDisassembly() call then that function is called 00531 /// to get any symbolic information at the Address for this instruction. If 00532 /// that returns non-zero then the symbolic information it returns is used to 00533 /// create an MCExpr and that is added as an operand to the MCInst. If 00534 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 00535 /// Value is done and if a symbol is found an MCExpr is created with that, else 00536 /// an MCExpr with Value is created. This function returns true if it adds an 00537 /// operand to the MCInst and false otherwise. 00538 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 00539 bool isBranch, uint64_t InstSize, 00540 MCInst &MI, const void *Decoder) { 00541 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 00542 // FIXME: Does it make sense for value to be negative? 00543 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 00544 /* Offset */ 0, InstSize); 00545 } 00546 00547 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 00548 /// referenced by a load instruction with the base register that is the Pc. 00549 /// These can often be values in a literal pool near the Address of the 00550 /// instruction. The Address of the instruction and its immediate Value are 00551 /// used as a possible literal pool entry. The SymbolLookUp call back will 00552 /// return the name of a symbol referenced by the literal pool's entry if 00553 /// the referenced address is that of a symbol. Or it will return a pointer to 00554 /// a literal 'C' string if the referenced address of the literal pool's entry 00555 /// is an address into a section with 'C' string literals. 00556 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 00557 const void *Decoder) { 00558 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 00559 Dis->tryAddingPcLoadReferenceComment(Value, Address); 00560 } 00561 00562 // Thumb1 instructions don't have explicit S bits. Rather, they 00563 // implicitly set CPSR. Since it's not represented in the encoding, the 00564 // auto-generated decoder won't inject the CPSR operand. We need to fix 00565 // that as a post-pass. 00566 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 00567 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 00568 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 00569 MCInst::iterator I = MI.begin(); 00570 for (unsigned i = 0; i < NumOps; ++i, ++I) { 00571 if (I == MI.end()) break; 00572 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 00573 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 00574 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 00575 return; 00576 } 00577 } 00578 00579 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 00580 } 00581 00582 // Most Thumb instructions don't have explicit predicates in the 00583 // encoding, but rather get their predicates from IT context. We need 00584 // to fix up the predicate operands using this context information as a 00585 // post-pass. 00586 MCDisassembler::DecodeStatus 00587 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 00588 MCDisassembler::DecodeStatus S = Success; 00589 00590 // A few instructions actually have predicates encoded in them. Don't 00591 // try to overwrite it if we're seeing one of those. 00592 switch (MI.getOpcode()) { 00593 case ARM::tBcc: 00594 case ARM::t2Bcc: 00595 case ARM::tCBZ: 00596 case ARM::tCBNZ: 00597 case ARM::tCPS: 00598 case ARM::t2CPS3p: 00599 case ARM::t2CPS2p: 00600 case ARM::t2CPS1p: 00601 case ARM::tMOVSr: 00602 case ARM::tSETEND: 00603 // Some instructions (mostly conditional branches) are not 00604 // allowed in IT blocks. 00605 if (ITBlock.instrInITBlock()) 00606 S = SoftFail; 00607 else 00608 return Success; 00609 break; 00610 case ARM::tB: 00611 case ARM::t2B: 00612 case ARM::t2TBB: 00613 case ARM::t2TBH: 00614 // Some instructions (mostly unconditional branches) can 00615 // only appears at the end of, or outside of, an IT. 00616 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 00617 S = SoftFail; 00618 break; 00619 default: 00620 break; 00621 } 00622 00623 // If we're in an IT block, base the predicate on that. Otherwise, 00624 // assume a predicate of AL. 00625 unsigned CC; 00626 CC = ITBlock.getITCC(); 00627 if (CC == 0xF) 00628 CC = ARMCC::AL; 00629 if (ITBlock.instrInITBlock()) 00630 ITBlock.advanceITState(); 00631 00632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 00633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 00634 MCInst::iterator I = MI.begin(); 00635 for (unsigned i = 0; i < NumOps; ++i, ++I) { 00636 if (I == MI.end()) break; 00637 if (OpInfo[i].isPredicate()) { 00638 I = MI.insert(I, MCOperand::CreateImm(CC)); 00639 ++I; 00640 if (CC == ARMCC::AL) 00641 MI.insert(I, MCOperand::CreateReg(0)); 00642 else 00643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 00644 return S; 00645 } 00646 } 00647 00648 I = MI.insert(I, MCOperand::CreateImm(CC)); 00649 ++I; 00650 if (CC == ARMCC::AL) 00651 MI.insert(I, MCOperand::CreateReg(0)); 00652 else 00653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 00654 00655 return S; 00656 } 00657 00658 // Thumb VFP instructions are a special case. Because we share their 00659 // encodings between ARM and Thumb modes, and they are predicable in ARM 00660 // mode, the auto-generated decoder will give them an (incorrect) 00661 // predicate operand. We need to rewrite these operands based on the IT 00662 // context as a post-pass. 00663 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 00664 unsigned CC; 00665 CC = ITBlock.getITCC(); 00666 if (ITBlock.instrInITBlock()) 00667 ITBlock.advanceITState(); 00668 00669 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 00670 MCInst::iterator I = MI.begin(); 00671 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 00672 for (unsigned i = 0; i < NumOps; ++i, ++I) { 00673 if (OpInfo[i].isPredicate() ) { 00674 I->setImm(CC); 00675 ++I; 00676 if (CC == ARMCC::AL) 00677 I->setReg(0); 00678 else 00679 I->setReg(ARM::CPSR); 00680 return; 00681 } 00682 } 00683 } 00684 00685 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 00686 const MemoryObject &Region, 00687 uint64_t Address, 00688 raw_ostream &os, 00689 raw_ostream &cs) const { 00690 CommentStream = &cs; 00691 00692 uint8_t bytes[4]; 00693 00694 assert((STI.getFeatureBits() & ARM::ModeThumb) && 00695 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 00696 00697 // We want to read exactly 2 bytes of data. 00698 if (Region.readBytes(Address, 2, bytes) == -1) { 00699 Size = 0; 00700 return MCDisassembler::Fail; 00701 } 00702 00703 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 00704 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 00705 Address, this, STI); 00706 if (result != MCDisassembler::Fail) { 00707 Size = 2; 00708 Check(result, AddThumbPredicate(MI)); 00709 return result; 00710 } 00711 00712 MI.clear(); 00713 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 00714 Address, this, STI); 00715 if (result) { 00716 Size = 2; 00717 bool InITBlock = ITBlock.instrInITBlock(); 00718 Check(result, AddThumbPredicate(MI)); 00719 AddThumb1SBit(MI, InITBlock); 00720 return result; 00721 } 00722 00723 MI.clear(); 00724 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 00725 Address, this, STI); 00726 if (result != MCDisassembler::Fail) { 00727 Size = 2; 00728 00729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 00730 // the Thumb predicate. 00731 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 00732 result = MCDisassembler::SoftFail; 00733 00734 Check(result, AddThumbPredicate(MI)); 00735 00736 // If we find an IT instruction, we need to parse its condition 00737 // code and mask operands so that we can apply them correctly 00738 // to the subsequent instructions. 00739 if (MI.getOpcode() == ARM::t2IT) { 00740 00741 unsigned Firstcond = MI.getOperand(0).getImm(); 00742 unsigned Mask = MI.getOperand(1).getImm(); 00743 ITBlock.setITState(Firstcond, Mask); 00744 } 00745 00746 return result; 00747 } 00748 00749 // We want to read exactly 4 bytes of data. 00750 if (Region.readBytes(Address, 4, bytes) == -1) { 00751 Size = 0; 00752 return MCDisassembler::Fail; 00753 } 00754 00755 uint32_t insn32 = (bytes[3] << 8) | 00756 (bytes[2] << 0) | 00757 (bytes[1] << 24) | 00758 (bytes[0] << 16); 00759 MI.clear(); 00760 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 00761 this, STI); 00762 if (result != MCDisassembler::Fail) { 00763 Size = 4; 00764 bool InITBlock = ITBlock.instrInITBlock(); 00765 Check(result, AddThumbPredicate(MI)); 00766 AddThumb1SBit(MI, InITBlock); 00767 return result; 00768 } 00769 00770 MI.clear(); 00771 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 00772 this, STI); 00773 if (result != MCDisassembler::Fail) { 00774 Size = 4; 00775 Check(result, AddThumbPredicate(MI)); 00776 return result; 00777 } 00778 00779 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 00780 MI.clear(); 00781 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 00782 if (result != MCDisassembler::Fail) { 00783 Size = 4; 00784 UpdateThumbVFPPredicate(MI); 00785 return result; 00786 } 00787 } 00788 00789 MI.clear(); 00790 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); 00791 if (result != MCDisassembler::Fail) { 00792 Size = 4; 00793 return result; 00794 } 00795 00796 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 00797 MI.clear(); 00798 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 00799 this, STI); 00800 if (result != MCDisassembler::Fail) { 00801 Size = 4; 00802 Check(result, AddThumbPredicate(MI)); 00803 return result; 00804 } 00805 } 00806 00807 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 00808 MI.clear(); 00809 uint32_t NEONLdStInsn = insn32; 00810 NEONLdStInsn &= 0xF0FFFFFF; 00811 NEONLdStInsn |= 0x04000000; 00812 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 00813 Address, this, STI); 00814 if (result != MCDisassembler::Fail) { 00815 Size = 4; 00816 Check(result, AddThumbPredicate(MI)); 00817 return result; 00818 } 00819 } 00820 00821 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 00822 MI.clear(); 00823 uint32_t NEONDataInsn = insn32; 00824 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 00825 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 00826 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 00827 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 00828 Address, this, STI); 00829 if (result != MCDisassembler::Fail) { 00830 Size = 4; 00831 Check(result, AddThumbPredicate(MI)); 00832 return result; 00833 } 00834 00835 MI.clear(); 00836 uint32_t NEONCryptoInsn = insn32; 00837 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 00838 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 00839 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 00840 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 00841 Address, this, STI); 00842 if (result != MCDisassembler::Fail) { 00843 Size = 4; 00844 return result; 00845 } 00846 00847 MI.clear(); 00848 uint32_t NEONv8Insn = insn32; 00849 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 00850 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 00851 this, STI); 00852 if (result != MCDisassembler::Fail) { 00853 Size = 4; 00854 return result; 00855 } 00856 } 00857 00858 MI.clear(); 00859 Size = 0; 00860 return MCDisassembler::Fail; 00861 } 00862 00863 00864 extern "C" void LLVMInitializeARMDisassembler() { 00865 TargetRegistry::RegisterMCDisassembler(TheARMLETarget, 00866 createARMDisassembler); 00867 TargetRegistry::RegisterMCDisassembler(TheARMBETarget, 00868 createARMDisassembler); 00869 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget, 00870 createThumbDisassembler); 00871 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget, 00872 createThumbDisassembler); 00873 } 00874 00875 static const uint16_t GPRDecoderTable[] = { 00876 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 00877 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 00878 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 00879 ARM::R12, ARM::SP, ARM::LR, ARM::PC 00880 }; 00881 00882 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00883 uint64_t Address, const void *Decoder) { 00884 if (RegNo > 15) 00885 return MCDisassembler::Fail; 00886 00887 unsigned Register = GPRDecoderTable[RegNo]; 00888 Inst.addOperand(MCOperand::CreateReg(Register)); 00889 return MCDisassembler::Success; 00890 } 00891 00892 static DecodeStatus 00893 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 00894 uint64_t Address, const void *Decoder) { 00895 DecodeStatus S = MCDisassembler::Success; 00896 00897 if (RegNo == 15) 00898 S = MCDisassembler::SoftFail; 00899 00900 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 00901 00902 return S; 00903 } 00904 00905 static DecodeStatus 00906 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 00907 uint64_t Address, const void *Decoder) { 00908 DecodeStatus S = MCDisassembler::Success; 00909 00910 if (RegNo == 15) 00911 { 00912 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 00913 return MCDisassembler::Success; 00914 } 00915 00916 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 00917 return S; 00918 } 00919 00920 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00921 uint64_t Address, const void *Decoder) { 00922 if (RegNo > 7) 00923 return MCDisassembler::Fail; 00924 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 00925 } 00926 00927 static const uint16_t GPRPairDecoderTable[] = { 00928 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 00929 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 00930 }; 00931 00932 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 00933 uint64_t Address, const void *Decoder) { 00934 DecodeStatus S = MCDisassembler::Success; 00935 00936 if (RegNo > 13) 00937 return MCDisassembler::Fail; 00938 00939 if ((RegNo & 1) || RegNo == 0xe) 00940 S = MCDisassembler::SoftFail; 00941 00942 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 00943 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 00944 return S; 00945 } 00946 00947 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00948 uint64_t Address, const void *Decoder) { 00949 unsigned Register = 0; 00950 switch (RegNo) { 00951 case 0: 00952 Register = ARM::R0; 00953 break; 00954 case 1: 00955 Register = ARM::R1; 00956 break; 00957 case 2: 00958 Register = ARM::R2; 00959 break; 00960 case 3: 00961 Register = ARM::R3; 00962 break; 00963 case 9: 00964 Register = ARM::R9; 00965 break; 00966 case 12: 00967 Register = ARM::R12; 00968 break; 00969 default: 00970 return MCDisassembler::Fail; 00971 } 00972 00973 Inst.addOperand(MCOperand::CreateReg(Register)); 00974 return MCDisassembler::Success; 00975 } 00976 00977 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 00978 uint64_t Address, const void *Decoder) { 00979 DecodeStatus S = MCDisassembler::Success; 00980 if (RegNo == 13 || RegNo == 15) 00981 S = MCDisassembler::SoftFail; 00982 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 00983 return S; 00984 } 00985 00986 static const uint16_t SPRDecoderTable[] = { 00987 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 00988 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 00989 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 00990 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 00991 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 00992 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 00993 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 00994 ARM::S28, ARM::S29, ARM::S30, ARM::S31 00995 }; 00996 00997 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 00998 uint64_t Address, const void *Decoder) { 00999 if (RegNo > 31) 01000 return MCDisassembler::Fail; 01001 01002 unsigned Register = SPRDecoderTable[RegNo]; 01003 Inst.addOperand(MCOperand::CreateReg(Register)); 01004 return MCDisassembler::Success; 01005 } 01006 01007 static const uint16_t DPRDecoderTable[] = { 01008 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 01009 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 01010 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 01011 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 01012 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 01013 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 01014 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 01015 ARM::D28, ARM::D29, ARM::D30, ARM::D31 01016 }; 01017 01018 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 01019 uint64_t Address, const void *Decoder) { 01020 if (RegNo > 31) 01021 return MCDisassembler::Fail; 01022 01023 unsigned Register = DPRDecoderTable[RegNo]; 01024 Inst.addOperand(MCOperand::CreateReg(Register)); 01025 return MCDisassembler::Success; 01026 } 01027 01028 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 01029 uint64_t Address, const void *Decoder) { 01030 if (RegNo > 7) 01031 return MCDisassembler::Fail; 01032 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 01033 } 01034 01035 static DecodeStatus 01036 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 01037 uint64_t Address, const void *Decoder) { 01038 if (RegNo > 15) 01039 return MCDisassembler::Fail; 01040 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 01041 } 01042 01043 static const uint16_t QPRDecoderTable[] = { 01044 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 01045 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 01046 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 01047 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 01048 }; 01049 01050 01051 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 01052 uint64_t Address, const void *Decoder) { 01053 if (RegNo > 31 || (RegNo & 1) != 0) 01054 return MCDisassembler::Fail; 01055 RegNo >>= 1; 01056 01057 unsigned Register = QPRDecoderTable[RegNo]; 01058 Inst.addOperand(MCOperand::CreateReg(Register)); 01059 return MCDisassembler::Success; 01060 } 01061 01062 static const uint16_t DPairDecoderTable[] = { 01063 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 01064 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 01065 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 01066 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 01067 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 01068 ARM::Q15 01069 }; 01070 01071 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 01072 uint64_t Address, const void *Decoder) { 01073 if (RegNo > 30) 01074 return MCDisassembler::Fail; 01075 01076 unsigned Register = DPairDecoderTable[RegNo]; 01077 Inst.addOperand(MCOperand::CreateReg(Register)); 01078 return MCDisassembler::Success; 01079 } 01080 01081 static const uint16_t DPairSpacedDecoderTable[] = { 01082 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 01083 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 01084 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 01085 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 01086 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 01087 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 01088 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 01089 ARM::D28_D30, ARM::D29_D31 01090 }; 01091 01092 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 01093 unsigned RegNo, 01094 uint64_t Address, 01095 const void *Decoder) { 01096 if (RegNo > 29) 01097 return MCDisassembler::Fail; 01098 01099 unsigned Register = DPairSpacedDecoderTable[RegNo]; 01100 Inst.addOperand(MCOperand::CreateReg(Register)); 01101 return MCDisassembler::Success; 01102 } 01103 01104 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 01105 uint64_t Address, const void *Decoder) { 01106 if (Val == 0xF) return MCDisassembler::Fail; 01107 // AL predicate is not allowed on Thumb1 branches. 01108 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 01109 return MCDisassembler::Fail; 01110 Inst.addOperand(MCOperand::CreateImm(Val)); 01111 if (Val == ARMCC::AL) { 01112 Inst.addOperand(MCOperand::CreateReg(0)); 01113 } else 01114 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 01115 return MCDisassembler::Success; 01116 } 01117 01118 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 01119 uint64_t Address, const void *Decoder) { 01120 if (Val) 01121 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 01122 else 01123 Inst.addOperand(MCOperand::CreateReg(0)); 01124 return MCDisassembler::Success; 01125 } 01126 01127 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 01128 uint64_t Address, const void *Decoder) { 01129 uint32_t imm = Val & 0xFF; 01130 uint32_t rot = (Val & 0xF00) >> 7; 01131 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 01132 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 01133 return MCDisassembler::Success; 01134 } 01135 01136 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 01137 uint64_t Address, const void *Decoder) { 01138 DecodeStatus S = MCDisassembler::Success; 01139 01140 unsigned Rm = fieldFromInstruction(Val, 0, 4); 01141 unsigned type = fieldFromInstruction(Val, 5, 2); 01142 unsigned imm = fieldFromInstruction(Val, 7, 5); 01143 01144 // Register-immediate 01145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 01146 return MCDisassembler::Fail; 01147 01148 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 01149 switch (type) { 01150 case 0: 01151 Shift = ARM_AM::lsl; 01152 break; 01153 case 1: 01154 Shift = ARM_AM::lsr; 01155 break; 01156 case 2: 01157 Shift = ARM_AM::asr; 01158 break; 01159 case 3: 01160 Shift = ARM_AM::ror; 01161 break; 01162 } 01163 01164 if (Shift == ARM_AM::ror && imm == 0) 01165 Shift = ARM_AM::rrx; 01166 01167 unsigned Op = Shift | (imm << 3); 01168 Inst.addOperand(MCOperand::CreateImm(Op)); 01169 01170 return S; 01171 } 01172 01173 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 01174 uint64_t Address, const void *Decoder) { 01175 DecodeStatus S = MCDisassembler::Success; 01176 01177 unsigned Rm = fieldFromInstruction(Val, 0, 4); 01178 unsigned type = fieldFromInstruction(Val, 5, 2); 01179 unsigned Rs = fieldFromInstruction(Val, 8, 4); 01180 01181 // Register-register 01182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 01183 return MCDisassembler::Fail; 01184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 01185 return MCDisassembler::Fail; 01186 01187 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 01188 switch (type) { 01189 case 0: 01190 Shift = ARM_AM::lsl; 01191 break; 01192 case 1: 01193 Shift = ARM_AM::lsr; 01194 break; 01195 case 2: 01196 Shift = ARM_AM::asr; 01197 break; 01198 case 3: 01199 Shift = ARM_AM::ror; 01200 break; 01201 } 01202 01203 Inst.addOperand(MCOperand::CreateImm(Shift)); 01204 01205 return S; 01206 } 01207 01208 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 01209 uint64_t Address, const void *Decoder) { 01210 DecodeStatus S = MCDisassembler::Success; 01211 01212 bool NeedDisjointWriteback = false; 01213 unsigned WritebackReg = 0; 01214 switch (Inst.getOpcode()) { 01215 default: 01216 break; 01217 case ARM::LDMIA_UPD: 01218 case ARM::LDMDB_UPD: 01219 case ARM::LDMIB_UPD: 01220 case ARM::LDMDA_UPD: 01221 case ARM::t2LDMIA_UPD: 01222 case ARM::t2LDMDB_UPD: 01223 case ARM::t2STMIA_UPD: 01224 case ARM::t2STMDB_UPD: 01225 NeedDisjointWriteback = true; 01226 WritebackReg = Inst.getOperand(0).getReg(); 01227 break; 01228 } 01229 01230 // Empty register lists are not allowed. 01231 if (Val == 0) return MCDisassembler::Fail; 01232 for (unsigned i = 0; i < 16; ++i) { 01233 if (Val & (1 << i)) { 01234 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 01235 return MCDisassembler::Fail; 01236 // Writeback not allowed if Rn is in the target list. 01237 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 01238 Check(S, MCDisassembler::SoftFail); 01239 } 01240 } 01241 01242 return S; 01243 } 01244 01245 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 01246 uint64_t Address, const void *Decoder) { 01247 DecodeStatus S = MCDisassembler::Success; 01248 01249 unsigned Vd = fieldFromInstruction(Val, 8, 5); 01250 unsigned regs = fieldFromInstruction(Val, 0, 8); 01251 01252 // In case of unpredictable encoding, tweak the operands. 01253 if (regs == 0 || (Vd + regs) > 32) { 01254 regs = Vd + regs > 32 ? 32 - Vd : regs; 01255 regs = std::max( 1u, regs); 01256 S = MCDisassembler::SoftFail; 01257 } 01258 01259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 01260 return MCDisassembler::Fail; 01261 for (unsigned i = 0; i < (regs - 1); ++i) { 01262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 01263 return MCDisassembler::Fail; 01264 } 01265 01266 return S; 01267 } 01268 01269 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 01270 uint64_t Address, const void *Decoder) { 01271 DecodeStatus S = MCDisassembler::Success; 01272 01273 unsigned Vd = fieldFromInstruction(Val, 8, 5); 01274 unsigned regs = fieldFromInstruction(Val, 1, 7); 01275 01276 // In case of unpredictable encoding, tweak the operands. 01277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 01278 regs = Vd + regs > 32 ? 32 - Vd : regs; 01279 regs = std::max( 1u, regs); 01280 regs = std::min(16u, regs); 01281 S = MCDisassembler::SoftFail; 01282 } 01283 01284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 01285 return MCDisassembler::Fail; 01286 for (unsigned i = 0; i < (regs - 1); ++i) { 01287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 01288 return MCDisassembler::Fail; 01289 } 01290 01291 return S; 01292 } 01293 01294 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 01295 uint64_t Address, const void *Decoder) { 01296 // This operand encodes a mask of contiguous zeros between a specified MSB 01297 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 01298 // the mask of all bits LSB-and-lower, and then xor them to create 01299 // the mask of that's all ones on [msb, lsb]. Finally we not it to 01300 // create the final mask. 01301 unsigned msb = fieldFromInstruction(Val, 5, 5); 01302 unsigned lsb = fieldFromInstruction(Val, 0, 5); 01303 01304 DecodeStatus S = MCDisassembler::Success; 01305 if (lsb > msb) { 01306 Check(S, MCDisassembler::SoftFail); 01307 // The check above will cause the warning for the "potentially undefined 01308 // instruction encoding" but we can't build a bad MCOperand value here 01309 // with a lsb > msb or else printing the MCInst will cause a crash. 01310 lsb = msb; 01311 } 01312 01313 uint32_t msb_mask = 0xFFFFFFFF; 01314 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 01315 uint32_t lsb_mask = (1U << lsb) - 1; 01316 01317 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 01318 return S; 01319 } 01320 01321 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 01322 uint64_t Address, const void *Decoder) { 01323 DecodeStatus S = MCDisassembler::Success; 01324 01325 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01326 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 01327 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 01328 unsigned imm = fieldFromInstruction(Insn, 0, 8); 01329 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01330 unsigned U = fieldFromInstruction(Insn, 23, 1); 01331 01332 switch (Inst.getOpcode()) { 01333 case ARM::LDC_OFFSET: 01334 case ARM::LDC_PRE: 01335 case ARM::LDC_POST: 01336 case ARM::LDC_OPTION: 01337 case ARM::LDCL_OFFSET: 01338 case ARM::LDCL_PRE: 01339 case ARM::LDCL_POST: 01340 case ARM::LDCL_OPTION: 01341 case ARM::STC_OFFSET: 01342 case ARM::STC_PRE: 01343 case ARM::STC_POST: 01344 case ARM::STC_OPTION: 01345 case ARM::STCL_OFFSET: 01346 case ARM::STCL_PRE: 01347 case ARM::STCL_POST: 01348 case ARM::STCL_OPTION: 01349 case ARM::t2LDC_OFFSET: 01350 case ARM::t2LDC_PRE: 01351 case ARM::t2LDC_POST: 01352 case ARM::t2LDC_OPTION: 01353 case ARM::t2LDCL_OFFSET: 01354 case ARM::t2LDCL_PRE: 01355 case ARM::t2LDCL_POST: 01356 case ARM::t2LDCL_OPTION: 01357 case ARM::t2STC_OFFSET: 01358 case ARM::t2STC_PRE: 01359 case ARM::t2STC_POST: 01360 case ARM::t2STC_OPTION: 01361 case ARM::t2STCL_OFFSET: 01362 case ARM::t2STCL_PRE: 01363 case ARM::t2STCL_POST: 01364 case ARM::t2STCL_OPTION: 01365 if (coproc == 0xA || coproc == 0xB) 01366 return MCDisassembler::Fail; 01367 break; 01368 default: 01369 break; 01370 } 01371 01372 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 01373 .getFeatureBits(); 01374 if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) 01375 return MCDisassembler::Fail; 01376 01377 Inst.addOperand(MCOperand::CreateImm(coproc)); 01378 Inst.addOperand(MCOperand::CreateImm(CRd)); 01379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01380 return MCDisassembler::Fail; 01381 01382 switch (Inst.getOpcode()) { 01383 case ARM::t2LDC2_OFFSET: 01384 case ARM::t2LDC2L_OFFSET: 01385 case ARM::t2LDC2_PRE: 01386 case ARM::t2LDC2L_PRE: 01387 case ARM::t2STC2_OFFSET: 01388 case ARM::t2STC2L_OFFSET: 01389 case ARM::t2STC2_PRE: 01390 case ARM::t2STC2L_PRE: 01391 case ARM::LDC2_OFFSET: 01392 case ARM::LDC2L_OFFSET: 01393 case ARM::LDC2_PRE: 01394 case ARM::LDC2L_PRE: 01395 case ARM::STC2_OFFSET: 01396 case ARM::STC2L_OFFSET: 01397 case ARM::STC2_PRE: 01398 case ARM::STC2L_PRE: 01399 case ARM::t2LDC_OFFSET: 01400 case ARM::t2LDCL_OFFSET: 01401 case ARM::t2LDC_PRE: 01402 case ARM::t2LDCL_PRE: 01403 case ARM::t2STC_OFFSET: 01404 case ARM::t2STCL_OFFSET: 01405 case ARM::t2STC_PRE: 01406 case ARM::t2STCL_PRE: 01407 case ARM::LDC_OFFSET: 01408 case ARM::LDCL_OFFSET: 01409 case ARM::LDC_PRE: 01410 case ARM::LDCL_PRE: 01411 case ARM::STC_OFFSET: 01412 case ARM::STCL_OFFSET: 01413 case ARM::STC_PRE: 01414 case ARM::STCL_PRE: 01415 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 01416 Inst.addOperand(MCOperand::CreateImm(imm)); 01417 break; 01418 case ARM::t2LDC2_POST: 01419 case ARM::t2LDC2L_POST: 01420 case ARM::t2STC2_POST: 01421 case ARM::t2STC2L_POST: 01422 case ARM::LDC2_POST: 01423 case ARM::LDC2L_POST: 01424 case ARM::STC2_POST: 01425 case ARM::STC2L_POST: 01426 case ARM::t2LDC_POST: 01427 case ARM::t2LDCL_POST: 01428 case ARM::t2STC_POST: 01429 case ARM::t2STCL_POST: 01430 case ARM::LDC_POST: 01431 case ARM::LDCL_POST: 01432 case ARM::STC_POST: 01433 case ARM::STCL_POST: 01434 imm |= U << 8; 01435 // fall through. 01436 default: 01437 // The 'option' variant doesn't encode 'U' in the immediate since 01438 // the immediate is unsigned [0,255]. 01439 Inst.addOperand(MCOperand::CreateImm(imm)); 01440 break; 01441 } 01442 01443 switch (Inst.getOpcode()) { 01444 case ARM::LDC_OFFSET: 01445 case ARM::LDC_PRE: 01446 case ARM::LDC_POST: 01447 case ARM::LDC_OPTION: 01448 case ARM::LDCL_OFFSET: 01449 case ARM::LDCL_PRE: 01450 case ARM::LDCL_POST: 01451 case ARM::LDCL_OPTION: 01452 case ARM::STC_OFFSET: 01453 case ARM::STC_PRE: 01454 case ARM::STC_POST: 01455 case ARM::STC_OPTION: 01456 case ARM::STCL_OFFSET: 01457 case ARM::STCL_PRE: 01458 case ARM::STCL_POST: 01459 case ARM::STCL_OPTION: 01460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01461 return MCDisassembler::Fail; 01462 break; 01463 default: 01464 break; 01465 } 01466 01467 return S; 01468 } 01469 01470 static DecodeStatus 01471 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 01472 uint64_t Address, const void *Decoder) { 01473 DecodeStatus S = MCDisassembler::Success; 01474 01475 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01476 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 01477 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 01478 unsigned imm = fieldFromInstruction(Insn, 0, 12); 01479 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01480 unsigned reg = fieldFromInstruction(Insn, 25, 1); 01481 unsigned P = fieldFromInstruction(Insn, 24, 1); 01482 unsigned W = fieldFromInstruction(Insn, 21, 1); 01483 01484 // On stores, the writeback operand precedes Rt. 01485 switch (Inst.getOpcode()) { 01486 case ARM::STR_POST_IMM: 01487 case ARM::STR_POST_REG: 01488 case ARM::STRB_POST_IMM: 01489 case ARM::STRB_POST_REG: 01490 case ARM::STRT_POST_REG: 01491 case ARM::STRT_POST_IMM: 01492 case ARM::STRBT_POST_REG: 01493 case ARM::STRBT_POST_IMM: 01494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01495 return MCDisassembler::Fail; 01496 break; 01497 default: 01498 break; 01499 } 01500 01501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 01502 return MCDisassembler::Fail; 01503 01504 // On loads, the writeback operand comes after Rt. 01505 switch (Inst.getOpcode()) { 01506 case ARM::LDR_POST_IMM: 01507 case ARM::LDR_POST_REG: 01508 case ARM::LDRB_POST_IMM: 01509 case ARM::LDRB_POST_REG: 01510 case ARM::LDRBT_POST_REG: 01511 case ARM::LDRBT_POST_IMM: 01512 case ARM::LDRT_POST_REG: 01513 case ARM::LDRT_POST_IMM: 01514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01515 return MCDisassembler::Fail; 01516 break; 01517 default: 01518 break; 01519 } 01520 01521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01522 return MCDisassembler::Fail; 01523 01524 ARM_AM::AddrOpc Op = ARM_AM::add; 01525 if (!fieldFromInstruction(Insn, 23, 1)) 01526 Op = ARM_AM::sub; 01527 01528 bool writeback = (P == 0) || (W == 1); 01529 unsigned idx_mode = 0; 01530 if (P && writeback) 01531 idx_mode = ARMII::IndexModePre; 01532 else if (!P && writeback) 01533 idx_mode = ARMII::IndexModePost; 01534 01535 if (writeback && (Rn == 15 || Rn == Rt)) 01536 S = MCDisassembler::SoftFail; // UNPREDICTABLE 01537 01538 if (reg) { 01539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 01540 return MCDisassembler::Fail; 01541 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 01542 switch( fieldFromInstruction(Insn, 5, 2)) { 01543 case 0: 01544 Opc = ARM_AM::lsl; 01545 break; 01546 case 1: 01547 Opc = ARM_AM::lsr; 01548 break; 01549 case 2: 01550 Opc = ARM_AM::asr; 01551 break; 01552 case 3: 01553 Opc = ARM_AM::ror; 01554 break; 01555 default: 01556 return MCDisassembler::Fail; 01557 } 01558 unsigned amt = fieldFromInstruction(Insn, 7, 5); 01559 if (Opc == ARM_AM::ror && amt == 0) 01560 Opc = ARM_AM::rrx; 01561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 01562 01563 Inst.addOperand(MCOperand::CreateImm(imm)); 01564 } else { 01565 Inst.addOperand(MCOperand::CreateReg(0)); 01566 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 01567 Inst.addOperand(MCOperand::CreateImm(tmp)); 01568 } 01569 01570 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01571 return MCDisassembler::Fail; 01572 01573 return S; 01574 } 01575 01576 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 01577 uint64_t Address, const void *Decoder) { 01578 DecodeStatus S = MCDisassembler::Success; 01579 01580 unsigned Rn = fieldFromInstruction(Val, 13, 4); 01581 unsigned Rm = fieldFromInstruction(Val, 0, 4); 01582 unsigned type = fieldFromInstruction(Val, 5, 2); 01583 unsigned imm = fieldFromInstruction(Val, 7, 5); 01584 unsigned U = fieldFromInstruction(Val, 12, 1); 01585 01586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 01587 switch (type) { 01588 case 0: 01589 ShOp = ARM_AM::lsl; 01590 break; 01591 case 1: 01592 ShOp = ARM_AM::lsr; 01593 break; 01594 case 2: 01595 ShOp = ARM_AM::asr; 01596 break; 01597 case 3: 01598 ShOp = ARM_AM::ror; 01599 break; 01600 } 01601 01602 if (ShOp == ARM_AM::ror && imm == 0) 01603 ShOp = ARM_AM::rrx; 01604 01605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01606 return MCDisassembler::Fail; 01607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 01608 return MCDisassembler::Fail; 01609 unsigned shift; 01610 if (U) 01611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 01612 else 01613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 01614 Inst.addOperand(MCOperand::CreateImm(shift)); 01615 01616 return S; 01617 } 01618 01619 static DecodeStatus 01620 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 01621 uint64_t Address, const void *Decoder) { 01622 DecodeStatus S = MCDisassembler::Success; 01623 01624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 01625 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01626 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 01627 unsigned type = fieldFromInstruction(Insn, 22, 1); 01628 unsigned imm = fieldFromInstruction(Insn, 8, 4); 01629 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 01630 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01631 unsigned W = fieldFromInstruction(Insn, 21, 1); 01632 unsigned P = fieldFromInstruction(Insn, 24, 1); 01633 unsigned Rt2 = Rt + 1; 01634 01635 bool writeback = (W == 1) | (P == 0); 01636 01637 // For {LD,ST}RD, Rt must be even, else undefined. 01638 switch (Inst.getOpcode()) { 01639 case ARM::STRD: 01640 case ARM::STRD_PRE: 01641 case ARM::STRD_POST: 01642 case ARM::LDRD: 01643 case ARM::LDRD_PRE: 01644 case ARM::LDRD_POST: 01645 if (Rt & 0x1) S = MCDisassembler::SoftFail; 01646 break; 01647 default: 01648 break; 01649 } 01650 switch (Inst.getOpcode()) { 01651 case ARM::STRD: 01652 case ARM::STRD_PRE: 01653 case ARM::STRD_POST: 01654 if (P == 0 && W == 1) 01655 S = MCDisassembler::SoftFail; 01656 01657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 01658 S = MCDisassembler::SoftFail; 01659 if (type && Rm == 15) 01660 S = MCDisassembler::SoftFail; 01661 if (Rt2 == 15) 01662 S = MCDisassembler::SoftFail; 01663 if (!type && fieldFromInstruction(Insn, 8, 4)) 01664 S = MCDisassembler::SoftFail; 01665 break; 01666 case ARM::STRH: 01667 case ARM::STRH_PRE: 01668 case ARM::STRH_POST: 01669 if (Rt == 15) 01670 S = MCDisassembler::SoftFail; 01671 if (writeback && (Rn == 15 || Rn == Rt)) 01672 S = MCDisassembler::SoftFail; 01673 if (!type && Rm == 15) 01674 S = MCDisassembler::SoftFail; 01675 break; 01676 case ARM::LDRD: 01677 case ARM::LDRD_PRE: 01678 case ARM::LDRD_POST: 01679 if (type && Rn == 15){ 01680 if (Rt2 == 15) 01681 S = MCDisassembler::SoftFail; 01682 break; 01683 } 01684 if (P == 0 && W == 1) 01685 S = MCDisassembler::SoftFail; 01686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 01687 S = MCDisassembler::SoftFail; 01688 if (!type && writeback && Rn == 15) 01689 S = MCDisassembler::SoftFail; 01690 if (writeback && (Rn == Rt || Rn == Rt2)) 01691 S = MCDisassembler::SoftFail; 01692 break; 01693 case ARM::LDRH: 01694 case ARM::LDRH_PRE: 01695 case ARM::LDRH_POST: 01696 if (type && Rn == 15){ 01697 if (Rt == 15) 01698 S = MCDisassembler::SoftFail; 01699 break; 01700 } 01701 if (Rt == 15) 01702 S = MCDisassembler::SoftFail; 01703 if (!type && Rm == 15) 01704 S = MCDisassembler::SoftFail; 01705 if (!type && writeback && (Rn == 15 || Rn == Rt)) 01706 S = MCDisassembler::SoftFail; 01707 break; 01708 case ARM::LDRSH: 01709 case ARM::LDRSH_PRE: 01710 case ARM::LDRSH_POST: 01711 case ARM::LDRSB: 01712 case ARM::LDRSB_PRE: 01713 case ARM::LDRSB_POST: 01714 if (type && Rn == 15){ 01715 if (Rt == 15) 01716 S = MCDisassembler::SoftFail; 01717 break; 01718 } 01719 if (type && (Rt == 15 || (writeback && Rn == Rt))) 01720 S = MCDisassembler::SoftFail; 01721 if (!type && (Rt == 15 || Rm == 15)) 01722 S = MCDisassembler::SoftFail; 01723 if (!type && writeback && (Rn == 15 || Rn == Rt)) 01724 S = MCDisassembler::SoftFail; 01725 break; 01726 default: 01727 break; 01728 } 01729 01730 if (writeback) { // Writeback 01731 if (P) 01732 U |= ARMII::IndexModePre << 9; 01733 else 01734 U |= ARMII::IndexModePost << 9; 01735 01736 // On stores, the writeback operand precedes Rt. 01737 switch (Inst.getOpcode()) { 01738 case ARM::STRD: 01739 case ARM::STRD_PRE: 01740 case ARM::STRD_POST: 01741 case ARM::STRH: 01742 case ARM::STRH_PRE: 01743 case ARM::STRH_POST: 01744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01745 return MCDisassembler::Fail; 01746 break; 01747 default: 01748 break; 01749 } 01750 } 01751 01752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 01753 return MCDisassembler::Fail; 01754 switch (Inst.getOpcode()) { 01755 case ARM::STRD: 01756 case ARM::STRD_PRE: 01757 case ARM::STRD_POST: 01758 case ARM::LDRD: 01759 case ARM::LDRD_PRE: 01760 case ARM::LDRD_POST: 01761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 01762 return MCDisassembler::Fail; 01763 break; 01764 default: 01765 break; 01766 } 01767 01768 if (writeback) { 01769 // On loads, the writeback operand comes after Rt. 01770 switch (Inst.getOpcode()) { 01771 case ARM::LDRD: 01772 case ARM::LDRD_PRE: 01773 case ARM::LDRD_POST: 01774 case ARM::LDRH: 01775 case ARM::LDRH_PRE: 01776 case ARM::LDRH_POST: 01777 case ARM::LDRSH: 01778 case ARM::LDRSH_PRE: 01779 case ARM::LDRSH_POST: 01780 case ARM::LDRSB: 01781 case ARM::LDRSB_PRE: 01782 case ARM::LDRSB_POST: 01783 case ARM::LDRHTr: 01784 case ARM::LDRSBTr: 01785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01786 return MCDisassembler::Fail; 01787 break; 01788 default: 01789 break; 01790 } 01791 } 01792 01793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01794 return MCDisassembler::Fail; 01795 01796 if (type) { 01797 Inst.addOperand(MCOperand::CreateReg(0)); 01798 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 01799 } else { 01800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 01801 return MCDisassembler::Fail; 01802 Inst.addOperand(MCOperand::CreateImm(U)); 01803 } 01804 01805 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01806 return MCDisassembler::Fail; 01807 01808 return S; 01809 } 01810 01811 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 01812 uint64_t Address, const void *Decoder) { 01813 DecodeStatus S = MCDisassembler::Success; 01814 01815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01816 unsigned mode = fieldFromInstruction(Insn, 23, 2); 01817 01818 switch (mode) { 01819 case 0: 01820 mode = ARM_AM::da; 01821 break; 01822 case 1: 01823 mode = ARM_AM::ia; 01824 break; 01825 case 2: 01826 mode = ARM_AM::db; 01827 break; 01828 case 3: 01829 mode = ARM_AM::ib; 01830 break; 01831 } 01832 01833 Inst.addOperand(MCOperand::CreateImm(mode)); 01834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01835 return MCDisassembler::Fail; 01836 01837 return S; 01838 } 01839 01840 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 01841 uint64_t Address, const void *Decoder) { 01842 DecodeStatus S = MCDisassembler::Success; 01843 01844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 01845 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 01846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01847 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01848 01849 if (pred == 0xF) 01850 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 01851 01852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 01853 return MCDisassembler::Fail; 01854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 01855 return MCDisassembler::Fail; 01856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 01857 return MCDisassembler::Fail; 01858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01859 return MCDisassembler::Fail; 01860 return S; 01861 } 01862 01863 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 01864 unsigned Insn, 01865 uint64_t Address, const void *Decoder) { 01866 DecodeStatus S = MCDisassembler::Success; 01867 01868 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 01869 unsigned pred = fieldFromInstruction(Insn, 28, 4); 01870 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 01871 01872 if (pred == 0xF) { 01873 // Ambiguous with RFE and SRS 01874 switch (Inst.getOpcode()) { 01875 case ARM::LDMDA: 01876 Inst.setOpcode(ARM::RFEDA); 01877 break; 01878 case ARM::LDMDA_UPD: 01879 Inst.setOpcode(ARM::RFEDA_UPD); 01880 break; 01881 case ARM::LDMDB: 01882 Inst.setOpcode(ARM::RFEDB); 01883 break; 01884 case ARM::LDMDB_UPD: 01885 Inst.setOpcode(ARM::RFEDB_UPD); 01886 break; 01887 case ARM::LDMIA: 01888 Inst.setOpcode(ARM::RFEIA); 01889 break; 01890 case ARM::LDMIA_UPD: 01891 Inst.setOpcode(ARM::RFEIA_UPD); 01892 break; 01893 case ARM::LDMIB: 01894 Inst.setOpcode(ARM::RFEIB); 01895 break; 01896 case ARM::LDMIB_UPD: 01897 Inst.setOpcode(ARM::RFEIB_UPD); 01898 break; 01899 case ARM::STMDA: 01900 Inst.setOpcode(ARM::SRSDA); 01901 break; 01902 case ARM::STMDA_UPD: 01903 Inst.setOpcode(ARM::SRSDA_UPD); 01904 break; 01905 case ARM::STMDB: 01906 Inst.setOpcode(ARM::SRSDB); 01907 break; 01908 case ARM::STMDB_UPD: 01909 Inst.setOpcode(ARM::SRSDB_UPD); 01910 break; 01911 case ARM::STMIA: 01912 Inst.setOpcode(ARM::SRSIA); 01913 break; 01914 case ARM::STMIA_UPD: 01915 Inst.setOpcode(ARM::SRSIA_UPD); 01916 break; 01917 case ARM::STMIB: 01918 Inst.setOpcode(ARM::SRSIB); 01919 break; 01920 case ARM::STMIB_UPD: 01921 Inst.setOpcode(ARM::SRSIB_UPD); 01922 break; 01923 default: 01924 return MCDisassembler::Fail; 01925 } 01926 01927 // For stores (which become SRS's, the only operand is the mode. 01928 if (fieldFromInstruction(Insn, 20, 1) == 0) { 01929 // Check SRS encoding constraints 01930 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 01931 fieldFromInstruction(Insn, 20, 1) == 0)) 01932 return MCDisassembler::Fail; 01933 01934 Inst.addOperand( 01935 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 01936 return S; 01937 } 01938 01939 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 01940 } 01941 01942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01943 return MCDisassembler::Fail; 01944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 01945 return MCDisassembler::Fail; // Tied 01946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 01947 return MCDisassembler::Fail; 01948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 01949 return MCDisassembler::Fail; 01950 01951 return S; 01952 } 01953 01954 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 01955 uint64_t Address, const void *Decoder) { 01956 unsigned imod = fieldFromInstruction(Insn, 18, 2); 01957 unsigned M = fieldFromInstruction(Insn, 17, 1); 01958 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 01959 unsigned mode = fieldFromInstruction(Insn, 0, 5); 01960 01961 DecodeStatus S = MCDisassembler::Success; 01962 01963 // This decoder is called from multiple location that do not check 01964 // the full encoding is valid before they do. 01965 if (fieldFromInstruction(Insn, 5, 1) != 0 || 01966 fieldFromInstruction(Insn, 16, 1) != 0 || 01967 fieldFromInstruction(Insn, 20, 8) != 0x10) 01968 return MCDisassembler::Fail; 01969 01970 // imod == '01' --> UNPREDICTABLE 01971 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 01972 // return failure here. The '01' imod value is unprintable, so there's 01973 // nothing useful we could do even if we returned UNPREDICTABLE. 01974 01975 if (imod == 1) return MCDisassembler::Fail; 01976 01977 if (imod && M) { 01978 Inst.setOpcode(ARM::CPS3p); 01979 Inst.addOperand(MCOperand::CreateImm(imod)); 01980 Inst.addOperand(MCOperand::CreateImm(iflags)); 01981 Inst.addOperand(MCOperand::CreateImm(mode)); 01982 } else if (imod && !M) { 01983 Inst.setOpcode(ARM::CPS2p); 01984 Inst.addOperand(MCOperand::CreateImm(imod)); 01985 Inst.addOperand(MCOperand::CreateImm(iflags)); 01986 if (mode) S = MCDisassembler::SoftFail; 01987 } else if (!imod && M) { 01988 Inst.setOpcode(ARM::CPS1p); 01989 Inst.addOperand(MCOperand::CreateImm(mode)); 01990 if (iflags) S = MCDisassembler::SoftFail; 01991 } else { 01992 // imod == '00' && M == '0' --> UNPREDICTABLE 01993 Inst.setOpcode(ARM::CPS1p); 01994 Inst.addOperand(MCOperand::CreateImm(mode)); 01995 S = MCDisassembler::SoftFail; 01996 } 01997 01998 return S; 01999 } 02000 02001 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 02002 uint64_t Address, const void *Decoder) { 02003 unsigned imod = fieldFromInstruction(Insn, 9, 2); 02004 unsigned M = fieldFromInstruction(Insn, 8, 1); 02005 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 02006 unsigned mode = fieldFromInstruction(Insn, 0, 5); 02007 02008 DecodeStatus S = MCDisassembler::Success; 02009 02010 // imod == '01' --> UNPREDICTABLE 02011 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 02012 // return failure here. The '01' imod value is unprintable, so there's 02013 // nothing useful we could do even if we returned UNPREDICTABLE. 02014 02015 if (imod == 1) return MCDisassembler::Fail; 02016 02017 if (imod && M) { 02018 Inst.setOpcode(ARM::t2CPS3p); 02019 Inst.addOperand(MCOperand::CreateImm(imod)); 02020 Inst.addOperand(MCOperand::CreateImm(iflags)); 02021 Inst.addOperand(MCOperand::CreateImm(mode)); 02022 } else if (imod && !M) { 02023 Inst.setOpcode(ARM::t2CPS2p); 02024 Inst.addOperand(MCOperand::CreateImm(imod)); 02025 Inst.addOperand(MCOperand::CreateImm(iflags)); 02026 if (mode) S = MCDisassembler::SoftFail; 02027 } else if (!imod && M) { 02028 Inst.setOpcode(ARM::t2CPS1p); 02029 Inst.addOperand(MCOperand::CreateImm(mode)); 02030 if (iflags) S = MCDisassembler::SoftFail; 02031 } else { 02032 // imod == '00' && M == '0' --> this is a HINT instruction 02033 int imm = fieldFromInstruction(Insn, 0, 8); 02034 // HINT are defined only for immediate in [0..4] 02035 if(imm > 4) return MCDisassembler::Fail; 02036 Inst.setOpcode(ARM::t2HINT); 02037 Inst.addOperand(MCOperand::CreateImm(imm)); 02038 } 02039 02040 return S; 02041 } 02042 02043 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 02044 uint64_t Address, const void *Decoder) { 02045 DecodeStatus S = MCDisassembler::Success; 02046 02047 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 02048 unsigned imm = 0; 02049 02050 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 02051 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 02052 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 02053 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 02054 02055 if (Inst.getOpcode() == ARM::t2MOVTi16) 02056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 02057 return MCDisassembler::Fail; 02058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 02059 return MCDisassembler::Fail; 02060 02061 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 02062 Inst.addOperand(MCOperand::CreateImm(imm)); 02063 02064 return S; 02065 } 02066 02067 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 02068 uint64_t Address, const void *Decoder) { 02069 DecodeStatus S = MCDisassembler::Success; 02070 02071 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02072 unsigned pred = fieldFromInstruction(Insn, 28, 4); 02073 unsigned imm = 0; 02074 02075 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 02076 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 02077 02078 if (Inst.getOpcode() == ARM::MOVTi16) 02079 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 02080 return MCDisassembler::Fail; 02081 02082 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 02083 return MCDisassembler::Fail; 02084 02085 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 02086 Inst.addOperand(MCOperand::CreateImm(imm)); 02087 02088 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 02089 return MCDisassembler::Fail; 02090 02091 return S; 02092 } 02093 02094 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 02095 uint64_t Address, const void *Decoder) { 02096 DecodeStatus S = MCDisassembler::Success; 02097 02098 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 02099 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 02100 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 02101 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 02102 unsigned pred = fieldFromInstruction(Insn, 28, 4); 02103 02104 if (pred == 0xF) 02105 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 02106 02107 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 02108 return MCDisassembler::Fail; 02109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 02110 return MCDisassembler::Fail; 02111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 02112 return MCDisassembler::Fail; 02113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 02114 return MCDisassembler::Fail; 02115 02116 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 02117 return MCDisassembler::Fail; 02118 02119 return S; 02120 } 02121 02122 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 02123 uint64_t Address, const void *Decoder) { 02124 DecodeStatus S = MCDisassembler::Success; 02125 02126 unsigned add = fieldFromInstruction(Val, 12, 1); 02127 unsigned imm = fieldFromInstruction(Val, 0, 12); 02128 unsigned Rn = fieldFromInstruction(Val, 13, 4); 02129 02130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02131 return MCDisassembler::Fail; 02132 02133 if (!add) imm *= -1; 02134 if (imm == 0 && !add) imm = INT32_MIN; 02135 Inst.addOperand(MCOperand::CreateImm(imm)); 02136 if (Rn == 15) 02137 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 02138 02139 return S; 02140 } 02141 02142 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 02143 uint64_t Address, const void *Decoder) { 02144 DecodeStatus S = MCDisassembler::Success; 02145 02146 unsigned Rn = fieldFromInstruction(Val, 9, 4); 02147 unsigned U = fieldFromInstruction(Val, 8, 1); 02148 unsigned imm = fieldFromInstruction(Val, 0, 8); 02149 02150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02151 return MCDisassembler::Fail; 02152 02153 if (U) 02154 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 02155 else 02156 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 02157 02158 return S; 02159 } 02160 02161 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 02162 uint64_t Address, const void *Decoder) { 02163 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 02164 } 02165 02166 static DecodeStatus 02167 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 02168 uint64_t Address, const void *Decoder) { 02169 DecodeStatus Status = MCDisassembler::Success; 02170 02171 // Note the J1 and J2 values are from the encoded instruction. So here 02172 // change them to I1 and I2 values via as documented: 02173 // I1 = NOT(J1 EOR S); 02174 // I2 = NOT(J2 EOR S); 02175 // and build the imm32 with one trailing zero as documented: 02176 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 02177 unsigned S = fieldFromInstruction(Insn, 26, 1); 02178 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 02179 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 02180 unsigned I1 = !(J1 ^ S); 02181 unsigned I2 = !(J2 ^ S); 02182 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 02183 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 02184 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 02185 int imm32 = SignExtend32<25>(tmp << 1); 02186 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 02187 true, 4, Inst, Decoder)) 02188 Inst.addOperand(MCOperand::CreateImm(imm32)); 02189 02190 return Status; 02191 } 02192 02193 static DecodeStatus 02194 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 02195 uint64_t Address, const void *Decoder) { 02196 DecodeStatus S = MCDisassembler::Success; 02197 02198 unsigned pred = fieldFromInstruction(Insn, 28, 4); 02199 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 02200 02201 if (pred == 0xF) { 02202 Inst.setOpcode(ARM::BLXi); 02203 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 02204 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 02205 true, 4, Inst, Decoder)) 02206 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 02207 return S; 02208 } 02209 02210 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 02211 true, 4, Inst, Decoder)) 02212 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 02213 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 02214 return MCDisassembler::Fail; 02215 02216 return S; 02217 } 02218 02219 02220 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 02221 uint64_t Address, const void *Decoder) { 02222 DecodeStatus S = MCDisassembler::Success; 02223 02224 unsigned Rm = fieldFromInstruction(Val, 0, 4); 02225 unsigned align = fieldFromInstruction(Val, 4, 2); 02226 02227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02228 return MCDisassembler::Fail; 02229 if (!align) 02230 Inst.addOperand(MCOperand::CreateImm(0)); 02231 else 02232 Inst.addOperand(MCOperand::CreateImm(4 << align)); 02233 02234 return S; 02235 } 02236 02237 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 02238 uint64_t Address, const void *Decoder) { 02239 DecodeStatus S = MCDisassembler::Success; 02240 02241 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02242 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02243 unsigned wb = fieldFromInstruction(Insn, 16, 4); 02244 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02245 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 02246 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02247 02248 // First output register 02249 switch (Inst.getOpcode()) { 02250 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 02251 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 02252 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 02253 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 02254 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 02255 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 02256 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 02257 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 02258 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 02259 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02260 return MCDisassembler::Fail; 02261 break; 02262 case ARM::VLD2b16: 02263 case ARM::VLD2b32: 02264 case ARM::VLD2b8: 02265 case ARM::VLD2b16wb_fixed: 02266 case ARM::VLD2b16wb_register: 02267 case ARM::VLD2b32wb_fixed: 02268 case ARM::VLD2b32wb_register: 02269 case ARM::VLD2b8wb_fixed: 02270 case ARM::VLD2b8wb_register: 02271 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 02272 return MCDisassembler::Fail; 02273 break; 02274 default: 02275 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02276 return MCDisassembler::Fail; 02277 } 02278 02279 // Second output register 02280 switch (Inst.getOpcode()) { 02281 case ARM::VLD3d8: 02282 case ARM::VLD3d16: 02283 case ARM::VLD3d32: 02284 case ARM::VLD3d8_UPD: 02285 case ARM::VLD3d16_UPD: 02286 case ARM::VLD3d32_UPD: 02287 case ARM::VLD4d8: 02288 case ARM::VLD4d16: 02289 case ARM::VLD4d32: 02290 case ARM::VLD4d8_UPD: 02291 case ARM::VLD4d16_UPD: 02292 case ARM::VLD4d32_UPD: 02293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 02294 return MCDisassembler::Fail; 02295 break; 02296 case ARM::VLD3q8: 02297 case ARM::VLD3q16: 02298 case ARM::VLD3q32: 02299 case ARM::VLD3q8_UPD: 02300 case ARM::VLD3q16_UPD: 02301 case ARM::VLD3q32_UPD: 02302 case ARM::VLD4q8: 02303 case ARM::VLD4q16: 02304 case ARM::VLD4q32: 02305 case ARM::VLD4q8_UPD: 02306 case ARM::VLD4q16_UPD: 02307 case ARM::VLD4q32_UPD: 02308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02309 return MCDisassembler::Fail; 02310 default: 02311 break; 02312 } 02313 02314 // Third output register 02315 switch(Inst.getOpcode()) { 02316 case ARM::VLD3d8: 02317 case ARM::VLD3d16: 02318 case ARM::VLD3d32: 02319 case ARM::VLD3d8_UPD: 02320 case ARM::VLD3d16_UPD: 02321 case ARM::VLD3d32_UPD: 02322 case ARM::VLD4d8: 02323 case ARM::VLD4d16: 02324 case ARM::VLD4d32: 02325 case ARM::VLD4d8_UPD: 02326 case ARM::VLD4d16_UPD: 02327 case ARM::VLD4d32_UPD: 02328 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02329 return MCDisassembler::Fail; 02330 break; 02331 case ARM::VLD3q8: 02332 case ARM::VLD3q16: 02333 case ARM::VLD3q32: 02334 case ARM::VLD3q8_UPD: 02335 case ARM::VLD3q16_UPD: 02336 case ARM::VLD3q32_UPD: 02337 case ARM::VLD4q8: 02338 case ARM::VLD4q16: 02339 case ARM::VLD4q32: 02340 case ARM::VLD4q8_UPD: 02341 case ARM::VLD4q16_UPD: 02342 case ARM::VLD4q32_UPD: 02343 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 02344 return MCDisassembler::Fail; 02345 break; 02346 default: 02347 break; 02348 } 02349 02350 // Fourth output register 02351 switch (Inst.getOpcode()) { 02352 case ARM::VLD4d8: 02353 case ARM::VLD4d16: 02354 case ARM::VLD4d32: 02355 case ARM::VLD4d8_UPD: 02356 case ARM::VLD4d16_UPD: 02357 case ARM::VLD4d32_UPD: 02358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 02359 return MCDisassembler::Fail; 02360 break; 02361 case ARM::VLD4q8: 02362 case ARM::VLD4q16: 02363 case ARM::VLD4q32: 02364 case ARM::VLD4q8_UPD: 02365 case ARM::VLD4q16_UPD: 02366 case ARM::VLD4q32_UPD: 02367 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 02368 return MCDisassembler::Fail; 02369 break; 02370 default: 02371 break; 02372 } 02373 02374 // Writeback operand 02375 switch (Inst.getOpcode()) { 02376 case ARM::VLD1d8wb_fixed: 02377 case ARM::VLD1d16wb_fixed: 02378 case ARM::VLD1d32wb_fixed: 02379 case ARM::VLD1d64wb_fixed: 02380 case ARM::VLD1d8wb_register: 02381 case ARM::VLD1d16wb_register: 02382 case ARM::VLD1d32wb_register: 02383 case ARM::VLD1d64wb_register: 02384 case ARM::VLD1q8wb_fixed: 02385 case ARM::VLD1q16wb_fixed: 02386 case ARM::VLD1q32wb_fixed: 02387 case ARM::VLD1q64wb_fixed: 02388 case ARM::VLD1q8wb_register: 02389 case ARM::VLD1q16wb_register: 02390 case ARM::VLD1q32wb_register: 02391 case ARM::VLD1q64wb_register: 02392 case ARM::VLD1d8Twb_fixed: 02393 case ARM::VLD1d8Twb_register: 02394 case ARM::VLD1d16Twb_fixed: 02395 case ARM::VLD1d16Twb_register: 02396 case ARM::VLD1d32Twb_fixed: 02397 case ARM::VLD1d32Twb_register: 02398 case ARM::VLD1d64Twb_fixed: 02399 case ARM::VLD1d64Twb_register: 02400 case ARM::VLD1d8Qwb_fixed: 02401 case ARM::VLD1d8Qwb_register: 02402 case ARM::VLD1d16Qwb_fixed: 02403 case ARM::VLD1d16Qwb_register: 02404 case ARM::VLD1d32Qwb_fixed: 02405 case ARM::VLD1d32Qwb_register: 02406 case ARM::VLD1d64Qwb_fixed: 02407 case ARM::VLD1d64Qwb_register: 02408 case ARM::VLD2d8wb_fixed: 02409 case ARM::VLD2d16wb_fixed: 02410 case ARM::VLD2d32wb_fixed: 02411 case ARM::VLD2q8wb_fixed: 02412 case ARM::VLD2q16wb_fixed: 02413 case ARM::VLD2q32wb_fixed: 02414 case ARM::VLD2d8wb_register: 02415 case ARM::VLD2d16wb_register: 02416 case ARM::VLD2d32wb_register: 02417 case ARM::VLD2q8wb_register: 02418 case ARM::VLD2q16wb_register: 02419 case ARM::VLD2q32wb_register: 02420 case ARM::VLD2b8wb_fixed: 02421 case ARM::VLD2b16wb_fixed: 02422 case ARM::VLD2b32wb_fixed: 02423 case ARM::VLD2b8wb_register: 02424 case ARM::VLD2b16wb_register: 02425 case ARM::VLD2b32wb_register: 02426 Inst.addOperand(MCOperand::CreateImm(0)); 02427 break; 02428 case ARM::VLD3d8_UPD: 02429 case ARM::VLD3d16_UPD: 02430 case ARM::VLD3d32_UPD: 02431 case ARM::VLD3q8_UPD: 02432 case ARM::VLD3q16_UPD: 02433 case ARM::VLD3q32_UPD: 02434 case ARM::VLD4d8_UPD: 02435 case ARM::VLD4d16_UPD: 02436 case ARM::VLD4d32_UPD: 02437 case ARM::VLD4q8_UPD: 02438 case ARM::VLD4q16_UPD: 02439 case ARM::VLD4q32_UPD: 02440 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 02441 return MCDisassembler::Fail; 02442 break; 02443 default: 02444 break; 02445 } 02446 02447 // AddrMode6 Base (register+alignment) 02448 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 02449 return MCDisassembler::Fail; 02450 02451 // AddrMode6 Offset (register) 02452 switch (Inst.getOpcode()) { 02453 default: 02454 // The below have been updated to have explicit am6offset split 02455 // between fixed and register offset. For those instructions not 02456 // yet updated, we need to add an additional reg0 operand for the 02457 // fixed variant. 02458 // 02459 // The fixed offset encodes as Rm == 0xd, so we check for that. 02460 if (Rm == 0xd) { 02461 Inst.addOperand(MCOperand::CreateReg(0)); 02462 break; 02463 } 02464 // Fall through to handle the register offset variant. 02465 case ARM::VLD1d8wb_fixed: 02466 case ARM::VLD1d16wb_fixed: 02467 case ARM::VLD1d32wb_fixed: 02468 case ARM::VLD1d64wb_fixed: 02469 case ARM::VLD1d8Twb_fixed: 02470 case ARM::VLD1d16Twb_fixed: 02471 case ARM::VLD1d32Twb_fixed: 02472 case ARM::VLD1d64Twb_fixed: 02473 case ARM::VLD1d8Qwb_fixed: 02474 case ARM::VLD1d16Qwb_fixed: 02475 case ARM::VLD1d32Qwb_fixed: 02476 case ARM::VLD1d64Qwb_fixed: 02477 case ARM::VLD1d8wb_register: 02478 case ARM::VLD1d16wb_register: 02479 case ARM::VLD1d32wb_register: 02480 case ARM::VLD1d64wb_register: 02481 case ARM::VLD1q8wb_fixed: 02482 case ARM::VLD1q16wb_fixed: 02483 case ARM::VLD1q32wb_fixed: 02484 case ARM::VLD1q64wb_fixed: 02485 case ARM::VLD1q8wb_register: 02486 case ARM::VLD1q16wb_register: 02487 case ARM::VLD1q32wb_register: 02488 case ARM::VLD1q64wb_register: 02489 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 02490 // variant encodes Rm == 0xf. Anything else is a register offset post- 02491 // increment and we need to add the register operand to the instruction. 02492 if (Rm != 0xD && Rm != 0xF && 02493 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02494 return MCDisassembler::Fail; 02495 break; 02496 case ARM::VLD2d8wb_fixed: 02497 case ARM::VLD2d16wb_fixed: 02498 case ARM::VLD2d32wb_fixed: 02499 case ARM::VLD2b8wb_fixed: 02500 case ARM::VLD2b16wb_fixed: 02501 case ARM::VLD2b32wb_fixed: 02502 case ARM::VLD2q8wb_fixed: 02503 case ARM::VLD2q16wb_fixed: 02504 case ARM::VLD2q32wb_fixed: 02505 break; 02506 } 02507 02508 return S; 02509 } 02510 02511 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 02512 uint64_t Address, const void *Decoder) { 02513 unsigned type = fieldFromInstruction(Insn, 8, 4); 02514 unsigned align = fieldFromInstruction(Insn, 4, 2); 02515 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 02516 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 02517 if (type == 10 && align == 3) return MCDisassembler::Fail; 02518 02519 unsigned load = fieldFromInstruction(Insn, 21, 1); 02520 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 02521 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 02522 } 02523 02524 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 02525 uint64_t Address, const void *Decoder) { 02526 unsigned size = fieldFromInstruction(Insn, 6, 2); 02527 if (size == 3) return MCDisassembler::Fail; 02528 02529 unsigned type = fieldFromInstruction(Insn, 8, 4); 02530 unsigned align = fieldFromInstruction(Insn, 4, 2); 02531 if (type == 8 && align == 3) return MCDisassembler::Fail; 02532 if (type == 9 && align == 3) return MCDisassembler::Fail; 02533 02534 unsigned load = fieldFromInstruction(Insn, 21, 1); 02535 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 02536 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 02537 } 02538 02539 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 02540 uint64_t Address, const void *Decoder) { 02541 unsigned size = fieldFromInstruction(Insn, 6, 2); 02542 if (size == 3) return MCDisassembler::Fail; 02543 02544 unsigned align = fieldFromInstruction(Insn, 4, 2); 02545 if (align & 2) return MCDisassembler::Fail; 02546 02547 unsigned load = fieldFromInstruction(Insn, 21, 1); 02548 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 02549 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 02550 } 02551 02552 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 02553 uint64_t Address, const void *Decoder) { 02554 unsigned size = fieldFromInstruction(Insn, 6, 2); 02555 if (size == 3) return MCDisassembler::Fail; 02556 02557 unsigned load = fieldFromInstruction(Insn, 21, 1); 02558 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 02559 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 02560 } 02561 02562 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 02563 uint64_t Address, const void *Decoder) { 02564 DecodeStatus S = MCDisassembler::Success; 02565 02566 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02567 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02568 unsigned wb = fieldFromInstruction(Insn, 16, 4); 02569 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02570 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 02571 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02572 02573 // Writeback Operand 02574 switch (Inst.getOpcode()) { 02575 case ARM::VST1d8wb_fixed: 02576 case ARM::VST1d16wb_fixed: 02577 case ARM::VST1d32wb_fixed: 02578 case ARM::VST1d64wb_fixed: 02579 case ARM::VST1d8wb_register: 02580 case ARM::VST1d16wb_register: 02581 case ARM::VST1d32wb_register: 02582 case ARM::VST1d64wb_register: 02583 case ARM::VST1q8wb_fixed: 02584 case ARM::VST1q16wb_fixed: 02585 case ARM::VST1q32wb_fixed: 02586 case ARM::VST1q64wb_fixed: 02587 case ARM::VST1q8wb_register: 02588 case ARM::VST1q16wb_register: 02589 case ARM::VST1q32wb_register: 02590 case ARM::VST1q64wb_register: 02591 case ARM::VST1d8Twb_fixed: 02592 case ARM::VST1d16Twb_fixed: 02593 case ARM::VST1d32Twb_fixed: 02594 case ARM::VST1d64Twb_fixed: 02595 case ARM::VST1d8Twb_register: 02596 case ARM::VST1d16Twb_register: 02597 case ARM::VST1d32Twb_register: 02598 case ARM::VST1d64Twb_register: 02599 case ARM::VST1d8Qwb_fixed: 02600 case ARM::VST1d16Qwb_fixed: 02601 case ARM::VST1d32Qwb_fixed: 02602 case ARM::VST1d64Qwb_fixed: 02603 case ARM::VST1d8Qwb_register: 02604 case ARM::VST1d16Qwb_register: 02605 case ARM::VST1d32Qwb_register: 02606 case ARM::VST1d64Qwb_register: 02607 case ARM::VST2d8wb_fixed: 02608 case ARM::VST2d16wb_fixed: 02609 case ARM::VST2d32wb_fixed: 02610 case ARM::VST2d8wb_register: 02611 case ARM::VST2d16wb_register: 02612 case ARM::VST2d32wb_register: 02613 case ARM::VST2q8wb_fixed: 02614 case ARM::VST2q16wb_fixed: 02615 case ARM::VST2q32wb_fixed: 02616 case ARM::VST2q8wb_register: 02617 case ARM::VST2q16wb_register: 02618 case ARM::VST2q32wb_register: 02619 case ARM::VST2b8wb_fixed: 02620 case ARM::VST2b16wb_fixed: 02621 case ARM::VST2b32wb_fixed: 02622 case ARM::VST2b8wb_register: 02623 case ARM::VST2b16wb_register: 02624 case ARM::VST2b32wb_register: 02625 if (Rm == 0xF) 02626 return MCDisassembler::Fail; 02627 Inst.addOperand(MCOperand::CreateImm(0)); 02628 break; 02629 case ARM::VST3d8_UPD: 02630 case ARM::VST3d16_UPD: 02631 case ARM::VST3d32_UPD: 02632 case ARM::VST3q8_UPD: 02633 case ARM::VST3q16_UPD: 02634 case ARM::VST3q32_UPD: 02635 case ARM::VST4d8_UPD: 02636 case ARM::VST4d16_UPD: 02637 case ARM::VST4d32_UPD: 02638 case ARM::VST4q8_UPD: 02639 case ARM::VST4q16_UPD: 02640 case ARM::VST4q32_UPD: 02641 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 02642 return MCDisassembler::Fail; 02643 break; 02644 default: 02645 break; 02646 } 02647 02648 // AddrMode6 Base (register+alignment) 02649 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 02650 return MCDisassembler::Fail; 02651 02652 // AddrMode6 Offset (register) 02653 switch (Inst.getOpcode()) { 02654 default: 02655 if (Rm == 0xD) 02656 Inst.addOperand(MCOperand::CreateReg(0)); 02657 else if (Rm != 0xF) { 02658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02659 return MCDisassembler::Fail; 02660 } 02661 break; 02662 case ARM::VST1d8wb_fixed: 02663 case ARM::VST1d16wb_fixed: 02664 case ARM::VST1d32wb_fixed: 02665 case ARM::VST1d64wb_fixed: 02666 case ARM::VST1q8wb_fixed: 02667 case ARM::VST1q16wb_fixed: 02668 case ARM::VST1q32wb_fixed: 02669 case ARM::VST1q64wb_fixed: 02670 case ARM::VST1d8Twb_fixed: 02671 case ARM::VST1d16Twb_fixed: 02672 case ARM::VST1d32Twb_fixed: 02673 case ARM::VST1d64Twb_fixed: 02674 case ARM::VST1d8Qwb_fixed: 02675 case ARM::VST1d16Qwb_fixed: 02676 case ARM::VST1d32Qwb_fixed: 02677 case ARM::VST1d64Qwb_fixed: 02678 case ARM::VST2d8wb_fixed: 02679 case ARM::VST2d16wb_fixed: 02680 case ARM::VST2d32wb_fixed: 02681 case ARM::VST2q8wb_fixed: 02682 case ARM::VST2q16wb_fixed: 02683 case ARM::VST2q32wb_fixed: 02684 case ARM::VST2b8wb_fixed: 02685 case ARM::VST2b16wb_fixed: 02686 case ARM::VST2b32wb_fixed: 02687 break; 02688 } 02689 02690 02691 // First input register 02692 switch (Inst.getOpcode()) { 02693 case ARM::VST1q16: 02694 case ARM::VST1q32: 02695 case ARM::VST1q64: 02696 case ARM::VST1q8: 02697 case ARM::VST1q16wb_fixed: 02698 case ARM::VST1q16wb_register: 02699 case ARM::VST1q32wb_fixed: 02700 case ARM::VST1q32wb_register: 02701 case ARM::VST1q64wb_fixed: 02702 case ARM::VST1q64wb_register: 02703 case ARM::VST1q8wb_fixed: 02704 case ARM::VST1q8wb_register: 02705 case ARM::VST2d16: 02706 case ARM::VST2d32: 02707 case ARM::VST2d8: 02708 case ARM::VST2d16wb_fixed: 02709 case ARM::VST2d16wb_register: 02710 case ARM::VST2d32wb_fixed: 02711 case ARM::VST2d32wb_register: 02712 case ARM::VST2d8wb_fixed: 02713 case ARM::VST2d8wb_register: 02714 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02715 return MCDisassembler::Fail; 02716 break; 02717 case ARM::VST2b16: 02718 case ARM::VST2b32: 02719 case ARM::VST2b8: 02720 case ARM::VST2b16wb_fixed: 02721 case ARM::VST2b16wb_register: 02722 case ARM::VST2b32wb_fixed: 02723 case ARM::VST2b32wb_register: 02724 case ARM::VST2b8wb_fixed: 02725 case ARM::VST2b8wb_register: 02726 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 02727 return MCDisassembler::Fail; 02728 break; 02729 default: 02730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02731 return MCDisassembler::Fail; 02732 } 02733 02734 // Second input register 02735 switch (Inst.getOpcode()) { 02736 case ARM::VST3d8: 02737 case ARM::VST3d16: 02738 case ARM::VST3d32: 02739 case ARM::VST3d8_UPD: 02740 case ARM::VST3d16_UPD: 02741 case ARM::VST3d32_UPD: 02742 case ARM::VST4d8: 02743 case ARM::VST4d16: 02744 case ARM::VST4d32: 02745 case ARM::VST4d8_UPD: 02746 case ARM::VST4d16_UPD: 02747 case ARM::VST4d32_UPD: 02748 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 02749 return MCDisassembler::Fail; 02750 break; 02751 case ARM::VST3q8: 02752 case ARM::VST3q16: 02753 case ARM::VST3q32: 02754 case ARM::VST3q8_UPD: 02755 case ARM::VST3q16_UPD: 02756 case ARM::VST3q32_UPD: 02757 case ARM::VST4q8: 02758 case ARM::VST4q16: 02759 case ARM::VST4q32: 02760 case ARM::VST4q8_UPD: 02761 case ARM::VST4q16_UPD: 02762 case ARM::VST4q32_UPD: 02763 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02764 return MCDisassembler::Fail; 02765 break; 02766 default: 02767 break; 02768 } 02769 02770 // Third input register 02771 switch (Inst.getOpcode()) { 02772 case ARM::VST3d8: 02773 case ARM::VST3d16: 02774 case ARM::VST3d32: 02775 case ARM::VST3d8_UPD: 02776 case ARM::VST3d16_UPD: 02777 case ARM::VST3d32_UPD: 02778 case ARM::VST4d8: 02779 case ARM::VST4d16: 02780 case ARM::VST4d32: 02781 case ARM::VST4d8_UPD: 02782 case ARM::VST4d16_UPD: 02783 case ARM::VST4d32_UPD: 02784 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 02785 return MCDisassembler::Fail; 02786 break; 02787 case ARM::VST3q8: 02788 case ARM::VST3q16: 02789 case ARM::VST3q32: 02790 case ARM::VST3q8_UPD: 02791 case ARM::VST3q16_UPD: 02792 case ARM::VST3q32_UPD: 02793 case ARM::VST4q8: 02794 case ARM::VST4q16: 02795 case ARM::VST4q32: 02796 case ARM::VST4q8_UPD: 02797 case ARM::VST4q16_UPD: 02798 case ARM::VST4q32_UPD: 02799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 02800 return MCDisassembler::Fail; 02801 break; 02802 default: 02803 break; 02804 } 02805 02806 // Fourth input register 02807 switch (Inst.getOpcode()) { 02808 case ARM::VST4d8: 02809 case ARM::VST4d16: 02810 case ARM::VST4d32: 02811 case ARM::VST4d8_UPD: 02812 case ARM::VST4d16_UPD: 02813 case ARM::VST4d32_UPD: 02814 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 02815 return MCDisassembler::Fail; 02816 break; 02817 case ARM::VST4q8: 02818 case ARM::VST4q16: 02819 case ARM::VST4q32: 02820 case ARM::VST4q8_UPD: 02821 case ARM::VST4q16_UPD: 02822 case ARM::VST4q32_UPD: 02823 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 02824 return MCDisassembler::Fail; 02825 break; 02826 default: 02827 break; 02828 } 02829 02830 return S; 02831 } 02832 02833 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 02834 uint64_t Address, const void *Decoder) { 02835 DecodeStatus S = MCDisassembler::Success; 02836 02837 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02838 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02840 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02841 unsigned align = fieldFromInstruction(Insn, 4, 1); 02842 unsigned size = fieldFromInstruction(Insn, 6, 2); 02843 02844 if (size == 0 && align == 1) 02845 return MCDisassembler::Fail; 02846 align *= (1 << size); 02847 02848 switch (Inst.getOpcode()) { 02849 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 02850 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 02851 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 02852 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 02853 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02854 return MCDisassembler::Fail; 02855 break; 02856 default: 02857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02858 return MCDisassembler::Fail; 02859 break; 02860 } 02861 if (Rm != 0xF) { 02862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02863 return MCDisassembler::Fail; 02864 } 02865 02866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02867 return MCDisassembler::Fail; 02868 Inst.addOperand(MCOperand::CreateImm(align)); 02869 02870 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 02871 // variant encodes Rm == 0xf. Anything else is a register offset post- 02872 // increment and we need to add the register operand to the instruction. 02873 if (Rm != 0xD && Rm != 0xF && 02874 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02875 return MCDisassembler::Fail; 02876 02877 return S; 02878 } 02879 02880 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 02881 uint64_t Address, const void *Decoder) { 02882 DecodeStatus S = MCDisassembler::Success; 02883 02884 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02886 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02887 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02888 unsigned align = fieldFromInstruction(Insn, 4, 1); 02889 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 02890 align *= 2*size; 02891 02892 switch (Inst.getOpcode()) { 02893 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 02894 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 02895 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 02896 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 02897 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 02898 return MCDisassembler::Fail; 02899 break; 02900 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 02901 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 02902 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 02903 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 02904 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 02905 return MCDisassembler::Fail; 02906 break; 02907 default: 02908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02909 return MCDisassembler::Fail; 02910 break; 02911 } 02912 02913 if (Rm != 0xF) 02914 Inst.addOperand(MCOperand::CreateImm(0)); 02915 02916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02917 return MCDisassembler::Fail; 02918 Inst.addOperand(MCOperand::CreateImm(align)); 02919 02920 if (Rm != 0xD && Rm != 0xF) { 02921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02922 return MCDisassembler::Fail; 02923 } 02924 02925 return S; 02926 } 02927 02928 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 02929 uint64_t Address, const void *Decoder) { 02930 DecodeStatus S = MCDisassembler::Success; 02931 02932 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02933 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02935 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02936 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 02937 02938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02939 return MCDisassembler::Fail; 02940 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 02941 return MCDisassembler::Fail; 02942 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 02943 return MCDisassembler::Fail; 02944 if (Rm != 0xF) { 02945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02946 return MCDisassembler::Fail; 02947 } 02948 02949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 02950 return MCDisassembler::Fail; 02951 Inst.addOperand(MCOperand::CreateImm(0)); 02952 02953 if (Rm == 0xD) 02954 Inst.addOperand(MCOperand::CreateReg(0)); 02955 else if (Rm != 0xF) { 02956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 02957 return MCDisassembler::Fail; 02958 } 02959 02960 return S; 02961 } 02962 02963 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 02964 uint64_t Address, const void *Decoder) { 02965 DecodeStatus S = MCDisassembler::Success; 02966 02967 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 02968 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 02969 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 02970 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 02971 unsigned size = fieldFromInstruction(Insn, 6, 2); 02972 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 02973 unsigned align = fieldFromInstruction(Insn, 4, 1); 02974 02975 if (size == 0x3) { 02976 if (align == 0) 02977 return MCDisassembler::Fail; 02978 size = 4; 02979 align = 16; 02980 } else { 02981 if (size == 2) { 02982 size = 1 << size; 02983 align *= 8; 02984 } else { 02985 size = 1 << size; 02986 align *= 4*size; 02987 } 02988 } 02989 02990 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 02991 return MCDisassembler::Fail; 02992 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 02993 return MCDisassembler::Fail; 02994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 02995 return MCDisassembler::Fail; 02996 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 02997 return MCDisassembler::Fail; 02998 if (Rm != 0xF) { 02999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03000 return MCDisassembler::Fail; 03001 } 03002 03003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03004 return MCDisassembler::Fail; 03005 Inst.addOperand(MCOperand::CreateImm(align)); 03006 03007 if (Rm == 0xD) 03008 Inst.addOperand(MCOperand::CreateReg(0)); 03009 else if (Rm != 0xF) { 03010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03011 return MCDisassembler::Fail; 03012 } 03013 03014 return S; 03015 } 03016 03017 static DecodeStatus 03018 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 03019 uint64_t Address, const void *Decoder) { 03020 DecodeStatus S = MCDisassembler::Success; 03021 03022 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03023 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03024 unsigned imm = fieldFromInstruction(Insn, 0, 4); 03025 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 03026 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 03027 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 03028 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 03029 unsigned Q = fieldFromInstruction(Insn, 6, 1); 03030 03031 if (Q) { 03032 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 03033 return MCDisassembler::Fail; 03034 } else { 03035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03036 return MCDisassembler::Fail; 03037 } 03038 03039 Inst.addOperand(MCOperand::CreateImm(imm)); 03040 03041 switch (Inst.getOpcode()) { 03042 case ARM::VORRiv4i16: 03043 case ARM::VORRiv2i32: 03044 case ARM::VBICiv4i16: 03045 case ARM::VBICiv2i32: 03046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03047 return MCDisassembler::Fail; 03048 break; 03049 case ARM::VORRiv8i16: 03050 case ARM::VORRiv4i32: 03051 case ARM::VBICiv8i16: 03052 case ARM::VBICiv4i32: 03053 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 03054 return MCDisassembler::Fail; 03055 break; 03056 default: 03057 break; 03058 } 03059 03060 return S; 03061 } 03062 03063 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 03064 uint64_t Address, const void *Decoder) { 03065 DecodeStatus S = MCDisassembler::Success; 03066 03067 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03068 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03069 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03070 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 03071 unsigned size = fieldFromInstruction(Insn, 18, 2); 03072 03073 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 03074 return MCDisassembler::Fail; 03075 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 03076 return MCDisassembler::Fail; 03077 Inst.addOperand(MCOperand::CreateImm(8 << size)); 03078 03079 return S; 03080 } 03081 03082 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 03083 uint64_t Address, const void *Decoder) { 03084 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 03085 return MCDisassembler::Success; 03086 } 03087 03088 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 03089 uint64_t Address, const void *Decoder) { 03090 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 03091 return MCDisassembler::Success; 03092 } 03093 03094 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 03095 uint64_t Address, const void *Decoder) { 03096 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 03097 return MCDisassembler::Success; 03098 } 03099 03100 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 03101 uint64_t Address, const void *Decoder) { 03102 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 03103 return MCDisassembler::Success; 03104 } 03105 03106 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 03107 uint64_t Address, const void *Decoder) { 03108 DecodeStatus S = MCDisassembler::Success; 03109 03110 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 03111 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 03112 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03113 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 03114 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03115 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 03116 unsigned op = fieldFromInstruction(Insn, 6, 1); 03117 03118 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03119 return MCDisassembler::Fail; 03120 if (op) { 03121 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 03122 return MCDisassembler::Fail; // Writeback 03123 } 03124 03125 switch (Inst.getOpcode()) { 03126 case ARM::VTBL2: 03127 case ARM::VTBX2: 03128 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 03129 return MCDisassembler::Fail; 03130 break; 03131 default: 03132 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 03133 return MCDisassembler::Fail; 03134 } 03135 03136 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 03137 return MCDisassembler::Fail; 03138 03139 return S; 03140 } 03141 03142 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 03143 uint64_t Address, const void *Decoder) { 03144 DecodeStatus S = MCDisassembler::Success; 03145 03146 unsigned dst = fieldFromInstruction(Insn, 8, 3); 03147 unsigned imm = fieldFromInstruction(Insn, 0, 8); 03148 03149 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 03150 return MCDisassembler::Fail; 03151 03152 switch(Inst.getOpcode()) { 03153 default: 03154 return MCDisassembler::Fail; 03155 case ARM::tADR: 03156 break; // tADR does not explicitly represent the PC as an operand. 03157 case ARM::tADDrSPi: 03158 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03159 break; 03160 } 03161 03162 Inst.addOperand(MCOperand::CreateImm(imm)); 03163 return S; 03164 } 03165 03166 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 03167 uint64_t Address, const void *Decoder) { 03168 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 03169 true, 2, Inst, Decoder)) 03170 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 03171 return MCDisassembler::Success; 03172 } 03173 03174 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 03175 uint64_t Address, const void *Decoder) { 03176 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 03177 true, 4, Inst, Decoder)) 03178 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 03179 return MCDisassembler::Success; 03180 } 03181 03182 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 03183 uint64_t Address, const void *Decoder) { 03184 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 03185 true, 2, Inst, Decoder)) 03186 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 03187 return MCDisassembler::Success; 03188 } 03189 03190 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 03191 uint64_t Address, const void *Decoder) { 03192 DecodeStatus S = MCDisassembler::Success; 03193 03194 unsigned Rn = fieldFromInstruction(Val, 0, 3); 03195 unsigned Rm = fieldFromInstruction(Val, 3, 3); 03196 03197 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 03198 return MCDisassembler::Fail; 03199 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 03200 return MCDisassembler::Fail; 03201 03202 return S; 03203 } 03204 03205 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 03206 uint64_t Address, const void *Decoder) { 03207 DecodeStatus S = MCDisassembler::Success; 03208 03209 unsigned Rn = fieldFromInstruction(Val, 0, 3); 03210 unsigned imm = fieldFromInstruction(Val, 3, 5); 03211 03212 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 03213 return MCDisassembler::Fail; 03214 Inst.addOperand(MCOperand::CreateImm(imm)); 03215 03216 return S; 03217 } 03218 03219 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 03220 uint64_t Address, const void *Decoder) { 03221 unsigned imm = Val << 2; 03222 03223 Inst.addOperand(MCOperand::CreateImm(imm)); 03224 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 03225 03226 return MCDisassembler::Success; 03227 } 03228 03229 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 03230 uint64_t Address, const void *Decoder) { 03231 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03232 Inst.addOperand(MCOperand::CreateImm(Val)); 03233 03234 return MCDisassembler::Success; 03235 } 03236 03237 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 03238 uint64_t Address, const void *Decoder) { 03239 DecodeStatus S = MCDisassembler::Success; 03240 03241 unsigned Rn = fieldFromInstruction(Val, 6, 4); 03242 unsigned Rm = fieldFromInstruction(Val, 2, 4); 03243 unsigned imm = fieldFromInstruction(Val, 0, 2); 03244 03245 // Thumb stores cannot use PC as dest register. 03246 switch (Inst.getOpcode()) { 03247 case ARM::t2STRHs: 03248 case ARM::t2STRBs: 03249 case ARM::t2STRs: 03250 if (Rn == 15) 03251 return MCDisassembler::Fail; 03252 default: 03253 break; 03254 } 03255 03256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03257 return MCDisassembler::Fail; 03258 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 03259 return MCDisassembler::Fail; 03260 Inst.addOperand(MCOperand::CreateImm(imm)); 03261 03262 return S; 03263 } 03264 03265 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 03266 uint64_t Address, const void *Decoder) { 03267 DecodeStatus S = MCDisassembler::Success; 03268 03269 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03270 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03271 03272 if (Rn == 15) { 03273 switch (Inst.getOpcode()) { 03274 case ARM::t2LDRBs: 03275 Inst.setOpcode(ARM::t2LDRBpci); 03276 break; 03277 case ARM::t2LDRHs: 03278 Inst.setOpcode(ARM::t2LDRHpci); 03279 break; 03280 case ARM::t2LDRSHs: 03281 Inst.setOpcode(ARM::t2LDRSHpci); 03282 break; 03283 case ARM::t2LDRSBs: 03284 Inst.setOpcode(ARM::t2LDRSBpci); 03285 break; 03286 case ARM::t2LDRs: 03287 Inst.setOpcode(ARM::t2LDRpci); 03288 break; 03289 case ARM::t2PLDs: 03290 Inst.setOpcode(ARM::t2PLDpci); 03291 break; 03292 case ARM::t2PLIs: 03293 Inst.setOpcode(ARM::t2PLIpci); 03294 break; 03295 default: 03296 return MCDisassembler::Fail; 03297 } 03298 03299 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 03300 } 03301 03302 if (Rt == 15) { 03303 switch (Inst.getOpcode()) { 03304 case ARM::t2LDRSHs: 03305 return MCDisassembler::Fail; 03306 case ARM::t2LDRHs: 03307 // FIXME: this instruction is only available with MP extensions, 03308 // this should be checked first but we don't have access to the 03309 // feature bits here. 03310 Inst.setOpcode(ARM::t2PLDWs); 03311 break; 03312 default: 03313 break; 03314 } 03315 } 03316 03317 switch (Inst.getOpcode()) { 03318 case ARM::t2PLDs: 03319 case ARM::t2PLDWs: 03320 case ARM::t2PLIs: 03321 break; 03322 default: 03323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03324 return MCDisassembler::Fail; 03325 } 03326 03327 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 03328 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 03329 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 03330 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 03331 return MCDisassembler::Fail; 03332 03333 return S; 03334 } 03335 03336 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 03337 uint64_t Address, const void* Decoder) { 03338 DecodeStatus S = MCDisassembler::Success; 03339 03340 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03341 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03342 unsigned U = fieldFromInstruction(Insn, 9, 1); 03343 unsigned imm = fieldFromInstruction(Insn, 0, 8); 03344 imm |= (U << 8); 03345 imm |= (Rn << 9); 03346 03347 if (Rn == 15) { 03348 switch (Inst.getOpcode()) { 03349 case ARM::t2LDRi8: 03350 Inst.setOpcode(ARM::t2LDRpci); 03351 break; 03352 case ARM::t2LDRBi8: 03353 Inst.setOpcode(ARM::t2LDRBpci); 03354 break; 03355 case ARM::t2LDRSBi8: 03356 Inst.setOpcode(ARM::t2LDRSBpci); 03357 break; 03358 case ARM::t2LDRHi8: 03359 Inst.setOpcode(ARM::t2LDRHpci); 03360 break; 03361 case ARM::t2LDRSHi8: 03362 Inst.setOpcode(ARM::t2LDRSHpci); 03363 break; 03364 case ARM::t2PLDi8: 03365 Inst.setOpcode(ARM::t2PLDpci); 03366 break; 03367 case ARM::t2PLIi8: 03368 Inst.setOpcode(ARM::t2PLIpci); 03369 break; 03370 default: 03371 return MCDisassembler::Fail; 03372 } 03373 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 03374 } 03375 03376 if (Rt == 15) { 03377 switch (Inst.getOpcode()) { 03378 case ARM::t2LDRSHi8: 03379 return MCDisassembler::Fail; 03380 default: 03381 break; 03382 } 03383 } 03384 03385 switch (Inst.getOpcode()) { 03386 case ARM::t2PLDi8: 03387 case ARM::t2PLIi8: 03388 case ARM::t2PLDWi8: 03389 break; 03390 default: 03391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03392 return MCDisassembler::Fail; 03393 } 03394 03395 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 03396 return MCDisassembler::Fail; 03397 return S; 03398 } 03399 03400 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 03401 uint64_t Address, const void* Decoder) { 03402 DecodeStatus S = MCDisassembler::Success; 03403 03404 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03405 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03406 unsigned imm = fieldFromInstruction(Insn, 0, 12); 03407 imm |= (Rn << 13); 03408 03409 if (Rn == 15) { 03410 switch (Inst.getOpcode()) { 03411 case ARM::t2LDRi12: 03412 Inst.setOpcode(ARM::t2LDRpci); 03413 break; 03414 case ARM::t2LDRHi12: 03415 Inst.setOpcode(ARM::t2LDRHpci); 03416 break; 03417 case ARM::t2LDRSHi12: 03418 Inst.setOpcode(ARM::t2LDRSHpci); 03419 break; 03420 case ARM::t2LDRBi12: 03421 Inst.setOpcode(ARM::t2LDRBpci); 03422 break; 03423 case ARM::t2LDRSBi12: 03424 Inst.setOpcode(ARM::t2LDRSBpci); 03425 break; 03426 case ARM::t2PLDi12: 03427 Inst.setOpcode(ARM::t2PLDpci); 03428 break; 03429 case ARM::t2PLIi12: 03430 Inst.setOpcode(ARM::t2PLIpci); 03431 break; 03432 default: 03433 return MCDisassembler::Fail; 03434 } 03435 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 03436 } 03437 03438 if (Rt == 15) { 03439 switch (Inst.getOpcode()) { 03440 case ARM::t2LDRSHi12: 03441 return MCDisassembler::Fail; 03442 case ARM::t2LDRHi12: 03443 Inst.setOpcode(ARM::t2PLDi12); 03444 break; 03445 default: 03446 break; 03447 } 03448 } 03449 03450 switch (Inst.getOpcode()) { 03451 case ARM::t2PLDi12: 03452 case ARM::t2PLDWi12: 03453 case ARM::t2PLIi12: 03454 break; 03455 default: 03456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03457 return MCDisassembler::Fail; 03458 } 03459 03460 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 03461 return MCDisassembler::Fail; 03462 return S; 03463 } 03464 03465 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 03466 uint64_t Address, const void* Decoder) { 03467 DecodeStatus S = MCDisassembler::Success; 03468 03469 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03470 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03471 unsigned imm = fieldFromInstruction(Insn, 0, 8); 03472 imm |= (Rn << 9); 03473 03474 if (Rn == 15) { 03475 switch (Inst.getOpcode()) { 03476 case ARM::t2LDRT: 03477 Inst.setOpcode(ARM::t2LDRpci); 03478 break; 03479 case ARM::t2LDRBT: 03480 Inst.setOpcode(ARM::t2LDRBpci); 03481 break; 03482 case ARM::t2LDRHT: 03483 Inst.setOpcode(ARM::t2LDRHpci); 03484 break; 03485 case ARM::t2LDRSBT: 03486 Inst.setOpcode(ARM::t2LDRSBpci); 03487 break; 03488 case ARM::t2LDRSHT: 03489 Inst.setOpcode(ARM::t2LDRSHpci); 03490 break; 03491 default: 03492 return MCDisassembler::Fail; 03493 } 03494 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 03495 } 03496 03497 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 03498 return MCDisassembler::Fail; 03499 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 03500 return MCDisassembler::Fail; 03501 return S; 03502 } 03503 03504 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 03505 uint64_t Address, const void* Decoder) { 03506 DecodeStatus S = MCDisassembler::Success; 03507 03508 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03509 unsigned U = fieldFromInstruction(Insn, 23, 1); 03510 int imm = fieldFromInstruction(Insn, 0, 12); 03511 03512 if (Rt == 15) { 03513 switch (Inst.getOpcode()) { 03514 case ARM::t2LDRBpci: 03515 case ARM::t2LDRHpci: 03516 Inst.setOpcode(ARM::t2PLDpci); 03517 break; 03518 case ARM::t2LDRSBpci: 03519 Inst.setOpcode(ARM::t2PLIpci); 03520 break; 03521 case ARM::t2LDRSHpci: 03522 return MCDisassembler::Fail; 03523 default: 03524 break; 03525 } 03526 } 03527 03528 switch(Inst.getOpcode()) { 03529 case ARM::t2PLDpci: 03530 case ARM::t2PLIpci: 03531 break; 03532 default: 03533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03534 return MCDisassembler::Fail; 03535 } 03536 03537 if (!U) { 03538 // Special case for #-0. 03539 if (imm == 0) 03540 imm = INT32_MIN; 03541 else 03542 imm = -imm; 03543 } 03544 Inst.addOperand(MCOperand::CreateImm(imm)); 03545 03546 return S; 03547 } 03548 03549 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 03550 uint64_t Address, const void *Decoder) { 03551 if (Val == 0) 03552 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 03553 else { 03554 int imm = Val & 0xFF; 03555 03556 if (!(Val & 0x100)) imm *= -1; 03557 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 03558 } 03559 03560 return MCDisassembler::Success; 03561 } 03562 03563 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 03564 uint64_t Address, const void *Decoder) { 03565 DecodeStatus S = MCDisassembler::Success; 03566 03567 unsigned Rn = fieldFromInstruction(Val, 9, 4); 03568 unsigned imm = fieldFromInstruction(Val, 0, 9); 03569 03570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03571 return MCDisassembler::Fail; 03572 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 03573 return MCDisassembler::Fail; 03574 03575 return S; 03576 } 03577 03578 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 03579 uint64_t Address, const void *Decoder) { 03580 DecodeStatus S = MCDisassembler::Success; 03581 03582 unsigned Rn = fieldFromInstruction(Val, 8, 4); 03583 unsigned imm = fieldFromInstruction(Val, 0, 8); 03584 03585 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 03586 return MCDisassembler::Fail; 03587 03588 Inst.addOperand(MCOperand::CreateImm(imm)); 03589 03590 return S; 03591 } 03592 03593 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 03594 uint64_t Address, const void *Decoder) { 03595 int imm = Val & 0xFF; 03596 if (Val == 0) 03597 imm = INT32_MIN; 03598 else if (!(Val & 0x100)) 03599 imm *= -1; 03600 Inst.addOperand(MCOperand::CreateImm(imm)); 03601 03602 return MCDisassembler::Success; 03603 } 03604 03605 03606 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 03607 uint64_t Address, const void *Decoder) { 03608 DecodeStatus S = MCDisassembler::Success; 03609 03610 unsigned Rn = fieldFromInstruction(Val, 9, 4); 03611 unsigned imm = fieldFromInstruction(Val, 0, 9); 03612 03613 // Thumb stores cannot use PC as dest register. 03614 switch (Inst.getOpcode()) { 03615 case ARM::t2STRT: 03616 case ARM::t2STRBT: 03617 case ARM::t2STRHT: 03618 case ARM::t2STRi8: 03619 case ARM::t2STRHi8: 03620 case ARM::t2STRBi8: 03621 if (Rn == 15) 03622 return MCDisassembler::Fail; 03623 break; 03624 default: 03625 break; 03626 } 03627 03628 // Some instructions always use an additive offset. 03629 switch (Inst.getOpcode()) { 03630 case ARM::t2LDRT: 03631 case ARM::t2LDRBT: 03632 case ARM::t2LDRHT: 03633 case ARM::t2LDRSBT: 03634 case ARM::t2LDRSHT: 03635 case ARM::t2STRT: 03636 case ARM::t2STRBT: 03637 case ARM::t2STRHT: 03638 imm |= 0x100; 03639 break; 03640 default: 03641 break; 03642 } 03643 03644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03645 return MCDisassembler::Fail; 03646 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 03647 return MCDisassembler::Fail; 03648 03649 return S; 03650 } 03651 03652 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 03653 uint64_t Address, const void *Decoder) { 03654 DecodeStatus S = MCDisassembler::Success; 03655 03656 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 03657 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03658 unsigned addr = fieldFromInstruction(Insn, 0, 8); 03659 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 03660 addr |= Rn << 9; 03661 unsigned load = fieldFromInstruction(Insn, 20, 1); 03662 03663 if (Rn == 15) { 03664 switch (Inst.getOpcode()) { 03665 case ARM::t2LDR_PRE: 03666 case ARM::t2LDR_POST: 03667 Inst.setOpcode(ARM::t2LDRpci); 03668 break; 03669 case ARM::t2LDRB_PRE: 03670 case ARM::t2LDRB_POST: 03671 Inst.setOpcode(ARM::t2LDRBpci); 03672 break; 03673 case ARM::t2LDRH_PRE: 03674 case ARM::t2LDRH_POST: 03675 Inst.setOpcode(ARM::t2LDRHpci); 03676 break; 03677 case ARM::t2LDRSB_PRE: 03678 case ARM::t2LDRSB_POST: 03679 if (Rt == 15) 03680 Inst.setOpcode(ARM::t2PLIpci); 03681 else 03682 Inst.setOpcode(ARM::t2LDRSBpci); 03683 break; 03684 case ARM::t2LDRSH_PRE: 03685 case ARM::t2LDRSH_POST: 03686 Inst.setOpcode(ARM::t2LDRSHpci); 03687 break; 03688 default: 03689 return MCDisassembler::Fail; 03690 } 03691 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 03692 } 03693 03694 if (!load) { 03695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03696 return MCDisassembler::Fail; 03697 } 03698 03699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 03700 return MCDisassembler::Fail; 03701 03702 if (load) { 03703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03704 return MCDisassembler::Fail; 03705 } 03706 03707 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 03708 return MCDisassembler::Fail; 03709 03710 return S; 03711 } 03712 03713 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 03714 uint64_t Address, const void *Decoder) { 03715 DecodeStatus S = MCDisassembler::Success; 03716 03717 unsigned Rn = fieldFromInstruction(Val, 13, 4); 03718 unsigned imm = fieldFromInstruction(Val, 0, 12); 03719 03720 // Thumb stores cannot use PC as dest register. 03721 switch (Inst.getOpcode()) { 03722 case ARM::t2STRi12: 03723 case ARM::t2STRBi12: 03724 case ARM::t2STRHi12: 03725 if (Rn == 15) 03726 return MCDisassembler::Fail; 03727 default: 03728 break; 03729 } 03730 03731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03732 return MCDisassembler::Fail; 03733 Inst.addOperand(MCOperand::CreateImm(imm)); 03734 03735 return S; 03736 } 03737 03738 03739 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 03740 uint64_t Address, const void *Decoder) { 03741 unsigned imm = fieldFromInstruction(Insn, 0, 7); 03742 03743 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03744 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03745 Inst.addOperand(MCOperand::CreateImm(imm)); 03746 03747 return MCDisassembler::Success; 03748 } 03749 03750 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 03751 uint64_t Address, const void *Decoder) { 03752 DecodeStatus S = MCDisassembler::Success; 03753 03754 if (Inst.getOpcode() == ARM::tADDrSP) { 03755 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 03756 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 03757 03758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 03759 return MCDisassembler::Fail; 03760 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 03762 return MCDisassembler::Fail; 03763 } else if (Inst.getOpcode() == ARM::tADDspr) { 03764 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 03765 03766 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03767 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 03768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 03769 return MCDisassembler::Fail; 03770 } 03771 03772 return S; 03773 } 03774 03775 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 03776 uint64_t Address, const void *Decoder) { 03777 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 03778 unsigned flags = fieldFromInstruction(Insn, 0, 3); 03779 03780 Inst.addOperand(MCOperand::CreateImm(imod)); 03781 Inst.addOperand(MCOperand::CreateImm(flags)); 03782 03783 return MCDisassembler::Success; 03784 } 03785 03786 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 03787 uint64_t Address, const void *Decoder) { 03788 DecodeStatus S = MCDisassembler::Success; 03789 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03790 unsigned add = fieldFromInstruction(Insn, 4, 1); 03791 03792 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 03793 return MCDisassembler::Fail; 03794 Inst.addOperand(MCOperand::CreateImm(add)); 03795 03796 return S; 03797 } 03798 03799 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 03800 uint64_t Address, const void *Decoder) { 03801 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 03802 // Note only one trailing zero not two. Also the J1 and J2 values are from 03803 // the encoded instruction. So here change to I1 and I2 values via: 03804 // I1 = NOT(J1 EOR S); 03805 // I2 = NOT(J2 EOR S); 03806 // and build the imm32 with two trailing zeros as documented: 03807 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 03808 unsigned S = (Val >> 23) & 1; 03809 unsigned J1 = (Val >> 22) & 1; 03810 unsigned J2 = (Val >> 21) & 1; 03811 unsigned I1 = !(J1 ^ S); 03812 unsigned I2 = !(J2 ^ S); 03813 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 03814 int imm32 = SignExtend32<25>(tmp << 1); 03815 03816 if (!tryAddingSymbolicOperand(Address, 03817 (Address & ~2u) + imm32 + 4, 03818 true, 4, Inst, Decoder)) 03819 Inst.addOperand(MCOperand::CreateImm(imm32)); 03820 return MCDisassembler::Success; 03821 } 03822 03823 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 03824 uint64_t Address, const void *Decoder) { 03825 if (Val == 0xA || Val == 0xB) 03826 return MCDisassembler::Fail; 03827 03828 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 03829 .getFeatureBits(); 03830 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) 03831 return MCDisassembler::Fail; 03832 03833 Inst.addOperand(MCOperand::CreateImm(Val)); 03834 return MCDisassembler::Success; 03835 } 03836 03837 static DecodeStatus 03838 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 03839 uint64_t Address, const void *Decoder) { 03840 DecodeStatus S = MCDisassembler::Success; 03841 03842 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 03843 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 03844 03845 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 03846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 03847 return MCDisassembler::Fail; 03848 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 03849 return MCDisassembler::Fail; 03850 return S; 03851 } 03852 03853 static DecodeStatus 03854 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 03855 uint64_t Address, const void *Decoder) { 03856 DecodeStatus S = MCDisassembler::Success; 03857 03858 unsigned pred = fieldFromInstruction(Insn, 22, 4); 03859 if (pred == 0xE || pred == 0xF) { 03860 unsigned opc = fieldFromInstruction(Insn, 4, 28); 03861 switch (opc) { 03862 default: 03863 return MCDisassembler::Fail; 03864 case 0xf3bf8f4: 03865 Inst.setOpcode(ARM::t2DSB); 03866 break; 03867 case 0xf3bf8f5: 03868 Inst.setOpcode(ARM::t2DMB); 03869 break; 03870 case 0xf3bf8f6: 03871 Inst.setOpcode(ARM::t2ISB); 03872 break; 03873 } 03874 03875 unsigned imm = fieldFromInstruction(Insn, 0, 4); 03876 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 03877 } 03878 03879 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 03880 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 03881 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 03882 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 03883 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 03884 03885 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 03886 return MCDisassembler::Fail; 03887 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 03888 return MCDisassembler::Fail; 03889 03890 return S; 03891 } 03892 03893 // Decode a shifted immediate operand. These basically consist 03894 // of an 8-bit value, and a 4-bit directive that specifies either 03895 // a splat operation or a rotation. 03896 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 03897 uint64_t Address, const void *Decoder) { 03898 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 03899 if (ctrl == 0) { 03900 unsigned byte = fieldFromInstruction(Val, 8, 2); 03901 unsigned imm = fieldFromInstruction(Val, 0, 8); 03902 switch (byte) { 03903 case 0: 03904 Inst.addOperand(MCOperand::CreateImm(imm)); 03905 break; 03906 case 1: 03907 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 03908 break; 03909 case 2: 03910 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 03911 break; 03912 case 3: 03913 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 03914 (imm << 8) | imm)); 03915 break; 03916 } 03917 } else { 03918 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 03919 unsigned rot = fieldFromInstruction(Val, 7, 5); 03920 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 03921 Inst.addOperand(MCOperand::CreateImm(imm)); 03922 } 03923 03924 return MCDisassembler::Success; 03925 } 03926 03927 static DecodeStatus 03928 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 03929 uint64_t Address, const void *Decoder){ 03930 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 03931 true, 2, Inst, Decoder)) 03932 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 03933 return MCDisassembler::Success; 03934 } 03935 03936 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 03937 uint64_t Address, const void *Decoder){ 03938 // Val is passed in as S:J1:J2:imm10:imm11 03939 // Note no trailing zero after imm11. Also the J1 and J2 values are from 03940 // the encoded instruction. So here change to I1 and I2 values via: 03941 // I1 = NOT(J1 EOR S); 03942 // I2 = NOT(J2 EOR S); 03943 // and build the imm32 with one trailing zero as documented: 03944 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 03945 unsigned S = (Val >> 23) & 1; 03946 unsigned J1 = (Val >> 22) & 1; 03947 unsigned J2 = (Val >> 21) & 1; 03948 unsigned I1 = !(J1 ^ S); 03949 unsigned I2 = !(J2 ^ S); 03950 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 03951 int imm32 = SignExtend32<25>(tmp << 1); 03952 03953 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 03954 true, 4, Inst, Decoder)) 03955 Inst.addOperand(MCOperand::CreateImm(imm32)); 03956 return MCDisassembler::Success; 03957 } 03958 03959 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 03960 uint64_t Address, const void *Decoder) { 03961 if (Val & ~0xf) 03962 return MCDisassembler::Fail; 03963 03964 Inst.addOperand(MCOperand::CreateImm(Val)); 03965 return MCDisassembler::Success; 03966 } 03967 03968 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 03969 uint64_t Address, const void *Decoder) { 03970 if (Val & ~0xf) 03971 return MCDisassembler::Fail; 03972 03973 Inst.addOperand(MCOperand::CreateImm(Val)); 03974 return MCDisassembler::Success; 03975 } 03976 03977 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 03978 uint64_t Address, const void *Decoder) { 03979 DecodeStatus S = MCDisassembler::Success; 03980 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 03981 .getFeatureBits(); 03982 if (FeatureBits & ARM::FeatureMClass) { 03983 unsigned ValLow = Val & 0xff; 03984 03985 // Validate the SYSm value first. 03986 switch (ValLow) { 03987 case 0: // apsr 03988 case 1: // iapsr 03989 case 2: // eapsr 03990 case 3: // xpsr 03991 case 5: // ipsr 03992 case 6: // epsr 03993 case 7: // iepsr 03994 case 8: // msp 03995 case 9: // psp 03996 case 16: // primask 03997 case 20: // control 03998 break; 03999 case 17: // basepri 04000 case 18: // basepri_max 04001 case 19: // faultmask 04002 if (!(FeatureBits & ARM::HasV7Ops)) 04003 // Values basepri, basepri_max and faultmask are only valid for v7m. 04004 return MCDisassembler::Fail; 04005 break; 04006 default: 04007 return MCDisassembler::Fail; 04008 } 04009 04010 if (Inst.getOpcode() == ARM::t2MSR_M) { 04011 unsigned Mask = fieldFromInstruction(Val, 10, 2); 04012 if (!(FeatureBits & ARM::HasV7Ops)) { 04013 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 04014 // unpredictable. 04015 if (Mask != 2) 04016 S = MCDisassembler::SoftFail; 04017 } 04018 else { 04019 // The ARMv7-M architecture stores an additional 2-bit mask value in 04020 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 04021 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 04022 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 04023 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 04024 // only if the processor includes the DSP extension. 04025 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 04026 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) 04027 S = MCDisassembler::SoftFail; 04028 } 04029 } 04030 } else { 04031 // A/R class 04032 if (Val == 0) 04033 return MCDisassembler::Fail; 04034 } 04035 Inst.addOperand(MCOperand::CreateImm(Val)); 04036 return S; 04037 } 04038 04039 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 04040 uint64_t Address, const void *Decoder) { 04041 04042 unsigned R = fieldFromInstruction(Val, 5, 1); 04043 unsigned SysM = fieldFromInstruction(Val, 0, 5); 04044 04045 // The table of encodings for these banked registers comes from B9.2.3 of the 04046 // ARM ARM. There are patterns, but nothing regular enough to make this logic 04047 // neater. So by fiat, these values are UNPREDICTABLE: 04048 if (!R) { 04049 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 04050 SysM == 0x1a || SysM == 0x1b) 04051 return MCDisassembler::SoftFail; 04052 } else { 04053 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 04054 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 04055 return MCDisassembler::SoftFail; 04056 } 04057 04058 Inst.addOperand(MCOperand::CreateImm(Val)); 04059 return MCDisassembler::Success; 04060 } 04061 04062 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 04063 uint64_t Address, const void *Decoder) { 04064 DecodeStatus S = MCDisassembler::Success; 04065 04066 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04067 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04068 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04069 04070 if (Rn == 0xF) 04071 S = MCDisassembler::SoftFail; 04072 04073 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 04074 return MCDisassembler::Fail; 04075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04076 return MCDisassembler::Fail; 04077 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04078 return MCDisassembler::Fail; 04079 04080 return S; 04081 } 04082 04083 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 04084 uint64_t Address, const void *Decoder){ 04085 DecodeStatus S = MCDisassembler::Success; 04086 04087 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04088 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 04089 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04090 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04091 04092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 04093 return MCDisassembler::Fail; 04094 04095 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 04096 S = MCDisassembler::SoftFail; 04097 04098 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 04099 return MCDisassembler::Fail; 04100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04101 return MCDisassembler::Fail; 04102 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04103 return MCDisassembler::Fail; 04104 04105 return S; 04106 } 04107 04108 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 04109 uint64_t Address, const void *Decoder) { 04110 DecodeStatus S = MCDisassembler::Success; 04111 04112 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04113 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04114 unsigned imm = fieldFromInstruction(Insn, 0, 12); 04115 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 04116 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 04117 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04118 04119 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 04120 04121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 04122 return MCDisassembler::Fail; 04123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04124 return MCDisassembler::Fail; 04125 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 04126 return MCDisassembler::Fail; 04127 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04128 return MCDisassembler::Fail; 04129 04130 return S; 04131 } 04132 04133 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 04134 uint64_t Address, const void *Decoder) { 04135 DecodeStatus S = MCDisassembler::Success; 04136 04137 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04138 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04139 unsigned imm = fieldFromInstruction(Insn, 0, 12); 04140 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 04141 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 04142 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04143 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04144 04145 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 04146 if (Rm == 0xF) S = MCDisassembler::SoftFail; 04147 04148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 04149 return MCDisassembler::Fail; 04150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04151 return MCDisassembler::Fail; 04152 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 04153 return MCDisassembler::Fail; 04154 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04155 return MCDisassembler::Fail; 04156 04157 return S; 04158 } 04159 04160 04161 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 04162 uint64_t Address, const void *Decoder) { 04163 DecodeStatus S = MCDisassembler::Success; 04164 04165 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04166 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04167 unsigned imm = fieldFromInstruction(Insn, 0, 12); 04168 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 04169 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 04170 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04171 04172 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 04173 04174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04175 return MCDisassembler::Fail; 04176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 04177 return MCDisassembler::Fail; 04178 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 04179 return MCDisassembler::Fail; 04180 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04181 return MCDisassembler::Fail; 04182 04183 return S; 04184 } 04185 04186 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 04187 uint64_t Address, const void *Decoder) { 04188 DecodeStatus S = MCDisassembler::Success; 04189 04190 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04191 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04192 unsigned imm = fieldFromInstruction(Insn, 0, 12); 04193 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 04194 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 04195 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04196 04197 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 04198 04199 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04200 return MCDisassembler::Fail; 04201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 04202 return MCDisassembler::Fail; 04203 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 04204 return MCDisassembler::Fail; 04205 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04206 return MCDisassembler::Fail; 04207 04208 return S; 04209 } 04210 04211 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 04212 uint64_t Address, const void *Decoder) { 04213 DecodeStatus S = MCDisassembler::Success; 04214 04215 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04216 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04217 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04218 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04219 unsigned size = fieldFromInstruction(Insn, 10, 2); 04220 04221 unsigned align = 0; 04222 unsigned index = 0; 04223 switch (size) { 04224 default: 04225 return MCDisassembler::Fail; 04226 case 0: 04227 if (fieldFromInstruction(Insn, 4, 1)) 04228 return MCDisassembler::Fail; // UNDEFINED 04229 index = fieldFromInstruction(Insn, 5, 3); 04230 break; 04231 case 1: 04232 if (fieldFromInstruction(Insn, 5, 1)) 04233 return MCDisassembler::Fail; // UNDEFINED 04234 index = fieldFromInstruction(Insn, 6, 2); 04235 if (fieldFromInstruction(Insn, 4, 1)) 04236 align = 2; 04237 break; 04238 case 2: 04239 if (fieldFromInstruction(Insn, 6, 1)) 04240 return MCDisassembler::Fail; // UNDEFINED 04241 index = fieldFromInstruction(Insn, 7, 1); 04242 04243 switch (fieldFromInstruction(Insn, 4, 2)) { 04244 case 0 : 04245 align = 0; break; 04246 case 3: 04247 align = 4; break; 04248 default: 04249 return MCDisassembler::Fail; 04250 } 04251 break; 04252 } 04253 04254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04255 return MCDisassembler::Fail; 04256 if (Rm != 0xF) { // Writeback 04257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04258 return MCDisassembler::Fail; 04259 } 04260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04261 return MCDisassembler::Fail; 04262 Inst.addOperand(MCOperand::CreateImm(align)); 04263 if (Rm != 0xF) { 04264 if (Rm != 0xD) { 04265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04266 return MCDisassembler::Fail; 04267 } else 04268 Inst.addOperand(MCOperand::CreateReg(0)); 04269 } 04270 04271 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04272 return MCDisassembler::Fail; 04273 Inst.addOperand(MCOperand::CreateImm(index)); 04274 04275 return S; 04276 } 04277 04278 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 04279 uint64_t Address, const void *Decoder) { 04280 DecodeStatus S = MCDisassembler::Success; 04281 04282 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04283 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04284 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04285 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04286 unsigned size = fieldFromInstruction(Insn, 10, 2); 04287 04288 unsigned align = 0; 04289 unsigned index = 0; 04290 switch (size) { 04291 default: 04292 return MCDisassembler::Fail; 04293 case 0: 04294 if (fieldFromInstruction(Insn, 4, 1)) 04295 return MCDisassembler::Fail; // UNDEFINED 04296 index = fieldFromInstruction(Insn, 5, 3); 04297 break; 04298 case 1: 04299 if (fieldFromInstruction(Insn, 5, 1)) 04300 return MCDisassembler::Fail; // UNDEFINED 04301 index = fieldFromInstruction(Insn, 6, 2); 04302 if (fieldFromInstruction(Insn, 4, 1)) 04303 align = 2; 04304 break; 04305 case 2: 04306 if (fieldFromInstruction(Insn, 6, 1)) 04307 return MCDisassembler::Fail; // UNDEFINED 04308 index = fieldFromInstruction(Insn, 7, 1); 04309 04310 switch (fieldFromInstruction(Insn, 4, 2)) { 04311 case 0: 04312 align = 0; break; 04313 case 3: 04314 align = 4; break; 04315 default: 04316 return MCDisassembler::Fail; 04317 } 04318 break; 04319 } 04320 04321 if (Rm != 0xF) { // Writeback 04322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04323 return MCDisassembler::Fail; 04324 } 04325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04326 return MCDisassembler::Fail; 04327 Inst.addOperand(MCOperand::CreateImm(align)); 04328 if (Rm != 0xF) { 04329 if (Rm != 0xD) { 04330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04331 return MCDisassembler::Fail; 04332 } else 04333 Inst.addOperand(MCOperand::CreateReg(0)); 04334 } 04335 04336 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04337 return MCDisassembler::Fail; 04338 Inst.addOperand(MCOperand::CreateImm(index)); 04339 04340 return S; 04341 } 04342 04343 04344 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 04345 uint64_t Address, const void *Decoder) { 04346 DecodeStatus S = MCDisassembler::Success; 04347 04348 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04349 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04350 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04351 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04352 unsigned size = fieldFromInstruction(Insn, 10, 2); 04353 04354 unsigned align = 0; 04355 unsigned index = 0; 04356 unsigned inc = 1; 04357 switch (size) { 04358 default: 04359 return MCDisassembler::Fail; 04360 case 0: 04361 index = fieldFromInstruction(Insn, 5, 3); 04362 if (fieldFromInstruction(Insn, 4, 1)) 04363 align = 2; 04364 break; 04365 case 1: 04366 index = fieldFromInstruction(Insn, 6, 2); 04367 if (fieldFromInstruction(Insn, 4, 1)) 04368 align = 4; 04369 if (fieldFromInstruction(Insn, 5, 1)) 04370 inc = 2; 04371 break; 04372 case 2: 04373 if (fieldFromInstruction(Insn, 5, 1)) 04374 return MCDisassembler::Fail; // UNDEFINED 04375 index = fieldFromInstruction(Insn, 7, 1); 04376 if (fieldFromInstruction(Insn, 4, 1) != 0) 04377 align = 8; 04378 if (fieldFromInstruction(Insn, 6, 1)) 04379 inc = 2; 04380 break; 04381 } 04382 04383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04384 return MCDisassembler::Fail; 04385 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04386 return MCDisassembler::Fail; 04387 if (Rm != 0xF) { // Writeback 04388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04389 return MCDisassembler::Fail; 04390 } 04391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04392 return MCDisassembler::Fail; 04393 Inst.addOperand(MCOperand::CreateImm(align)); 04394 if (Rm != 0xF) { 04395 if (Rm != 0xD) { 04396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04397 return MCDisassembler::Fail; 04398 } else 04399 Inst.addOperand(MCOperand::CreateReg(0)); 04400 } 04401 04402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04403 return MCDisassembler::Fail; 04404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04405 return MCDisassembler::Fail; 04406 Inst.addOperand(MCOperand::CreateImm(index)); 04407 04408 return S; 04409 } 04410 04411 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 04412 uint64_t Address, const void *Decoder) { 04413 DecodeStatus S = MCDisassembler::Success; 04414 04415 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04416 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04417 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04418 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04419 unsigned size = fieldFromInstruction(Insn, 10, 2); 04420 04421 unsigned align = 0; 04422 unsigned index = 0; 04423 unsigned inc = 1; 04424 switch (size) { 04425 default: 04426 return MCDisassembler::Fail; 04427 case 0: 04428 index = fieldFromInstruction(Insn, 5, 3); 04429 if (fieldFromInstruction(Insn, 4, 1)) 04430 align = 2; 04431 break; 04432 case 1: 04433 index = fieldFromInstruction(Insn, 6, 2); 04434 if (fieldFromInstruction(Insn, 4, 1)) 04435 align = 4; 04436 if (fieldFromInstruction(Insn, 5, 1)) 04437 inc = 2; 04438 break; 04439 case 2: 04440 if (fieldFromInstruction(Insn, 5, 1)) 04441 return MCDisassembler::Fail; // UNDEFINED 04442 index = fieldFromInstruction(Insn, 7, 1); 04443 if (fieldFromInstruction(Insn, 4, 1) != 0) 04444 align = 8; 04445 if (fieldFromInstruction(Insn, 6, 1)) 04446 inc = 2; 04447 break; 04448 } 04449 04450 if (Rm != 0xF) { // Writeback 04451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04452 return MCDisassembler::Fail; 04453 } 04454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04455 return MCDisassembler::Fail; 04456 Inst.addOperand(MCOperand::CreateImm(align)); 04457 if (Rm != 0xF) { 04458 if (Rm != 0xD) { 04459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04460 return MCDisassembler::Fail; 04461 } else 04462 Inst.addOperand(MCOperand::CreateReg(0)); 04463 } 04464 04465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04466 return MCDisassembler::Fail; 04467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04468 return MCDisassembler::Fail; 04469 Inst.addOperand(MCOperand::CreateImm(index)); 04470 04471 return S; 04472 } 04473 04474 04475 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 04476 uint64_t Address, const void *Decoder) { 04477 DecodeStatus S = MCDisassembler::Success; 04478 04479 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04480 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04481 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04482 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04483 unsigned size = fieldFromInstruction(Insn, 10, 2); 04484 04485 unsigned align = 0; 04486 unsigned index = 0; 04487 unsigned inc = 1; 04488 switch (size) { 04489 default: 04490 return MCDisassembler::Fail; 04491 case 0: 04492 if (fieldFromInstruction(Insn, 4, 1)) 04493 return MCDisassembler::Fail; // UNDEFINED 04494 index = fieldFromInstruction(Insn, 5, 3); 04495 break; 04496 case 1: 04497 if (fieldFromInstruction(Insn, 4, 1)) 04498 return MCDisassembler::Fail; // UNDEFINED 04499 index = fieldFromInstruction(Insn, 6, 2); 04500 if (fieldFromInstruction(Insn, 5, 1)) 04501 inc = 2; 04502 break; 04503 case 2: 04504 if (fieldFromInstruction(Insn, 4, 2)) 04505 return MCDisassembler::Fail; // UNDEFINED 04506 index = fieldFromInstruction(Insn, 7, 1); 04507 if (fieldFromInstruction(Insn, 6, 1)) 04508 inc = 2; 04509 break; 04510 } 04511 04512 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04513 return MCDisassembler::Fail; 04514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04515 return MCDisassembler::Fail; 04516 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04517 return MCDisassembler::Fail; 04518 04519 if (Rm != 0xF) { // Writeback 04520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04521 return MCDisassembler::Fail; 04522 } 04523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04524 return MCDisassembler::Fail; 04525 Inst.addOperand(MCOperand::CreateImm(align)); 04526 if (Rm != 0xF) { 04527 if (Rm != 0xD) { 04528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04529 return MCDisassembler::Fail; 04530 } else 04531 Inst.addOperand(MCOperand::CreateReg(0)); 04532 } 04533 04534 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04535 return MCDisassembler::Fail; 04536 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04537 return MCDisassembler::Fail; 04538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04539 return MCDisassembler::Fail; 04540 Inst.addOperand(MCOperand::CreateImm(index)); 04541 04542 return S; 04543 } 04544 04545 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 04546 uint64_t Address, const void *Decoder) { 04547 DecodeStatus S = MCDisassembler::Success; 04548 04549 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04550 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04551 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04552 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04553 unsigned size = fieldFromInstruction(Insn, 10, 2); 04554 04555 unsigned align = 0; 04556 unsigned index = 0; 04557 unsigned inc = 1; 04558 switch (size) { 04559 default: 04560 return MCDisassembler::Fail; 04561 case 0: 04562 if (fieldFromInstruction(Insn, 4, 1)) 04563 return MCDisassembler::Fail; // UNDEFINED 04564 index = fieldFromInstruction(Insn, 5, 3); 04565 break; 04566 case 1: 04567 if (fieldFromInstruction(Insn, 4, 1)) 04568 return MCDisassembler::Fail; // UNDEFINED 04569 index = fieldFromInstruction(Insn, 6, 2); 04570 if (fieldFromInstruction(Insn, 5, 1)) 04571 inc = 2; 04572 break; 04573 case 2: 04574 if (fieldFromInstruction(Insn, 4, 2)) 04575 return MCDisassembler::Fail; // UNDEFINED 04576 index = fieldFromInstruction(Insn, 7, 1); 04577 if (fieldFromInstruction(Insn, 6, 1)) 04578 inc = 2; 04579 break; 04580 } 04581 04582 if (Rm != 0xF) { // Writeback 04583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04584 return MCDisassembler::Fail; 04585 } 04586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04587 return MCDisassembler::Fail; 04588 Inst.addOperand(MCOperand::CreateImm(align)); 04589 if (Rm != 0xF) { 04590 if (Rm != 0xD) { 04591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04592 return MCDisassembler::Fail; 04593 } else 04594 Inst.addOperand(MCOperand::CreateReg(0)); 04595 } 04596 04597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04598 return MCDisassembler::Fail; 04599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04600 return MCDisassembler::Fail; 04601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04602 return MCDisassembler::Fail; 04603 Inst.addOperand(MCOperand::CreateImm(index)); 04604 04605 return S; 04606 } 04607 04608 04609 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 04610 uint64_t Address, const void *Decoder) { 04611 DecodeStatus S = MCDisassembler::Success; 04612 04613 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04614 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04615 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04616 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04617 unsigned size = fieldFromInstruction(Insn, 10, 2); 04618 04619 unsigned align = 0; 04620 unsigned index = 0; 04621 unsigned inc = 1; 04622 switch (size) { 04623 default: 04624 return MCDisassembler::Fail; 04625 case 0: 04626 if (fieldFromInstruction(Insn, 4, 1)) 04627 align = 4; 04628 index = fieldFromInstruction(Insn, 5, 3); 04629 break; 04630 case 1: 04631 if (fieldFromInstruction(Insn, 4, 1)) 04632 align = 8; 04633 index = fieldFromInstruction(Insn, 6, 2); 04634 if (fieldFromInstruction(Insn, 5, 1)) 04635 inc = 2; 04636 break; 04637 case 2: 04638 switch (fieldFromInstruction(Insn, 4, 2)) { 04639 case 0: 04640 align = 0; break; 04641 case 3: 04642 return MCDisassembler::Fail; 04643 default: 04644 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 04645 } 04646 04647 index = fieldFromInstruction(Insn, 7, 1); 04648 if (fieldFromInstruction(Insn, 6, 1)) 04649 inc = 2; 04650 break; 04651 } 04652 04653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04654 return MCDisassembler::Fail; 04655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04656 return MCDisassembler::Fail; 04657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04658 return MCDisassembler::Fail; 04659 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 04660 return MCDisassembler::Fail; 04661 04662 if (Rm != 0xF) { // Writeback 04663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04664 return MCDisassembler::Fail; 04665 } 04666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04667 return MCDisassembler::Fail; 04668 Inst.addOperand(MCOperand::CreateImm(align)); 04669 if (Rm != 0xF) { 04670 if (Rm != 0xD) { 04671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04672 return MCDisassembler::Fail; 04673 } else 04674 Inst.addOperand(MCOperand::CreateReg(0)); 04675 } 04676 04677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04678 return MCDisassembler::Fail; 04679 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04680 return MCDisassembler::Fail; 04681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04682 return MCDisassembler::Fail; 04683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 04684 return MCDisassembler::Fail; 04685 Inst.addOperand(MCOperand::CreateImm(index)); 04686 04687 return S; 04688 } 04689 04690 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 04691 uint64_t Address, const void *Decoder) { 04692 DecodeStatus S = MCDisassembler::Success; 04693 04694 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04695 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 04696 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 04697 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 04698 unsigned size = fieldFromInstruction(Insn, 10, 2); 04699 04700 unsigned align = 0; 04701 unsigned index = 0; 04702 unsigned inc = 1; 04703 switch (size) { 04704 default: 04705 return MCDisassembler::Fail; 04706 case 0: 04707 if (fieldFromInstruction(Insn, 4, 1)) 04708 align = 4; 04709 index = fieldFromInstruction(Insn, 5, 3); 04710 break; 04711 case 1: 04712 if (fieldFromInstruction(Insn, 4, 1)) 04713 align = 8; 04714 index = fieldFromInstruction(Insn, 6, 2); 04715 if (fieldFromInstruction(Insn, 5, 1)) 04716 inc = 2; 04717 break; 04718 case 2: 04719 switch (fieldFromInstruction(Insn, 4, 2)) { 04720 case 0: 04721 align = 0; break; 04722 case 3: 04723 return MCDisassembler::Fail; 04724 default: 04725 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 04726 } 04727 04728 index = fieldFromInstruction(Insn, 7, 1); 04729 if (fieldFromInstruction(Insn, 6, 1)) 04730 inc = 2; 04731 break; 04732 } 04733 04734 if (Rm != 0xF) { // Writeback 04735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04736 return MCDisassembler::Fail; 04737 } 04738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 04739 return MCDisassembler::Fail; 04740 Inst.addOperand(MCOperand::CreateImm(align)); 04741 if (Rm != 0xF) { 04742 if (Rm != 0xD) { 04743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 04744 return MCDisassembler::Fail; 04745 } else 04746 Inst.addOperand(MCOperand::CreateReg(0)); 04747 } 04748 04749 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 04750 return MCDisassembler::Fail; 04751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 04752 return MCDisassembler::Fail; 04753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 04754 return MCDisassembler::Fail; 04755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 04756 return MCDisassembler::Fail; 04757 Inst.addOperand(MCOperand::CreateImm(index)); 04758 04759 return S; 04760 } 04761 04762 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 04763 uint64_t Address, const void *Decoder) { 04764 DecodeStatus S = MCDisassembler::Success; 04765 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04766 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 04767 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 04768 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04769 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 04770 04771 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 04772 S = MCDisassembler::SoftFail; 04773 04774 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 04775 return MCDisassembler::Fail; 04776 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 04777 return MCDisassembler::Fail; 04778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 04779 return MCDisassembler::Fail; 04780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 04781 return MCDisassembler::Fail; 04782 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04783 return MCDisassembler::Fail; 04784 04785 return S; 04786 } 04787 04788 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 04789 uint64_t Address, const void *Decoder) { 04790 DecodeStatus S = MCDisassembler::Success; 04791 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04792 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 04793 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 04794 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04795 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 04796 04797 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 04798 S = MCDisassembler::SoftFail; 04799 04800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 04801 return MCDisassembler::Fail; 04802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 04803 return MCDisassembler::Fail; 04804 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 04805 return MCDisassembler::Fail; 04806 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 04807 return MCDisassembler::Fail; 04808 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04809 return MCDisassembler::Fail; 04810 04811 return S; 04812 } 04813 04814 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 04815 uint64_t Address, const void *Decoder) { 04816 DecodeStatus S = MCDisassembler::Success; 04817 unsigned pred = fieldFromInstruction(Insn, 4, 4); 04818 unsigned mask = fieldFromInstruction(Insn, 0, 4); 04819 04820 if (pred == 0xF) { 04821 pred = 0xE; 04822 S = MCDisassembler::SoftFail; 04823 } 04824 04825 if (mask == 0x0) 04826 return MCDisassembler::Fail; 04827 04828 Inst.addOperand(MCOperand::CreateImm(pred)); 04829 Inst.addOperand(MCOperand::CreateImm(mask)); 04830 return S; 04831 } 04832 04833 static DecodeStatus 04834 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 04835 uint64_t Address, const void *Decoder) { 04836 DecodeStatus S = MCDisassembler::Success; 04837 04838 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04839 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 04840 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04841 unsigned addr = fieldFromInstruction(Insn, 0, 8); 04842 unsigned W = fieldFromInstruction(Insn, 21, 1); 04843 unsigned U = fieldFromInstruction(Insn, 23, 1); 04844 unsigned P = fieldFromInstruction(Insn, 24, 1); 04845 bool writeback = (W == 1) | (P == 0); 04846 04847 addr |= (U << 8) | (Rn << 9); 04848 04849 if (writeback && (Rn == Rt || Rn == Rt2)) 04850 Check(S, MCDisassembler::SoftFail); 04851 if (Rt == Rt2) 04852 Check(S, MCDisassembler::SoftFail); 04853 04854 // Rt 04855 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 04856 return MCDisassembler::Fail; 04857 // Rt2 04858 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 04859 return MCDisassembler::Fail; 04860 // Writeback operand 04861 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 04862 return MCDisassembler::Fail; 04863 // addr 04864 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 04865 return MCDisassembler::Fail; 04866 04867 return S; 04868 } 04869 04870 static DecodeStatus 04871 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 04872 uint64_t Address, const void *Decoder) { 04873 DecodeStatus S = MCDisassembler::Success; 04874 04875 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04876 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 04877 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04878 unsigned addr = fieldFromInstruction(Insn, 0, 8); 04879 unsigned W = fieldFromInstruction(Insn, 21, 1); 04880 unsigned U = fieldFromInstruction(Insn, 23, 1); 04881 unsigned P = fieldFromInstruction(Insn, 24, 1); 04882 bool writeback = (W == 1) | (P == 0); 04883 04884 addr |= (U << 8) | (Rn << 9); 04885 04886 if (writeback && (Rn == Rt || Rn == Rt2)) 04887 Check(S, MCDisassembler::SoftFail); 04888 04889 // Writeback operand 04890 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 04891 return MCDisassembler::Fail; 04892 // Rt 04893 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 04894 return MCDisassembler::Fail; 04895 // Rt2 04896 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 04897 return MCDisassembler::Fail; 04898 // addr 04899 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 04900 return MCDisassembler::Fail; 04901 04902 return S; 04903 } 04904 04905 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 04906 uint64_t Address, const void *Decoder) { 04907 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 04908 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 04909 if (sign1 != sign2) return MCDisassembler::Fail; 04910 04911 unsigned Val = fieldFromInstruction(Insn, 0, 8); 04912 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 04913 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 04914 Val |= sign1 << 12; 04915 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 04916 04917 return MCDisassembler::Success; 04918 } 04919 04920 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 04921 uint64_t Address, 04922 const void *Decoder) { 04923 DecodeStatus S = MCDisassembler::Success; 04924 04925 // Shift of "asr #32" is not allowed in Thumb2 mode. 04926 if (Val == 0x20) S = MCDisassembler::SoftFail; 04927 Inst.addOperand(MCOperand::CreateImm(Val)); 04928 return S; 04929 } 04930 04931 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 04932 uint64_t Address, const void *Decoder) { 04933 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 04934 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 04935 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 04936 unsigned pred = fieldFromInstruction(Insn, 28, 4); 04937 04938 if (pred == 0xF) 04939 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 04940 04941 DecodeStatus S = MCDisassembler::Success; 04942 04943 if (Rt == Rn || Rn == Rt2) 04944 S = MCDisassembler::SoftFail; 04945 04946 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 04947 return MCDisassembler::Fail; 04948 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 04949 return MCDisassembler::Fail; 04950 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 04951 return MCDisassembler::Fail; 04952 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 04953 return MCDisassembler::Fail; 04954 04955 return S; 04956 } 04957 04958 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 04959 uint64_t Address, const void *Decoder) { 04960 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 04961 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 04962 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 04963 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 04964 unsigned imm = fieldFromInstruction(Insn, 16, 6); 04965 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 04966 unsigned op = fieldFromInstruction(Insn, 5, 1); 04967 04968 DecodeStatus S = MCDisassembler::Success; 04969 04970 // VMOVv2f32 is ambiguous with these decodings. 04971 if (!(imm & 0x38) && cmode == 0xF) { 04972 if (op == 1) return MCDisassembler::Fail; 04973 Inst.setOpcode(ARM::VMOVv2f32); 04974 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 04975 } 04976 04977 if (!(imm & 0x20)) return MCDisassembler::Fail; 04978 04979 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 04980 return MCDisassembler::Fail; 04981 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 04982 return MCDisassembler::Fail; 04983 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 04984 04985 return S; 04986 } 04987 04988 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 04989 uint64_t Address, const void *Decoder) { 04990 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 04991 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 04992 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 04993 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 04994 unsigned imm = fieldFromInstruction(Insn, 16, 6); 04995 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 04996 unsigned op = fieldFromInstruction(Insn, 5, 1); 04997 04998 DecodeStatus S = MCDisassembler::Success; 04999 05000 // VMOVv4f32 is ambiguous with these decodings. 05001 if (!(imm & 0x38) && cmode == 0xF) { 05002 if (op == 1) return MCDisassembler::Fail; 05003 Inst.setOpcode(ARM::VMOVv4f32); 05004 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 05005 } 05006 05007 if (!(imm & 0x20)) return MCDisassembler::Fail; 05008 05009 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 05010 return MCDisassembler::Fail; 05011 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 05012 return MCDisassembler::Fail; 05013 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 05014 05015 return S; 05016 } 05017 05018 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 05019 uint64_t Address, const void *Decoder) { 05020 DecodeStatus S = MCDisassembler::Success; 05021 05022 unsigned Rn = fieldFromInstruction(Val, 16, 4); 05023 unsigned Rt = fieldFromInstruction(Val, 12, 4); 05024 unsigned Rm = fieldFromInstruction(Val, 0, 4); 05025 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 05026 unsigned Cond = fieldFromInstruction(Val, 28, 4); 05027 05028 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 05029 S = MCDisassembler::SoftFail; 05030 05031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 05032 return MCDisassembler::Fail; 05033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 05034 return MCDisassembler::Fail; 05035 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 05036 return MCDisassembler::Fail; 05037 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 05038 return MCDisassembler::Fail; 05039 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 05040 return MCDisassembler::Fail; 05041 05042 return S; 05043 } 05044 05045 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 05046 uint64_t Address, const void *Decoder) { 05047 05048 DecodeStatus S = MCDisassembler::Success; 05049 05050 unsigned CRm = fieldFromInstruction(Val, 0, 4); 05051 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 05052 unsigned cop = fieldFromInstruction(Val, 8, 4); 05053 unsigned Rt = fieldFromInstruction(Val, 12, 4); 05054 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 05055 05056 if ((cop & ~0x1) == 0xa) 05057 return MCDisassembler::Fail; 05058 05059 if (Rt == Rt2) 05060 S = MCDisassembler::SoftFail; 05061 05062 Inst.addOperand(MCOperand::CreateImm(cop)); 05063 Inst.addOperand(MCOperand::CreateImm(opc1)); 05064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 05065 return MCDisassembler::Fail; 05066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 05067 return MCDisassembler::Fail; 05068 Inst.addOperand(MCOperand::CreateImm(CRm)); 05069 05070 return S; 05071 } 05072
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