#include <MCInstrDesc.h>
Public Member Functions | |
| int | getOperandConstraint (unsigned OpNum, MCOI::OperandConstraint Constraint) const |
| Returns the value of the specific constraint if it is set. Returns -1 if it is not set. | |
| bool | getDeprecatedInfo (MCInst &MI, MCSubtargetInfo &STI, std::string &Info) const |
Returns true if a certain instruction is deprecated and if so returns the reason in Info. | |
| unsigned | getOpcode () const |
| Return the opcode number for this descriptor. | |
| unsigned | getNumOperands () const |
| Return the number of declared MachineOperands for this MachineInstruction. Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well. | |
| unsigned | getNumDefs () const |
| Return the number of MachineOperands that are register definitions. Register definitions always occur at the start of the machine operand list. This is the number of "outs" in the .td file, and does not include implicit defs. | |
| unsigned | getFlags () const |
| Return flags of this instruction. | |
| bool | isVariadic () const |
| Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present). | |
| bool | hasOptionalDef () const |
| Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set. | |
| bool | isPseudo () const |
| Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. | |
| bool | isReturn () const |
| Return true if the instruction is a return. | |
| bool | isCall () const |
| Return true if the instruction is a call. | |
| bool | isBarrier () const |
| Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions. | |
| bool | isTerminator () const |
| Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions. | |
| bool | isBranch () const |
| Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information. | |
| bool | isIndirectBranch () const |
| Return true if this is an indirect branch, such as a branch through a register. | |
| bool | isConditionalBranch () const |
| Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch. | |
| bool | isUnconditionalBranch () const |
| Return true if this is a branch which always transfers control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch. | |
| bool | mayAffectControlFlow (const MCInst &MI, const MCRegisterInfo &RI) const |
| Return true if this is a branch or an instruction which directly writes to the program counter. Considered 'may' affect rather than 'does' affect as things like predication are not taken into account. | |
| bool | isPredicable () const |
| Return true if this instruction has a predicate operand that controls execution. It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction. | |
| bool | isCompare () const |
| Return true if this instruction is a comparison. | |
| bool | isMoveImmediate () const |
| Return true if this instruction is a move immediate (including conditional moves) instruction. | |
| bool | isBitcast () const |
| Return true if this instruction is a bitcast instruction. | |
| bool | isSelect () const |
| Return true if this is a select instruction. | |
| bool | isNotDuplicable () const |
| Return true if this instruction cannot be safely duplicated. For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors. | |
| bool | hasDelaySlot () const |
| bool | canFoldAsLoad () const |
| bool | isRegSequenceLike () const |
| Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. | |
| bool | isExtractSubregLike () const |
| Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1. | |
| bool | isInsertSubregLike () const |
| Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) | |
| bool | mayLoad () const |
| Return true if this instruction could possibly read memory. Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example. | |
| bool | mayStore () const |
| Return true if this instruction could possibly modify memory. Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example. | |
| bool | hasUnmodeledSideEffects () const |
| bool | isCommutable () const |
| bool | isConvertibleTo3Addr () const |
| bool | usesCustomInsertionHook () const |
| bool | hasPostISelHook () const |
| bool | isRematerializable () const |
| bool | isAsCheapAsAMove () const |
| bool | hasExtraSrcRegAllocReq () const |
| bool | hasExtraDefRegAllocReq () const |
| const uint16_t * | getImplicitUses () const |
| unsigned | getNumImplicitUses () const |
| Return the number of implicit uses this instruction has. | |
| const uint16_t * | getImplicitDefs () const |
| unsigned | getNumImplicitDefs () const |
| Return the number of implicit defs this instruct has. | |
| bool | hasImplicitUseOfPhysReg (unsigned Reg) const |
| Return true if this instruction implicitly uses the specified physical register. | |
| bool | hasImplicitDefOfPhysReg (unsigned Reg, const MCRegisterInfo *MRI=nullptr) const |
| Return true if this instruction implicitly defines the specified physical register. | |
| bool | hasDefOfPhysReg (const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const |
| Return true if this instruction defines the specified physical register, either explicitly or implicitly. | |
| unsigned | getSchedClass () const |
| Return the scheduling class for this instruction. The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction. | |
| unsigned | getSize () const |
| Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode. | |
| int | findFirstPredOperandIdx () const |
| Find the index of the first operand in the operand list that is used to represent the predicate. It returns -1 if none is found. | |
Public Attributes | |
| unsigned short | Opcode |
| unsigned short | NumOperands |
| unsigned short | NumDefs |
| unsigned short | SchedClass |
| unsigned short | Size |
| unsigned | Flags |
| uint64_t | TSFlags |
| const uint16_t * | ImplicitUses |
| const uint16_t * | ImplicitDefs |
| const MCOperandInfo * | OpInfo |
| uint64_t | DeprecatedFeatureMask |
| bool(* | ComplexDeprecationInfo )(MCInst &, MCSubtargetInfo &, std::string &) |
Detailed Description
MCInstrDesc - Describe properties that are true of each instruction in the target description file. This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.
Definition at line 140 of file MCInstrDesc.h.
Member Function Documentation
| bool llvm::MCInstrDesc::canFoldAsLoad | ( | ) | const [inline] |
canFoldAsLoad - Return true for instructions that can be folded as memory operands in other instructions. The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.
Definition at line 359 of file MCInstrDesc.h.
References Flags, and llvm::MCID::FoldableAsLoad.
| int llvm::MCInstrDesc::findFirstPredOperandIdx | ( | ) | const [inline] |
Find the index of the first operand in the operand list that is used to represent the predicate. It returns -1 if none is found.
Definition at line 633 of file MCInstrDesc.h.
References getNumOperands(), isPredicable(), and OpInfo.
| bool llvm::MCInstrDesc::getDeprecatedInfo | ( | MCInst & | MI, |
| MCSubtargetInfo & | STI, | ||
| std::string & | Info | ||
| ) | const [inline] |
Returns true if a certain instruction is deprecated and if so returns the reason in Info.
Definition at line 171 of file MCInstrDesc.h.
References ComplexDeprecationInfo, DeprecatedFeatureMask, and llvm::MCSubtargetInfo::getFeatureBits().
| unsigned llvm::MCInstrDesc::getFlags | ( | ) | const [inline] |
Return flags of this instruction.
Definition at line 206 of file MCInstrDesc.h.
References Flags.
Referenced by llvm::MachineInstr::hasProperty().
| const uint16_t* llvm::MCInstrDesc::getImplicitDefs | ( | ) | const [inline] |
getImplicitDefs - Return a list of registers that are potentially written by any instance of this machine instruction. For example, on X86, many instructions implicitly set the flags register. In this case, they are marked as setting the FLAGS. Likewise, many instructions always deposit their result in a physical register. For example, the X86 divide instruction always deposits the quotient and remainder in the EAX/EDX registers. For that instruction, this will return a list containing the EAX/EDX/EFLAGS registers.
This method returns null if the instruction has no implicit defs.
Definition at line 573 of file MCInstrDesc.h.
References ImplicitDefs.
Referenced by getPhysicalRegisterVT(), HasImplicitCPSRDef(), and llvm::PPCInstrInfo::optimizeCompareInstr().
| const uint16_t* llvm::MCInstrDesc::getImplicitUses | ( | ) | const [inline] |
getImplicitUses - Return a list of registers that are potentially read by any instance of this machine instruction. For example, on X86, the "adc" instruction adds two register operands and adds the carry bit in from the flags register. In this case, the instruction is marked as implicitly reading the flags. Likewise, the variable shift instruction on X86 is marked as implicitly reading the 'CL' register, which it always does.
This method returns null if the instruction has no implicit uses.
Definition at line 551 of file MCInstrDesc.h.
References ImplicitUses.
Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().
| unsigned llvm::MCInstrDesc::getNumDefs | ( | ) | const [inline] |
Return the number of MachineOperands that are register definitions. Register definitions always occur at the start of the machine operand list. This is the number of "outs" in the .td file, and does not include implicit defs.
Definition at line 201 of file MCInstrDesc.h.
References NumDefs.
Referenced by CheckForPhysRegDependency(), llvm::TargetInstrInfo::commuteInstruction(), llvm::MachineInstr::defs(), llvm::FastISel::fastEmitInst_i(), llvm::FastISel::fastEmitInst_ii(), llvm::FastISel::fastEmitInst_r(), llvm::FastISel::fastEmitInst_rf(), llvm::FastISel::fastEmitInst_ri(), llvm::FastISel::fastEmitInst_rii(), llvm::FastISel::fastEmitInst_rr(), llvm::FastISel::fastEmitInst_rri(), llvm::FastISel::fastEmitInst_rrii(), llvm::FastISel::fastEmitInst_rrr(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), getPhysicalRegisterVT(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::ResourcePriorityQueue::initNumRegDefsLeft(), and llvm::MachineInstr::uses().
| unsigned llvm::MCInstrDesc::getNumImplicitDefs | ( | ) | const [inline] |
Return the number of implicit defs this instruct has.
Definition at line 578 of file MCInstrDesc.h.
References ImplicitDefs.
| unsigned llvm::MCInstrDesc::getNumImplicitUses | ( | ) | const [inline] |
Return the number of implicit uses this instruction has.
Definition at line 556 of file MCInstrDesc.h.
References ImplicitUses.
| unsigned llvm::MCInstrDesc::getNumOperands | ( | ) | const [inline] |
Return the number of declared MachineOperands for this MachineInstruction. Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well.
Definition at line 193 of file MCInstrDesc.h.
References NumOperands.
Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::MachineInstr::copyImplicitOps(), llvm::PPCInstrInfo::copyPhysReg(), Expand2AddrUndef(), findFirstPredOperandIdx(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), FuseTwoAddrInst(), llvm::ARMBaseInstrInfo::GetInstSizeInBytes(), getLSMultipleTransferSize(), getMemoryOpOffset(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::X86II::getOperandBias(), llvm::SIInstrInfo::getOpRegClass(), llvm::TargetInstrInfo::getRegClass(), getTargetMBB(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), llvm::ARMBaseInstrInfo::setExecutionDomain(), transferImpOps(), and llvm::SIInstrInfo::verifyInstruction().
| unsigned llvm::MCInstrDesc::getOpcode | ( | ) | const [inline] |
Return the opcode number for this descriptor.
Definition at line 184 of file MCInstrDesc.h.
References Opcode.
Referenced by adjustDefLatency(), llvm::AArch64InstrInfo::GetInstSizeInBytes(), llvm::MSP430InstrInfo::GetInstSizeInBytes(), llvm::ARMBaseInstrInfo::getOperandLatency(), hasRAWHazard(), and llvm::SIInstrInfo::verifyInstruction().
| int llvm::MCInstrDesc::getOperandConstraint | ( | unsigned | OpNum, |
| MCOI::OperandConstraint | Constraint | ||
| ) | const [inline] |
Returns the value of the specific constraint if it is set. Returns -1 if it is not set.
Definition at line 159 of file MCInstrDesc.h.
References llvm::MCOperandInfo::Constraints, NumOperands, and OpInfo.
Referenced by llvm::PPCInstrInfo::commuteInstruction(), llvm::TargetInstrInfo::commuteInstruction(), DetermineREXPrefix(), and llvm::X86II::getOperandBias().
| unsigned llvm::MCInstrDesc::getSchedClass | ( | ) | const [inline] |
Return the scheduling class for this instruction. The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction.
Definition at line 620 of file MCInstrDesc.h.
References SchedClass.
Referenced by llvm::DFAPacketizer::canReserveResources(), llvm::TargetSchedModel::computeInstrLatency(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetInstrInfo::computeOperandLatency(), llvm::ScoreboardHazardRecognizer::EmitInstruction(), llvm::ScoreboardHazardRecognizer::getHazardType(), llvm::TargetInstrInfo::getInstrLatency(), getItineraryLatency(), getLatency(), llvm::TargetSchedModel::getNumMicroOps(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::TargetInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getOperandLatency(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::TargetInstrInfo::hasLowDefLatency(), llvm::DFAPacketizer::reserveResources(), and llvm::TargetSchedModel::resolveSchedClass().
| unsigned llvm::MCInstrDesc::getSize | ( | ) | const [inline] |
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode.
Definition at line 626 of file MCInstrDesc.h.
References Size.
Referenced by llvm::MipsInstrInfo::GetInstSizeInBytes(), llvm::ARMBaseInstrInfo::GetInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), and llvm::PPCInstrInfo::GetInstSizeInBytes().
| bool llvm::MCInstrDesc::hasDefOfPhysReg | ( | const MCInst & | MI, |
| unsigned | Reg, | ||
| const MCRegisterInfo & | RI | ||
| ) | const [inline] |
Return true if this instruction defines the specified physical register, either explicitly or implicitly.
Definition at line 607 of file MCInstrDesc.h.
References llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), hasImplicitDefOfPhysReg(), llvm::MCOperand::isReg(), llvm::MCRegisterInfo::isSubRegisterEq(), and NumDefs.
Referenced by mayAffectControlFlow().
| bool llvm::MCInstrDesc::hasDelaySlot | ( | ) | const [inline] |
hasDelaySlot - Returns true if the specified instruction has a delay slot which must be filled by the code generator.
Definition at line 347 of file MCInstrDesc.h.
References llvm::MCID::DelaySlot, and Flags.
| bool llvm::MCInstrDesc::hasExtraDefRegAllocReq | ( | ) | const [inline] |
hasExtraDefRegAllocReq - Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.
Definition at line 537 of file MCInstrDesc.h.
References llvm::MCID::ExtraDefRegAllocReq, and Flags.
| bool llvm::MCInstrDesc::hasExtraSrcRegAllocReq | ( | ) | const [inline] |
hasExtraSrcRegAllocReq - Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.
Definition at line 527 of file MCInstrDesc.h.
References llvm::MCID::ExtraSrcRegAllocReq, and Flags.
| bool llvm::MCInstrDesc::hasImplicitDefOfPhysReg | ( | unsigned | Reg, |
| const MCRegisterInfo * | MRI = nullptr |
||
| ) | const [inline] |
Return true if this instruction implicitly defines the specified physical register.
Definition at line 596 of file MCInstrDesc.h.
References ImplicitDefs.
Referenced by hasDefOfPhysReg().
| bool llvm::MCInstrDesc::hasImplicitUseOfPhysReg | ( | unsigned | Reg | ) | const [inline] |
Return true if this instruction implicitly uses the specified physical register.
Definition at line 587 of file MCInstrDesc.h.
References ImplicitUses.
| bool llvm::MCInstrDesc::hasOptionalDef | ( | ) | const [inline] |
Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set.
Definition at line 218 of file MCInstrDesc.h.
References Flags, and llvm::MCID::HasOptionalDef.
Referenced by llvm::ARMBaseInstrInfo::FoldImmediate().
| bool llvm::MCInstrDesc::hasPostISelHook | ( | ) | const [inline] |
hasPostISelHook - Return true if this instruction requires *adjustment* after instruction selection by calling a target hook. For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.
Definition at line 493 of file MCInstrDesc.h.
References Flags, and llvm::MCID::HasPostISelHook.
| bool llvm::MCInstrDesc::hasUnmodeledSideEffects | ( | ) | const [inline] |
hasUnmodeledSideEffects - Return true if this instruction has side effects that are not modeled by other flags. This does not return true for instructions whose effects are captured by:
1. Their operand list and implicit definition/use list. Register use/def info is explicit for instructions. 2. Memory accesses. Use mayLoad/mayStore. 3. Calling, branching, returning: use isCall/isReturn/isBranch.
Examples of side effects would be modifying 'invisible' machine state like a control register, flushing a cache, modifying a register invisible to LLVM, etc.
Definition at line 437 of file MCInstrDesc.h.
References Flags, and llvm::MCID::UnmodeledSideEffects.
| bool llvm::MCInstrDesc::isAsCheapAsAMove | ( | ) | const [inline] |
isAsCheapAsAMove - Returns true if this instruction has the same cost (or less) than a move instruction. This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.
This method could be called by interface TargetInstrInfo::isAsCheapAsAMove for different subtargets.
Definition at line 517 of file MCInstrDesc.h.
References llvm::MCID::CheapAsAMove, and Flags.
| bool llvm::MCInstrDesc::isBarrier | ( | ) | const [inline] |
Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.
Definition at line 242 of file MCInstrDesc.h.
References llvm::MCID::Barrier, and Flags.
Referenced by isConditionalBranch(), and isUnconditionalBranch().
| bool llvm::MCInstrDesc::isBitcast | ( | ) | const [inline] |
Return true if this instruction is a bitcast instruction.
Definition at line 329 of file MCInstrDesc.h.
References llvm::MCID::Bitcast, and Flags.
| bool llvm::MCInstrDesc::isBranch | ( | ) | const [inline] |
Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.
Definition at line 260 of file MCInstrDesc.h.
References llvm::MCID::Branch, and Flags.
Referenced by llvm::PPCDispatchGroupSBHazardRecognizer::EmitInstruction(), llvm::HexagonInstrInfo::isBranch(), isConditionalBranch(), isUnconditionalBranch(), and mayAffectControlFlow().
| bool llvm::MCInstrDesc::isCall | ( | ) | const [inline] |
Return true if the instruction is a call.
Definition at line 235 of file MCInstrDesc.h.
References llvm::Call, and Flags.
Referenced by IsControlFlow(), mayAffectControlFlow(), llvm::SelectionDAGISel::runOnMachineFunction(), and llvm::ResourcePriorityQueue::SUSchedulingCost().
| bool llvm::MCInstrDesc::isCommutable | ( | ) | const [inline] |
isCommutable - Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.
Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.
Definition at line 455 of file MCInstrDesc.h.
References llvm::MCID::Commutable, and Flags.
| bool llvm::MCInstrDesc::isCompare | ( | ) | const [inline] |
Return true if this instruction is a comparison.
Definition at line 318 of file MCInstrDesc.h.
References llvm::MCID::Compare, and Flags.
| bool llvm::MCInstrDesc::isConditionalBranch | ( | ) | const [inline] |
Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 274 of file MCInstrDesc.h.
References isBarrier(), isBranch(), and isIndirectBranch().
| bool llvm::MCInstrDesc::isConvertibleTo3Addr | ( | ) | const [inline] |
isConvertibleTo3Addr - Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.
If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).
Definition at line 473 of file MCInstrDesc.h.
References llvm::MCID::ConvertibleTo3Addr, and Flags.
| bool llvm::MCInstrDesc::isExtractSubregLike | ( | ) | const [inline] |
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1.
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.
Definition at line 386 of file MCInstrDesc.h.
References llvm::MCID::ExtractSubreg, and Flags.
| bool llvm::MCInstrDesc::isIndirectBranch | ( | ) | const [inline] |
Return true if this is an indirect branch, such as a branch through a register.
Definition at line 266 of file MCInstrDesc.h.
References Flags, and llvm::MCID::IndirectBranch.
Referenced by isConditionalBranch(), isUnconditionalBranch(), and mayAffectControlFlow().
| bool llvm::MCInstrDesc::isInsertSubregLike | ( | ) | const [inline] |
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.
Definition at line 400 of file MCInstrDesc.h.
References Flags, and llvm::MCID::InsertSubreg.
| bool llvm::MCInstrDesc::isMoveImmediate | ( | ) | const [inline] |
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition at line 324 of file MCInstrDesc.h.
References Flags, and llvm::MCID::MoveImm.
| bool llvm::MCInstrDesc::isNotDuplicable | ( | ) | const [inline] |
Return true if this instruction cannot be safely duplicated. For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.
Definition at line 341 of file MCInstrDesc.h.
References Flags, and llvm::MCID::NotDuplicable.
| bool llvm::MCInstrDesc::isPredicable | ( | ) | const [inline] |
Return true if this instruction has a predicate operand that controls execution. It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.
Definition at line 313 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Predicable.
Referenced by findFirstPredOperandIdx(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::HexagonInstrInfo::isPredicable(), llvm::AMDGPUInstrInfo::isPredicable(), and llvm::TargetInstrInfo::isPredicable().
| bool llvm::MCInstrDesc::isPseudo | ( | ) | const [inline] |
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition at line 225 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Pseudo.
Referenced by llvm::PPCInstrInfo::FoldImmediate(), and llvm::HexagonMCInst::isCanon().
| bool llvm::MCInstrDesc::isRegSequenceLike | ( | ) | const [inline] |
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.
Definition at line 373 of file MCInstrDesc.h.
References Flags, and llvm::MCID::RegSequence.
| bool llvm::MCInstrDesc::isRematerializable | ( | ) | const [inline] |
isRematerializable - Returns true if this instruction is a candidate for remat. This flag is only used in TargetInstrInfo method isTriviallyRematerializable.
If this flag is set, the isReallyTriviallyReMaterializable() or isReallyTriviallyReMaterializableGeneric methods are called to verify the instruction is really rematable.
Definition at line 504 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Rematerializable.
Referenced by llvm::TargetInstrInfo::isTriviallyReMaterializable().
| bool llvm::MCInstrDesc::isReturn | ( | ) | const [inline] |
Return true if the instruction is a return.
Definition at line 230 of file MCInstrDesc.h.
References Flags, and llvm::GC::Return.
Referenced by mayAffectControlFlow(), and llvm::SelectionDAGISel::runOnMachineFunction().
| bool llvm::MCInstrDesc::isSelect | ( | ) | const [inline] |
Return true if this is a select instruction.
Definition at line 334 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Select.
Referenced by llvm::TargetInstrInfo::analyzeSelect().
| bool llvm::MCInstrDesc::isTerminator | ( | ) | const [inline] |
Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions.
Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.
Definition at line 252 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Terminator.
Referenced by IsControlFlow(), and llvm::HexagonInstrInfo::isSchedulingBoundary().
| bool llvm::MCInstrDesc::isUnconditionalBranch | ( | ) | const [inline] |
Return true if this is a branch which always transfers control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 282 of file MCInstrDesc.h.
References isBarrier(), isBranch(), and isIndirectBranch().
| bool llvm::MCInstrDesc::isVariadic | ( | ) | const [inline] |
Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).
Definition at line 212 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Variadic.
Referenced by llvm::SIInstrInfo::verifyInstruction().
| bool llvm::MCInstrDesc::mayAffectControlFlow | ( | const MCInst & | MI, |
| const MCRegisterInfo & | RI | ||
| ) | const [inline] |
Return true if this is a branch or an instruction which directly writes to the program counter. Considered 'may' affect rather than 'does' affect as things like predication are not taken into account.
Definition at line 289 of file MCInstrDesc.h.
References llvm::MCInst::getNumOperands(), llvm::MCInst::getOperand(), llvm::MCRegisterInfo::getProgramCounter(), llvm::MCOperand::getReg(), hasDefOfPhysReg(), isBranch(), isCall(), isIndirectBranch(), llvm::MCOperand::isReg(), isReturn(), llvm::MCRegisterInfo::isSubRegisterEq(), and NumOperands.
| bool llvm::MCInstrDesc::mayLoad | ( | ) | const [inline] |
Return true if this instruction could possibly read memory. Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.
Definition at line 411 of file MCInstrDesc.h.
References Flags, and llvm::MCID::MayLoad.
Referenced by llvm::addFrameReference(), llvm::HexagonInstrInfo::getNonExtOpcode(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), GetPostIncrementOperand(), llvm::HexagonInstrInfo::NonExtEquivalentExists(), and llvm::SelectionDAGISel::SelectCodeCommon().
| bool llvm::MCInstrDesc::mayStore | ( | ) | const [inline] |
Return true if this instruction could possibly modify memory. Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.
Definition at line 420 of file MCInstrDesc.h.
References Flags, and llvm::MCID::MayStore.
Referenced by llvm::addFrameReference(), llvm::HexagonInstrInfo::getNonExtOpcode(), llvm::ARMBaseInstrInfo::getNumMicroOps(), GetPostIncrementOperand(), llvm::HexagonInstrInfo::NonExtEquivalentExists(), and llvm::SelectionDAGISel::SelectCodeCommon().
| bool llvm::MCInstrDesc::usesCustomInsertionHook | ( | ) | const [inline] |
usesCustomInsertionHook - Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.
If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.
Definition at line 485 of file MCInstrDesc.h.
References Flags, and llvm::MCID::UsesCustomInserter.
Member Data Documentation
| bool(* llvm::MCInstrDesc::ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &) |
Definition at line 155 of file MCInstrDesc.h.
Referenced by getDeprecatedInfo().
Definition at line 152 of file MCInstrDesc.h.
Referenced by getDeprecatedInfo().
Definition at line 147 of file MCInstrDesc.h.
Referenced by canFoldAsLoad(), getFlags(), hasDelaySlot(), hasExtraDefRegAllocReq(), hasExtraSrcRegAllocReq(), hasOptionalDef(), hasPostISelHook(), hasUnmodeledSideEffects(), isAsCheapAsAMove(), isBarrier(), isBitcast(), isBranch(), isCall(), isCommutable(), isCompare(), isConvertibleTo3Addr(), isExtractSubregLike(), isIndirectBranch(), isInsertSubregLike(), isMoveImmediate(), isNotDuplicable(), isPredicable(), isPseudo(), isRegSequenceLike(), isRematerializable(), isReturn(), isSelect(), isTerminator(), isVariadic(), mayLoad(), mayStore(), and usesCustomInsertionHook().
| const uint16_t* llvm::MCInstrDesc::ImplicitDefs |
Definition at line 150 of file MCInstrDesc.h.
Referenced by CheckForPhysRegDependency(), llvm::FastISel::fastEmitInst_i(), llvm::FastISel::fastEmitInst_ii(), llvm::FastISel::fastEmitInst_r(), llvm::FastISel::fastEmitInst_rf(), llvm::FastISel::fastEmitInst_ri(), llvm::FastISel::fastEmitInst_rii(), llvm::FastISel::fastEmitInst_rr(), llvm::FastISel::fastEmitInst_rri(), llvm::FastISel::fastEmitInst_rrii(), llvm::FastISel::fastEmitInst_rrr(), getImplicitDefs(), getNumImplicitDefs(), getPhysicalRegisterVT(), hasImplicitDefOfPhysReg(), and llvm::PPCInstrInfo::optimizeCompareInstr().
| const uint16_t* llvm::MCInstrDesc::ImplicitUses |
Definition at line 149 of file MCInstrDesc.h.
Referenced by getImplicitUses(), getNumImplicitUses(), hasImplicitUseOfPhysReg(), and llvm::PPCInstrInfo::optimizeCompareInstr().
Definition at line 144 of file MCInstrDesc.h.
Referenced by getNumDefs(), and hasDefOfPhysReg().
Definition at line 143 of file MCInstrDesc.h.
Referenced by AddThumb1SBit(), getNumOperands(), getOperandConstraint(), and mayAffectControlFlow().
Definition at line 142 of file MCInstrDesc.h.
Referenced by llvm::ScoreboardHazardRecognizer::EmitInstruction(), getOpcode(), llvm::MachineInstr::getOpcode(), and llvm::ARMBaseInstrInfo::getOperandLatency().
Definition at line 151 of file MCInstrDesc.h.
Referenced by AddThumb1SBit(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::TargetSchedModel::computeOperandLatency(), findFirstPredOperandIdx(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::PPCInstrInfo::FoldImmediate(), getOperandConstraint(), llvm::SIInstrInfo::getOpRegClass(), llvm::TargetInstrInfo::getRegClass(), llvm::SIInstrInfo::isOperandLegal(), and llvm::SIInstrInfo::verifyInstruction().
Definition at line 145 of file MCInstrDesc.h.
Referenced by getSchedClass().
Definition at line 146 of file MCInstrDesc.h.
Referenced by getSize().
| uint64_t llvm::MCInstrDesc::TSFlags |
Definition at line 148 of file MCInstrDesc.h.
Referenced by llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::HexagonInstrInfo::getAddrMode(), llvm::HexagonMCInst::getBitCount(), llvm::HexagonMCInst::getCExtOpNum(), llvm::HexagonInstrInfo::getCExtOpNum(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::ARMHazardRecognizer::getHazardType(), llvm::MSP430InstrInfo::GetInstSizeInBytes(), llvm::HexagonInstrInfo::getMaxValue(), llvm::HexagonInstrInfo::getMinValue(), llvm::HexagonMCInst::getNewValue(), llvm::SystemZInstrInfo::getOpcodeForOffset(), getTruncatedShiftCount(), llvm::HexagonMCInst::getType(), llvm::HexagonMCInst::hasNewValue(), hasRAWHazard(), llvm::HexagonInstrInfo::isConstExtended(), llvm::HexagonInstrInfo::isExtendable(), llvm::HexagonInstrInfo::isExtended(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), llvm::NVPTXInstrInfo::isLoadInstr(), llvm::NVPTXInstrInfo::isMoveInstr(), llvm::HexagonMCInst::isNewValue(), llvm::HexagonInstrInfo::isNewValue(), llvm::HexagonInstrInfo::isNewValueStore(), llvm::HexagonInstrInfo::isOperandExtended(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonInstrInfo::isPredicatedNew(), llvm::HexagonInstrInfo::isPredicatedTrue(), isSimpleBD12Move(), isSimpleMove(), llvm::HexagonMCInst::isSolo(), llvm::NVPTXInstrInfo::isStoreInstr(), llvm::HexagonInstrInfo::mayBeNewStore(), llvm::SystemZInstrInfo::optimizeCompareInstr(), llvm::rewriteARMFrameIndex(), llvm::Thumb1RegisterInfo::rewriteFrameIndex(), and llvm::rewriteT2FrameIndex().
The documentation for this class was generated from the following file:
1.7.6.1