LLVM API Documentation
00001 //===-- OptimizePHIs.cpp - Optimize machine instruction PHIs --------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This pass optimizes machine instruction PHIs to take advantage of 00011 // opportunities created during DAG legalization. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #include "llvm/CodeGen/Passes.h" 00016 #include "llvm/ADT/SmallPtrSet.h" 00017 #include "llvm/ADT/Statistic.h" 00018 #include "llvm/CodeGen/MachineFunctionPass.h" 00019 #include "llvm/CodeGen/MachineInstr.h" 00020 #include "llvm/CodeGen/MachineRegisterInfo.h" 00021 #include "llvm/IR/Function.h" 00022 #include "llvm/Target/TargetInstrInfo.h" 00023 #include "llvm/Target/TargetSubtargetInfo.h" 00024 using namespace llvm; 00025 00026 #define DEBUG_TYPE "phi-opt" 00027 00028 STATISTIC(NumPHICycles, "Number of PHI cycles replaced"); 00029 STATISTIC(NumDeadPHICycles, "Number of dead PHI cycles"); 00030 00031 namespace { 00032 class OptimizePHIs : public MachineFunctionPass { 00033 MachineRegisterInfo *MRI; 00034 const TargetInstrInfo *TII; 00035 00036 public: 00037 static char ID; // Pass identification 00038 OptimizePHIs() : MachineFunctionPass(ID) { 00039 initializeOptimizePHIsPass(*PassRegistry::getPassRegistry()); 00040 } 00041 00042 bool runOnMachineFunction(MachineFunction &MF) override; 00043 00044 void getAnalysisUsage(AnalysisUsage &AU) const override { 00045 AU.setPreservesCFG(); 00046 MachineFunctionPass::getAnalysisUsage(AU); 00047 } 00048 00049 private: 00050 typedef SmallPtrSet<MachineInstr*, 16> InstrSet; 00051 typedef SmallPtrSetIterator<MachineInstr*> InstrSetIterator; 00052 00053 bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg, 00054 InstrSet &PHIsInCycle); 00055 bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle); 00056 bool OptimizeBB(MachineBasicBlock &MBB); 00057 }; 00058 } 00059 00060 char OptimizePHIs::ID = 0; 00061 char &llvm::OptimizePHIsID = OptimizePHIs::ID; 00062 INITIALIZE_PASS(OptimizePHIs, "opt-phis", 00063 "Optimize machine instruction PHIs", false, false) 00064 00065 bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) { 00066 if (skipOptnoneFunction(*Fn.getFunction())) 00067 return false; 00068 00069 MRI = &Fn.getRegInfo(); 00070 TII = Fn.getSubtarget().getInstrInfo(); 00071 00072 // Find dead PHI cycles and PHI cycles that can be replaced by a single 00073 // value. InstCombine does these optimizations, but DAG legalization may 00074 // introduce new opportunities, e.g., when i64 values are split up for 00075 // 32-bit targets. 00076 bool Changed = false; 00077 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 00078 Changed |= OptimizeBB(*I); 00079 00080 return Changed; 00081 } 00082 00083 /// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands 00084 /// are copies of SingleValReg, possibly via copies through other PHIs. If 00085 /// SingleValReg is zero on entry, it is set to the register with the single 00086 /// non-copy value. PHIsInCycle is a set used to keep track of the PHIs that 00087 /// have been scanned. 00088 bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI, 00089 unsigned &SingleValReg, 00090 InstrSet &PHIsInCycle) { 00091 assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction"); 00092 unsigned DstReg = MI->getOperand(0).getReg(); 00093 00094 // See if we already saw this register. 00095 if (!PHIsInCycle.insert(MI)) 00096 return true; 00097 00098 // Don't scan crazily complex things. 00099 if (PHIsInCycle.size() == 16) 00100 return false; 00101 00102 // Scan the PHI operands. 00103 for (unsigned i = 1; i != MI->getNumOperands(); i += 2) { 00104 unsigned SrcReg = MI->getOperand(i).getReg(); 00105 if (SrcReg == DstReg) 00106 continue; 00107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 00108 00109 // Skip over register-to-register moves. 00110 if (SrcMI && SrcMI->isCopy() && 00111 !SrcMI->getOperand(0).getSubReg() && 00112 !SrcMI->getOperand(1).getSubReg() && 00113 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg())) 00114 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 00115 if (!SrcMI) 00116 return false; 00117 00118 if (SrcMI->isPHI()) { 00119 if (!IsSingleValuePHICycle(SrcMI, SingleValReg, PHIsInCycle)) 00120 return false; 00121 } else { 00122 // Fail if there is more than one non-phi/non-move register. 00123 if (SingleValReg != 0) 00124 return false; 00125 SingleValReg = SrcReg; 00126 } 00127 } 00128 return true; 00129 } 00130 00131 /// IsDeadPHICycle - Check if the register defined by a PHI is only used by 00132 /// other PHIs in a cycle. 00133 bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) { 00134 assert(MI->isPHI() && "IsDeadPHICycle expects a PHI instruction"); 00135 unsigned DstReg = MI->getOperand(0).getReg(); 00136 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && 00137 "PHI destination is not a virtual register"); 00138 00139 // See if we already saw this register. 00140 if (!PHIsInCycle.insert(MI)) 00141 return true; 00142 00143 // Don't scan crazily complex things. 00144 if (PHIsInCycle.size() == 16) 00145 return false; 00146 00147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { 00148 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle)) 00149 return false; 00150 } 00151 00152 return true; 00153 } 00154 00155 /// OptimizeBB - Remove dead PHI cycles and PHI cycles that can be replaced by 00156 /// a single value. 00157 bool OptimizePHIs::OptimizeBB(MachineBasicBlock &MBB) { 00158 bool Changed = false; 00159 for (MachineBasicBlock::iterator 00160 MII = MBB.begin(), E = MBB.end(); MII != E; ) { 00161 MachineInstr *MI = &*MII++; 00162 if (!MI->isPHI()) 00163 break; 00164 00165 // Check for single-value PHI cycles. 00166 unsigned SingleValReg = 0; 00167 InstrSet PHIsInCycle; 00168 if (IsSingleValuePHICycle(MI, SingleValReg, PHIsInCycle) && 00169 SingleValReg != 0) { 00170 unsigned OldReg = MI->getOperand(0).getReg(); 00171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) 00172 continue; 00173 00174 MRI->replaceRegWith(OldReg, SingleValReg); 00175 MI->eraseFromParent(); 00176 ++NumPHICycles; 00177 Changed = true; 00178 continue; 00179 } 00180 00181 // Check for dead PHI cycles. 00182 PHIsInCycle.clear(); 00183 if (IsDeadPHICycle(MI, PHIsInCycle)) { 00184 for (InstrSetIterator PI = PHIsInCycle.begin(), PE = PHIsInCycle.end(); 00185 PI != PE; ++PI) { 00186 MachineInstr *PhiMI = *PI; 00187 if (&*MII == PhiMI) 00188 ++MII; 00189 PhiMI->eraseFromParent(); 00190 } 00191 ++NumDeadPHICycles; 00192 Changed = true; 00193 } 00194 } 00195 return Changed; 00196 }