#include <PPCHazardRecognizers.h>
Public Member Functions | |
| PPCHazardRecognizer970 (const ScheduleDAG &DAG) | |
| HazardType | getHazardType (SUnit *SU, int Stalls) override |
| void | EmitInstruction (SUnit *SU) override |
| void | AdvanceCycle () override |
| void | Reset () override |
Detailed Description
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on the PowerPC 970 (aka G5) processor. This promotes good dispatch group formation and implements noop insertion to avoid structural hazards that cause significant performance penalties (e.g. setting the CTR register then branching through it within a dispatch group), or storing then loading from the same address within a dispatch group.
Definition at line 56 of file PPCHazardRecognizers.h.
Constructor & Destructor Documentation
Definition at line 262 of file PPCHazardRecognizers.cpp.
Member Function Documentation
| void PPCHazardRecognizer970::AdvanceCycle | ( | ) | [override, virtual] |
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot issue in the current cycle, either because of latency or resource conflicts. This should increment the internal state of the hazard recognizer so that previously "Hazard" instructions will now not be hazards.
Reimplemented from llvm::ScheduleHazardRecognizer.
Definition at line 423 of file PPCHazardRecognizers.cpp.
| void PPCHazardRecognizer970::EmitInstruction | ( | SUnit * | ) | [override, virtual] |
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard state.
Reimplemented from llvm::ScheduleHazardRecognizer.
Definition at line 385 of file PPCHazardRecognizers.cpp.
References llvm::SUnit::getInstr(), llvm::MachineMemOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineMemOperand::getSize(), llvm::MachineMemOperand::getValue(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::memoperands_begin(), llvm::AArch64CC::MI, llvm::PPCISD::MTCTR, llvm::PPCII::PPC970_BRU, and llvm::PPCII::PPC970_Pseudo.
| ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::getHazardType | ( | SUnit * | SU, |
| int | Stalls | ||
| ) | [override, virtual] |
getHazardType - We return hazard for any non-branch instruction that would terminate the dispatch group. We turn NoopHazard for any instructions that wouldn't terminate the dispatch group that would cause a pipeline flush.
Reimplemented from llvm::ScheduleHazardRecognizer.
Definition at line 325 of file PPCHazardRecognizers.cpp.
References llvm::PPCISD::BCTRL, llvm::SUnit::getInstr(), llvm::MachineMemOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineMemOperand::getSize(), llvm::MachineMemOperand::getValue(), llvm::ScheduleHazardRecognizer::Hazard, llvm::MachineInstr::isDebugValue(), llvm_unreachable, llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), llvm::AArch64CC::MI, llvm::ScheduleHazardRecognizer::NoHazard, llvm::ScheduleHazardRecognizer::NoopHazard, llvm::PPCII::PPC970_BRU, llvm::PPCII::PPC970_CRU, llvm::PPCII::PPC970_FPU, llvm::PPCII::PPC970_FXU, llvm::PPCII::PPC970_LSU, llvm::PPCII::PPC970_Pseudo, llvm::PPCII::PPC970_VALU, and llvm::PPCII::PPC970_VPERM.
| void PPCHazardRecognizer970::Reset | ( | ) | [override, virtual] |
Reset - This callback is invoked when a new block of instructions is about to be schedule. The hazard state should be set to an initialized state.
Reimplemented from llvm::ScheduleHazardRecognizer.
Definition at line 430 of file PPCHazardRecognizers.cpp.
The documentation for this class was generated from the following files:
1.7.6.1